1 #ifndef QEMU_PCI_H 2 #define QEMU_PCI_H 3 4 #include "qemu-common.h" 5 6 #include "hw/qdev.h" 7 #include "exec/memory.h" 8 #include "sysemu/dma.h" 9 #include "qapi/error.h" 10 11 /* PCI includes legacy ISA access. */ 12 #include "hw/isa/isa.h" 13 14 #include "hw/pci/pcie.h" 15 16 /* PCI bus */ 17 18 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 19 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 20 #define PCI_FUNC(devfn) ((devfn) & 0x07) 21 #define PCI_SLOT_MAX 32 22 #define PCI_FUNC_MAX 8 23 24 /* Class, Vendor and Device IDs from Linux's pci_ids.h */ 25 #include "hw/pci/pci_ids.h" 26 27 /* QEMU-specific Vendor and Device ID definitions */ 28 29 /* IBM (0x1014) */ 30 #define PCI_DEVICE_ID_IBM_440GX 0x027f 31 #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff 32 33 /* Hitachi (0x1054) */ 34 #define PCI_VENDOR_ID_HITACHI 0x1054 35 #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e 36 37 /* Apple (0x106b) */ 38 #define PCI_DEVICE_ID_APPLE_343S1201 0x0010 39 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e 40 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f 41 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022 42 #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f 43 44 /* Realtek (0x10ec) */ 45 #define PCI_DEVICE_ID_REALTEK_8029 0x8029 46 47 /* Xilinx (0x10ee) */ 48 #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300 49 50 /* Marvell (0x11ab) */ 51 #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620 52 53 /* QEMU/Bochs VGA (0x1234) */ 54 #define PCI_VENDOR_ID_QEMU 0x1234 55 #define PCI_DEVICE_ID_QEMU_VGA 0x1111 56 57 /* VMWare (0x15ad) */ 58 #define PCI_VENDOR_ID_VMWARE 0x15ad 59 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 60 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710 61 #define PCI_DEVICE_ID_VMWARE_NET 0x0720 62 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730 63 #define PCI_DEVICE_ID_VMWARE_PVSCSI 0x07C0 64 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729 65 #define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0 66 67 /* Intel (0x8086) */ 68 #define PCI_DEVICE_ID_INTEL_82551IT 0x1209 69 #define PCI_DEVICE_ID_INTEL_82557 0x1229 70 #define PCI_DEVICE_ID_INTEL_82801IR 0x2922 71 72 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */ 73 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 74 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 75 #define PCI_SUBDEVICE_ID_QEMU 0x1100 76 77 #define PCI_DEVICE_ID_VIRTIO_NET 0x1000 78 #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001 79 #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002 80 #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003 81 #define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004 82 #define PCI_DEVICE_ID_VIRTIO_RNG 0x1005 83 #define PCI_DEVICE_ID_VIRTIO_9P 0x1009 84 85 #define PCI_VENDOR_ID_REDHAT 0x1b36 86 #define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001 87 #define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002 88 #define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003 89 #define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004 90 #define PCI_DEVICE_ID_REDHAT_TEST 0x0005 91 #define PCI_DEVICE_ID_REDHAT_ROCKER 0x0006 92 #define PCI_DEVICE_ID_REDHAT_SDHCI 0x0007 93 #define PCI_DEVICE_ID_REDHAT_PCIE_HOST 0x0008 94 #define PCI_DEVICE_ID_REDHAT_PXB 0x0009 95 #define PCI_DEVICE_ID_REDHAT_BRIDGE_SEAT 0x000a 96 #define PCI_DEVICE_ID_REDHAT_QXL 0x0100 97 98 #define FMT_PCIBUS PRIx64 99 100 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, 101 uint32_t address, uint32_t data, int len); 102 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev, 103 uint32_t address, int len); 104 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, 105 pcibus_t addr, pcibus_t size, int type); 106 typedef void PCIUnregisterFunc(PCIDevice *pci_dev); 107 108 typedef struct PCIIORegion { 109 pcibus_t addr; /* current PCI mapping address. -1 means not mapped */ 110 #define PCI_BAR_UNMAPPED (~(pcibus_t)0) 111 pcibus_t size; 112 uint8_t type; 113 MemoryRegion *memory; 114 MemoryRegion *address_space; 115 } PCIIORegion; 116 117 #define PCI_ROM_SLOT 6 118 #define PCI_NUM_REGIONS 7 119 120 enum { 121 QEMU_PCI_VGA_MEM, 122 QEMU_PCI_VGA_IO_LO, 123 QEMU_PCI_VGA_IO_HI, 124 QEMU_PCI_VGA_NUM_REGIONS, 125 }; 126 127 #define QEMU_PCI_VGA_MEM_BASE 0xa0000 128 #define QEMU_PCI_VGA_MEM_SIZE 0x20000 129 #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0 130 #define QEMU_PCI_VGA_IO_LO_SIZE 0xc 131 #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0 132 #define QEMU_PCI_VGA_IO_HI_SIZE 0x20 133 134 #include "hw/pci/pci_regs.h" 135 136 /* PCI HEADER_TYPE */ 137 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80 138 139 /* Size of the standard PCI config header */ 140 #define PCI_CONFIG_HEADER_SIZE 0x40 141 /* Size of the standard PCI config space */ 142 #define PCI_CONFIG_SPACE_SIZE 0x100 143 /* Size of the standard PCIe config space: 4KB */ 144 #define PCIE_CONFIG_SPACE_SIZE 0x1000 145 146 #define PCI_NUM_PINS 4 /* A-D */ 147 148 /* Bits in cap_present field. */ 149 enum { 150 QEMU_PCI_CAP_MSI = 0x1, 151 QEMU_PCI_CAP_MSIX = 0x2, 152 QEMU_PCI_CAP_EXPRESS = 0x4, 153 154 /* multifunction capable device */ 155 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3 156 QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR), 157 158 /* command register SERR bit enabled */ 159 #define QEMU_PCI_CAP_SERR_BITNR 4 160 QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR), 161 /* Standard hot plug controller. */ 162 #define QEMU_PCI_SHPC_BITNR 5 163 QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR), 164 #define QEMU_PCI_SLOTID_BITNR 6 165 QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR), 166 /* PCI Express capability - Power Controller Present */ 167 #define QEMU_PCIE_SLTCAP_PCP_BITNR 7 168 QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR), 169 }; 170 171 #define TYPE_PCI_DEVICE "pci-device" 172 #define PCI_DEVICE(obj) \ 173 OBJECT_CHECK(PCIDevice, (obj), TYPE_PCI_DEVICE) 174 #define PCI_DEVICE_CLASS(klass) \ 175 OBJECT_CLASS_CHECK(PCIDeviceClass, (klass), TYPE_PCI_DEVICE) 176 #define PCI_DEVICE_GET_CLASS(obj) \ 177 OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE) 178 179 typedef struct PCIINTxRoute { 180 enum { 181 PCI_INTX_ENABLED, 182 PCI_INTX_INVERTED, 183 PCI_INTX_DISABLED, 184 } mode; 185 int irq; 186 } PCIINTxRoute; 187 188 typedef struct PCIDeviceClass { 189 DeviceClass parent_class; 190 191 void (*realize)(PCIDevice *dev, Error **errp); 192 int (*init)(PCIDevice *dev);/* TODO convert to realize() and remove */ 193 PCIUnregisterFunc *exit; 194 PCIConfigReadFunc *config_read; 195 PCIConfigWriteFunc *config_write; 196 197 uint16_t vendor_id; 198 uint16_t device_id; 199 uint8_t revision; 200 uint16_t class_id; 201 uint16_t subsystem_vendor_id; /* only for header type = 0 */ 202 uint16_t subsystem_id; /* only for header type = 0 */ 203 204 /* 205 * pci-to-pci bridge or normal device. 206 * This doesn't mean pci host switch. 207 * When card bus bridge is supported, this would be enhanced. 208 */ 209 int is_bridge; 210 211 /* pcie stuff */ 212 int is_express; /* is this device pci express? */ 213 214 /* rom bar */ 215 const char *romfile; 216 } PCIDeviceClass; 217 218 typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev); 219 typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector, 220 MSIMessage msg); 221 typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector); 222 typedef void (*MSIVectorPollNotifier)(PCIDevice *dev, 223 unsigned int vector_start, 224 unsigned int vector_end); 225 226 struct PCIDevice { 227 DeviceState qdev; 228 229 /* PCI config space */ 230 uint8_t *config; 231 232 /* Used to enable config checks on load. Note that writable bits are 233 * never checked even if set in cmask. */ 234 uint8_t *cmask; 235 236 /* Used to implement R/W bytes */ 237 uint8_t *wmask; 238 239 /* Used to implement RW1C(Write 1 to Clear) bytes */ 240 uint8_t *w1cmask; 241 242 /* Used to allocate config space for capabilities. */ 243 uint8_t *used; 244 245 /* the following fields are read only */ 246 PCIBus *bus; 247 int32_t devfn; 248 char name[64]; 249 PCIIORegion io_regions[PCI_NUM_REGIONS]; 250 AddressSpace bus_master_as; 251 MemoryRegion bus_master_enable_region; 252 253 /* do not access the following fields */ 254 PCIConfigReadFunc *config_read; 255 PCIConfigWriteFunc *config_write; 256 257 /* Legacy PCI VGA regions */ 258 MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS]; 259 bool has_vga; 260 261 /* Current IRQ levels. Used internally by the generic PCI code. */ 262 uint8_t irq_state; 263 264 /* Capability bits */ 265 uint32_t cap_present; 266 267 /* Offset of MSI-X capability in config space */ 268 uint8_t msix_cap; 269 270 /* MSI-X entries */ 271 int msix_entries_nr; 272 273 /* Space to store MSIX table & pending bit array */ 274 uint8_t *msix_table; 275 uint8_t *msix_pba; 276 /* MemoryRegion container for msix exclusive BAR setup */ 277 MemoryRegion msix_exclusive_bar; 278 /* Memory Regions for MSIX table and pending bit entries. */ 279 MemoryRegion msix_table_mmio; 280 MemoryRegion msix_pba_mmio; 281 /* Reference-count for entries actually in use by driver. */ 282 unsigned *msix_entry_used; 283 /* MSIX function mask set or MSIX disabled */ 284 bool msix_function_masked; 285 /* Version id needed for VMState */ 286 int32_t version_id; 287 288 /* Offset of MSI capability in config space */ 289 uint8_t msi_cap; 290 291 /* PCI Express */ 292 PCIExpressDevice exp; 293 294 /* SHPC */ 295 SHPCDevice *shpc; 296 297 /* Location of option rom */ 298 char *romfile; 299 bool has_rom; 300 MemoryRegion rom; 301 uint32_t rom_bar; 302 303 /* INTx routing notifier */ 304 PCIINTxRoutingNotifier intx_routing_notifier; 305 306 /* MSI-X notifiers */ 307 MSIVectorUseNotifier msix_vector_use_notifier; 308 MSIVectorReleaseNotifier msix_vector_release_notifier; 309 MSIVectorPollNotifier msix_vector_poll_notifier; 310 }; 311 312 void pci_register_bar(PCIDevice *pci_dev, int region_num, 313 uint8_t attr, MemoryRegion *memory); 314 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, 315 MemoryRegion *io_lo, MemoryRegion *io_hi); 316 void pci_unregister_vga(PCIDevice *pci_dev); 317 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num); 318 319 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, 320 uint8_t offset, uint8_t size); 321 int pci_add_capability2(PCIDevice *pdev, uint8_t cap_id, 322 uint8_t offset, uint8_t size, 323 Error **errp); 324 325 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size); 326 327 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id); 328 329 330 uint32_t pci_default_read_config(PCIDevice *d, 331 uint32_t address, int len); 332 void pci_default_write_config(PCIDevice *d, 333 uint32_t address, uint32_t val, int len); 334 void pci_device_save(PCIDevice *s, QEMUFile *f); 335 int pci_device_load(PCIDevice *s, QEMUFile *f); 336 MemoryRegion *pci_address_space(PCIDevice *dev); 337 MemoryRegion *pci_address_space_io(PCIDevice *dev); 338 339 /* 340 * Should not normally be used by devices. For use by sPAPR target 341 * where QEMU emulates firmware. 342 */ 343 int pci_bar(PCIDevice *d, int reg); 344 345 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level); 346 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); 347 typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin); 348 349 #define TYPE_PCI_BUS "PCI" 350 #define PCI_BUS(obj) OBJECT_CHECK(PCIBus, (obj), TYPE_PCI_BUS) 351 #define PCI_BUS_CLASS(klass) OBJECT_CLASS_CHECK(PCIBusClass, (klass), TYPE_PCI_BUS) 352 #define PCI_BUS_GET_CLASS(obj) OBJECT_GET_CLASS(PCIBusClass, (obj), TYPE_PCI_BUS) 353 #define TYPE_PCIE_BUS "PCIE" 354 355 bool pci_bus_is_express(PCIBus *bus); 356 bool pci_bus_is_root(PCIBus *bus); 357 void pci_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent, 358 const char *name, 359 MemoryRegion *address_space_mem, 360 MemoryRegion *address_space_io, 361 uint8_t devfn_min, const char *typename); 362 PCIBus *pci_bus_new(DeviceState *parent, const char *name, 363 MemoryRegion *address_space_mem, 364 MemoryRegion *address_space_io, 365 uint8_t devfn_min, const char *typename); 366 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 367 void *irq_opaque, int nirq); 368 int pci_bus_get_irq_level(PCIBus *bus, int irq_num); 369 /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */ 370 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin); 371 PCIBus *pci_register_bus(DeviceState *parent, const char *name, 372 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 373 void *irq_opaque, 374 MemoryRegion *address_space_mem, 375 MemoryRegion *address_space_io, 376 uint8_t devfn_min, int nirq, const char *typename); 377 void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn); 378 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin); 379 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new); 380 void pci_bus_fire_intx_routing_notifier(PCIBus *bus); 381 void pci_device_set_intx_routing_notifier(PCIDevice *dev, 382 PCIINTxRoutingNotifier notifier); 383 void pci_device_reset(PCIDevice *dev); 384 385 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus, 386 const char *default_model, 387 const char *default_devaddr); 388 389 PCIDevice *pci_vga_init(PCIBus *bus); 390 391 int pci_bus_num(PCIBus *s); 392 int pci_bus_numa_node(PCIBus *bus); 393 void pci_for_each_device(PCIBus *bus, int bus_num, 394 void (*fn)(PCIBus *bus, PCIDevice *d, void *opaque), 395 void *opaque); 396 void pci_for_each_bus_depth_first(PCIBus *bus, 397 void *(*begin)(PCIBus *bus, void *parent_state), 398 void (*end)(PCIBus *bus, void *state), 399 void *parent_state); 400 401 /* Use this wrapper when specific scan order is not required. */ 402 static inline 403 void pci_for_each_bus(PCIBus *bus, 404 void (*fn)(PCIBus *bus, void *opaque), 405 void *opaque) 406 { 407 pci_for_each_bus_depth_first(bus, NULL, fn, opaque); 408 } 409 410 PCIBus *pci_find_primary_bus(void); 411 PCIBus *pci_device_root_bus(const PCIDevice *d); 412 const char *pci_root_bus_path(PCIDevice *dev); 413 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn); 414 int pci_qdev_find_device(const char *id, PCIDevice **pdev); 415 void pci_bus_get_w64_range(PCIBus *bus, Range *range); 416 417 void pci_device_deassert_intx(PCIDevice *dev); 418 419 typedef AddressSpace *(*PCIIOMMUFunc)(PCIBus *, void *, int); 420 421 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev); 422 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque); 423 424 static inline void 425 pci_set_byte(uint8_t *config, uint8_t val) 426 { 427 *config = val; 428 } 429 430 static inline uint8_t 431 pci_get_byte(const uint8_t *config) 432 { 433 return *config; 434 } 435 436 static inline void 437 pci_set_word(uint8_t *config, uint16_t val) 438 { 439 stw_le_p(config, val); 440 } 441 442 static inline uint16_t 443 pci_get_word(const uint8_t *config) 444 { 445 return lduw_le_p(config); 446 } 447 448 static inline void 449 pci_set_long(uint8_t *config, uint32_t val) 450 { 451 stl_le_p(config, val); 452 } 453 454 static inline uint32_t 455 pci_get_long(const uint8_t *config) 456 { 457 return ldl_le_p(config); 458 } 459 460 static inline void 461 pci_set_quad(uint8_t *config, uint64_t val) 462 { 463 cpu_to_le64w((uint64_t *)config, val); 464 } 465 466 static inline uint64_t 467 pci_get_quad(const uint8_t *config) 468 { 469 return le64_to_cpup((const uint64_t *)config); 470 } 471 472 static inline void 473 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val) 474 { 475 pci_set_word(&pci_config[PCI_VENDOR_ID], val); 476 } 477 478 static inline void 479 pci_config_set_device_id(uint8_t *pci_config, uint16_t val) 480 { 481 pci_set_word(&pci_config[PCI_DEVICE_ID], val); 482 } 483 484 static inline void 485 pci_config_set_revision(uint8_t *pci_config, uint8_t val) 486 { 487 pci_set_byte(&pci_config[PCI_REVISION_ID], val); 488 } 489 490 static inline void 491 pci_config_set_class(uint8_t *pci_config, uint16_t val) 492 { 493 pci_set_word(&pci_config[PCI_CLASS_DEVICE], val); 494 } 495 496 static inline void 497 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val) 498 { 499 pci_set_byte(&pci_config[PCI_CLASS_PROG], val); 500 } 501 502 static inline void 503 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val) 504 { 505 pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val); 506 } 507 508 /* 509 * helper functions to do bit mask operation on configuration space. 510 * Just to set bit, use test-and-set and discard returned value. 511 * Just to clear bit, use test-and-clear and discard returned value. 512 * NOTE: They aren't atomic. 513 */ 514 static inline uint8_t 515 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask) 516 { 517 uint8_t val = pci_get_byte(config); 518 pci_set_byte(config, val & ~mask); 519 return val & mask; 520 } 521 522 static inline uint8_t 523 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask) 524 { 525 uint8_t val = pci_get_byte(config); 526 pci_set_byte(config, val | mask); 527 return val & mask; 528 } 529 530 static inline uint16_t 531 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask) 532 { 533 uint16_t val = pci_get_word(config); 534 pci_set_word(config, val & ~mask); 535 return val & mask; 536 } 537 538 static inline uint16_t 539 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask) 540 { 541 uint16_t val = pci_get_word(config); 542 pci_set_word(config, val | mask); 543 return val & mask; 544 } 545 546 static inline uint32_t 547 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask) 548 { 549 uint32_t val = pci_get_long(config); 550 pci_set_long(config, val & ~mask); 551 return val & mask; 552 } 553 554 static inline uint32_t 555 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask) 556 { 557 uint32_t val = pci_get_long(config); 558 pci_set_long(config, val | mask); 559 return val & mask; 560 } 561 562 static inline uint64_t 563 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask) 564 { 565 uint64_t val = pci_get_quad(config); 566 pci_set_quad(config, val & ~mask); 567 return val & mask; 568 } 569 570 static inline uint64_t 571 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask) 572 { 573 uint64_t val = pci_get_quad(config); 574 pci_set_quad(config, val | mask); 575 return val & mask; 576 } 577 578 /* Access a register specified by a mask */ 579 static inline void 580 pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg) 581 { 582 uint8_t val = pci_get_byte(config); 583 uint8_t rval = reg << ctz32(mask); 584 pci_set_byte(config, (~mask & val) | (mask & rval)); 585 } 586 587 static inline uint8_t 588 pci_get_byte_by_mask(uint8_t *config, uint8_t mask) 589 { 590 uint8_t val = pci_get_byte(config); 591 return (val & mask) >> ctz32(mask); 592 } 593 594 static inline void 595 pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg) 596 { 597 uint16_t val = pci_get_word(config); 598 uint16_t rval = reg << ctz32(mask); 599 pci_set_word(config, (~mask & val) | (mask & rval)); 600 } 601 602 static inline uint16_t 603 pci_get_word_by_mask(uint8_t *config, uint16_t mask) 604 { 605 uint16_t val = pci_get_word(config); 606 return (val & mask) >> ctz32(mask); 607 } 608 609 static inline void 610 pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg) 611 { 612 uint32_t val = pci_get_long(config); 613 uint32_t rval = reg << ctz32(mask); 614 pci_set_long(config, (~mask & val) | (mask & rval)); 615 } 616 617 static inline uint32_t 618 pci_get_long_by_mask(uint8_t *config, uint32_t mask) 619 { 620 uint32_t val = pci_get_long(config); 621 return (val & mask) >> ctz32(mask); 622 } 623 624 static inline void 625 pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg) 626 { 627 uint64_t val = pci_get_quad(config); 628 uint64_t rval = reg << ctz32(mask); 629 pci_set_quad(config, (~mask & val) | (mask & rval)); 630 } 631 632 static inline uint64_t 633 pci_get_quad_by_mask(uint8_t *config, uint64_t mask) 634 { 635 uint64_t val = pci_get_quad(config); 636 return (val & mask) >> ctz32(mask); 637 } 638 639 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction, 640 const char *name); 641 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, 642 bool multifunction, 643 const char *name); 644 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name); 645 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name); 646 647 qemu_irq pci_allocate_irq(PCIDevice *pci_dev); 648 void pci_set_irq(PCIDevice *pci_dev, int level); 649 650 static inline void pci_irq_assert(PCIDevice *pci_dev) 651 { 652 pci_set_irq(pci_dev, 1); 653 } 654 655 static inline void pci_irq_deassert(PCIDevice *pci_dev) 656 { 657 pci_set_irq(pci_dev, 0); 658 } 659 660 /* 661 * FIXME: PCI does not work this way. 662 * All the callers to this method should be fixed. 663 */ 664 static inline void pci_irq_pulse(PCIDevice *pci_dev) 665 { 666 pci_irq_assert(pci_dev); 667 pci_irq_deassert(pci_dev); 668 } 669 670 static inline int pci_is_express(const PCIDevice *d) 671 { 672 return d->cap_present & QEMU_PCI_CAP_EXPRESS; 673 } 674 675 static inline uint32_t pci_config_size(const PCIDevice *d) 676 { 677 return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE; 678 } 679 680 /* DMA access functions */ 681 static inline AddressSpace *pci_get_address_space(PCIDevice *dev) 682 { 683 return &dev->bus_master_as; 684 } 685 686 static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr, 687 void *buf, dma_addr_t len, DMADirection dir) 688 { 689 dma_memory_rw(pci_get_address_space(dev), addr, buf, len, dir); 690 return 0; 691 } 692 693 static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr, 694 void *buf, dma_addr_t len) 695 { 696 return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE); 697 } 698 699 static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr, 700 const void *buf, dma_addr_t len) 701 { 702 return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE); 703 } 704 705 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \ 706 static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev, \ 707 dma_addr_t addr) \ 708 { \ 709 return ld##_l##_dma(pci_get_address_space(dev), addr); \ 710 } \ 711 static inline void st##_s##_pci_dma(PCIDevice *dev, \ 712 dma_addr_t addr, uint##_bits##_t val) \ 713 { \ 714 st##_s##_dma(pci_get_address_space(dev), addr, val); \ 715 } 716 717 PCI_DMA_DEFINE_LDST(ub, b, 8); 718 PCI_DMA_DEFINE_LDST(uw_le, w_le, 16) 719 PCI_DMA_DEFINE_LDST(l_le, l_le, 32); 720 PCI_DMA_DEFINE_LDST(q_le, q_le, 64); 721 PCI_DMA_DEFINE_LDST(uw_be, w_be, 16) 722 PCI_DMA_DEFINE_LDST(l_be, l_be, 32); 723 PCI_DMA_DEFINE_LDST(q_be, q_be, 64); 724 725 #undef PCI_DMA_DEFINE_LDST 726 727 static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr, 728 dma_addr_t *plen, DMADirection dir) 729 { 730 void *buf; 731 732 buf = dma_memory_map(pci_get_address_space(dev), addr, plen, dir); 733 return buf; 734 } 735 736 static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len, 737 DMADirection dir, dma_addr_t access_len) 738 { 739 dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len); 740 } 741 742 static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev, 743 int alloc_hint) 744 { 745 qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev)); 746 } 747 748 extern const VMStateDescription vmstate_pci_device; 749 750 #define VMSTATE_PCI_DEVICE(_field, _state) { \ 751 .name = (stringify(_field)), \ 752 .size = sizeof(PCIDevice), \ 753 .vmsd = &vmstate_pci_device, \ 754 .flags = VMS_STRUCT, \ 755 .offset = vmstate_offset_value(_state, _field, PCIDevice), \ 756 } 757 758 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \ 759 .name = (stringify(_field)), \ 760 .size = sizeof(PCIDevice), \ 761 .vmsd = &vmstate_pci_device, \ 762 .flags = VMS_STRUCT|VMS_POINTER, \ 763 .offset = vmstate_offset_pointer(_state, _field, PCIDevice), \ 764 } 765 766 #endif 767