1 #ifndef QEMU_PCI_H 2 #define QEMU_PCI_H 3 4 #include "hw/qdev.h" 5 #include "exec/memory.h" 6 #include "sysemu/dma.h" 7 8 /* PCI includes legacy ISA access. */ 9 #include "hw/isa/isa.h" 10 11 #include "hw/pci/pcie.h" 12 13 /* PCI bus */ 14 15 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 16 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 17 #define PCI_FUNC(devfn) ((devfn) & 0x07) 18 #define PCI_BUILD_BDF(bus, devfn) ((bus << 8) | (devfn)) 19 #define PCI_SLOT_MAX 32 20 #define PCI_FUNC_MAX 8 21 22 /* Class, Vendor and Device IDs from Linux's pci_ids.h */ 23 #include "hw/pci/pci_ids.h" 24 25 /* QEMU-specific Vendor and Device ID definitions */ 26 27 /* IBM (0x1014) */ 28 #define PCI_DEVICE_ID_IBM_440GX 0x027f 29 #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff 30 31 /* Hitachi (0x1054) */ 32 #define PCI_VENDOR_ID_HITACHI 0x1054 33 #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e 34 35 /* Apple (0x106b) */ 36 #define PCI_DEVICE_ID_APPLE_343S1201 0x0010 37 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e 38 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f 39 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022 40 #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f 41 42 /* Realtek (0x10ec) */ 43 #define PCI_DEVICE_ID_REALTEK_8029 0x8029 44 45 /* Xilinx (0x10ee) */ 46 #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300 47 48 /* Marvell (0x11ab) */ 49 #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620 50 51 /* QEMU/Bochs VGA (0x1234) */ 52 #define PCI_VENDOR_ID_QEMU 0x1234 53 #define PCI_DEVICE_ID_QEMU_VGA 0x1111 54 55 /* VMWare (0x15ad) */ 56 #define PCI_VENDOR_ID_VMWARE 0x15ad 57 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 58 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710 59 #define PCI_DEVICE_ID_VMWARE_NET 0x0720 60 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730 61 #define PCI_DEVICE_ID_VMWARE_PVSCSI 0x07C0 62 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729 63 #define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0 64 65 /* Intel (0x8086) */ 66 #define PCI_DEVICE_ID_INTEL_82551IT 0x1209 67 #define PCI_DEVICE_ID_INTEL_82557 0x1229 68 #define PCI_DEVICE_ID_INTEL_82801IR 0x2922 69 70 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */ 71 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 72 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 73 #define PCI_SUBDEVICE_ID_QEMU 0x1100 74 75 #define PCI_DEVICE_ID_VIRTIO_NET 0x1000 76 #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001 77 #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002 78 #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003 79 #define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004 80 #define PCI_DEVICE_ID_VIRTIO_RNG 0x1005 81 #define PCI_DEVICE_ID_VIRTIO_9P 0x1009 82 #define PCI_DEVICE_ID_VIRTIO_VSOCK 0x1012 83 84 #define PCI_VENDOR_ID_REDHAT 0x1b36 85 #define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001 86 #define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002 87 #define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003 88 #define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004 89 #define PCI_DEVICE_ID_REDHAT_TEST 0x0005 90 #define PCI_DEVICE_ID_REDHAT_ROCKER 0x0006 91 #define PCI_DEVICE_ID_REDHAT_SDHCI 0x0007 92 #define PCI_DEVICE_ID_REDHAT_PCIE_HOST 0x0008 93 #define PCI_DEVICE_ID_REDHAT_PXB 0x0009 94 #define PCI_DEVICE_ID_REDHAT_BRIDGE_SEAT 0x000a 95 #define PCI_DEVICE_ID_REDHAT_PXB_PCIE 0x000b 96 #define PCI_DEVICE_ID_REDHAT_QXL 0x0100 97 98 #define FMT_PCIBUS PRIx64 99 100 typedef uint64_t pcibus_t; 101 102 struct PCIHostDeviceAddress { 103 unsigned int domain; 104 unsigned int bus; 105 unsigned int slot; 106 unsigned int function; 107 }; 108 109 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, 110 uint32_t address, uint32_t data, int len); 111 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev, 112 uint32_t address, int len); 113 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, 114 pcibus_t addr, pcibus_t size, int type); 115 typedef void PCIUnregisterFunc(PCIDevice *pci_dev); 116 117 typedef struct PCIIORegion { 118 pcibus_t addr; /* current PCI mapping address. -1 means not mapped */ 119 #define PCI_BAR_UNMAPPED (~(pcibus_t)0) 120 pcibus_t size; 121 uint8_t type; 122 MemoryRegion *memory; 123 MemoryRegion *address_space; 124 } PCIIORegion; 125 126 #define PCI_ROM_SLOT 6 127 #define PCI_NUM_REGIONS 7 128 129 enum { 130 QEMU_PCI_VGA_MEM, 131 QEMU_PCI_VGA_IO_LO, 132 QEMU_PCI_VGA_IO_HI, 133 QEMU_PCI_VGA_NUM_REGIONS, 134 }; 135 136 #define QEMU_PCI_VGA_MEM_BASE 0xa0000 137 #define QEMU_PCI_VGA_MEM_SIZE 0x20000 138 #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0 139 #define QEMU_PCI_VGA_IO_LO_SIZE 0xc 140 #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0 141 #define QEMU_PCI_VGA_IO_HI_SIZE 0x20 142 143 #include "hw/pci/pci_regs.h" 144 145 /* PCI HEADER_TYPE */ 146 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80 147 148 /* Size of the standard PCI config header */ 149 #define PCI_CONFIG_HEADER_SIZE 0x40 150 /* Size of the standard PCI config space */ 151 #define PCI_CONFIG_SPACE_SIZE 0x100 152 /* Size of the standard PCIe config space: 4KB */ 153 #define PCIE_CONFIG_SPACE_SIZE 0x1000 154 155 #define PCI_NUM_PINS 4 /* A-D */ 156 157 /* Bits in cap_present field. */ 158 enum { 159 QEMU_PCI_CAP_MSI = 0x1, 160 QEMU_PCI_CAP_MSIX = 0x2, 161 QEMU_PCI_CAP_EXPRESS = 0x4, 162 163 /* multifunction capable device */ 164 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3 165 QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR), 166 167 /* command register SERR bit enabled */ 168 #define QEMU_PCI_CAP_SERR_BITNR 4 169 QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR), 170 /* Standard hot plug controller. */ 171 #define QEMU_PCI_SHPC_BITNR 5 172 QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR), 173 #define QEMU_PCI_SLOTID_BITNR 6 174 QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR), 175 /* PCI Express capability - Power Controller Present */ 176 #define QEMU_PCIE_SLTCAP_PCP_BITNR 7 177 QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR), 178 /* Link active status in endpoint capability is always set */ 179 #define QEMU_PCIE_LNKSTA_DLLLA_BITNR 8 180 QEMU_PCIE_LNKSTA_DLLLA = (1 << QEMU_PCIE_LNKSTA_DLLLA_BITNR), 181 }; 182 183 #define TYPE_PCI_DEVICE "pci-device" 184 #define PCI_DEVICE(obj) \ 185 OBJECT_CHECK(PCIDevice, (obj), TYPE_PCI_DEVICE) 186 #define PCI_DEVICE_CLASS(klass) \ 187 OBJECT_CLASS_CHECK(PCIDeviceClass, (klass), TYPE_PCI_DEVICE) 188 #define PCI_DEVICE_GET_CLASS(obj) \ 189 OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE) 190 191 typedef struct PCIINTxRoute { 192 enum { 193 PCI_INTX_ENABLED, 194 PCI_INTX_INVERTED, 195 PCI_INTX_DISABLED, 196 } mode; 197 int irq; 198 } PCIINTxRoute; 199 200 typedef struct PCIDeviceClass { 201 DeviceClass parent_class; 202 203 void (*realize)(PCIDevice *dev, Error **errp); 204 int (*init)(PCIDevice *dev);/* TODO convert to realize() and remove */ 205 PCIUnregisterFunc *exit; 206 PCIConfigReadFunc *config_read; 207 PCIConfigWriteFunc *config_write; 208 209 uint16_t vendor_id; 210 uint16_t device_id; 211 uint8_t revision; 212 uint16_t class_id; 213 uint16_t subsystem_vendor_id; /* only for header type = 0 */ 214 uint16_t subsystem_id; /* only for header type = 0 */ 215 216 /* 217 * pci-to-pci bridge or normal device. 218 * This doesn't mean pci host switch. 219 * When card bus bridge is supported, this would be enhanced. 220 */ 221 int is_bridge; 222 223 /* pcie stuff */ 224 int is_express; /* is this device pci express? */ 225 226 /* rom bar */ 227 const char *romfile; 228 } PCIDeviceClass; 229 230 typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev); 231 typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector, 232 MSIMessage msg); 233 typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector); 234 typedef void (*MSIVectorPollNotifier)(PCIDevice *dev, 235 unsigned int vector_start, 236 unsigned int vector_end); 237 238 enum PCIReqIDType { 239 PCI_REQ_ID_INVALID = 0, 240 PCI_REQ_ID_BDF, 241 PCI_REQ_ID_SECONDARY_BUS, 242 PCI_REQ_ID_MAX, 243 }; 244 typedef enum PCIReqIDType PCIReqIDType; 245 246 struct PCIReqIDCache { 247 PCIDevice *dev; 248 PCIReqIDType type; 249 }; 250 typedef struct PCIReqIDCache PCIReqIDCache; 251 252 struct PCIDevice { 253 DeviceState qdev; 254 255 /* PCI config space */ 256 uint8_t *config; 257 258 /* Used to enable config checks on load. Note that writable bits are 259 * never checked even if set in cmask. */ 260 uint8_t *cmask; 261 262 /* Used to implement R/W bytes */ 263 uint8_t *wmask; 264 265 /* Used to implement RW1C(Write 1 to Clear) bytes */ 266 uint8_t *w1cmask; 267 268 /* Used to allocate config space for capabilities. */ 269 uint8_t *used; 270 271 /* the following fields are read only */ 272 PCIBus *bus; 273 int32_t devfn; 274 /* Cached device to fetch requester ID from, to avoid the PCI 275 * tree walking every time we invoke PCI request (e.g., 276 * MSI). For conventional PCI root complex, this field is 277 * meaningless. */ 278 PCIReqIDCache requester_id_cache; 279 char name[64]; 280 PCIIORegion io_regions[PCI_NUM_REGIONS]; 281 AddressSpace bus_master_as; 282 MemoryRegion bus_master_enable_region; 283 284 /* do not access the following fields */ 285 PCIConfigReadFunc *config_read; 286 PCIConfigWriteFunc *config_write; 287 288 /* Legacy PCI VGA regions */ 289 MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS]; 290 bool has_vga; 291 292 /* Current IRQ levels. Used internally by the generic PCI code. */ 293 uint8_t irq_state; 294 295 /* Capability bits */ 296 uint32_t cap_present; 297 298 /* Offset of MSI-X capability in config space */ 299 uint8_t msix_cap; 300 301 /* MSI-X entries */ 302 int msix_entries_nr; 303 304 /* Space to store MSIX table & pending bit array */ 305 uint8_t *msix_table; 306 uint8_t *msix_pba; 307 /* MemoryRegion container for msix exclusive BAR setup */ 308 MemoryRegion msix_exclusive_bar; 309 /* Memory Regions for MSIX table and pending bit entries. */ 310 MemoryRegion msix_table_mmio; 311 MemoryRegion msix_pba_mmio; 312 /* Reference-count for entries actually in use by driver. */ 313 unsigned *msix_entry_used; 314 /* MSIX function mask set or MSIX disabled */ 315 bool msix_function_masked; 316 /* Version id needed for VMState */ 317 int32_t version_id; 318 319 /* Offset of MSI capability in config space */ 320 uint8_t msi_cap; 321 322 /* PCI Express */ 323 PCIExpressDevice exp; 324 325 /* SHPC */ 326 SHPCDevice *shpc; 327 328 /* Location of option rom */ 329 char *romfile; 330 bool has_rom; 331 MemoryRegion rom; 332 uint32_t rom_bar; 333 334 /* INTx routing notifier */ 335 PCIINTxRoutingNotifier intx_routing_notifier; 336 337 /* MSI-X notifiers */ 338 MSIVectorUseNotifier msix_vector_use_notifier; 339 MSIVectorReleaseNotifier msix_vector_release_notifier; 340 MSIVectorPollNotifier msix_vector_poll_notifier; 341 }; 342 343 void pci_register_bar(PCIDevice *pci_dev, int region_num, 344 uint8_t attr, MemoryRegion *memory); 345 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, 346 MemoryRegion *io_lo, MemoryRegion *io_hi); 347 void pci_unregister_vga(PCIDevice *pci_dev); 348 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num); 349 350 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, 351 uint8_t offset, uint8_t size); 352 int pci_add_capability2(PCIDevice *pdev, uint8_t cap_id, 353 uint8_t offset, uint8_t size, 354 Error **errp); 355 356 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size); 357 358 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id); 359 360 361 uint32_t pci_default_read_config(PCIDevice *d, 362 uint32_t address, int len); 363 void pci_default_write_config(PCIDevice *d, 364 uint32_t address, uint32_t val, int len); 365 void pci_device_save(PCIDevice *s, QEMUFile *f); 366 int pci_device_load(PCIDevice *s, QEMUFile *f); 367 MemoryRegion *pci_address_space(PCIDevice *dev); 368 MemoryRegion *pci_address_space_io(PCIDevice *dev); 369 370 /* 371 * Should not normally be used by devices. For use by sPAPR target 372 * where QEMU emulates firmware. 373 */ 374 int pci_bar(PCIDevice *d, int reg); 375 376 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level); 377 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); 378 typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin); 379 380 #define TYPE_PCI_BUS "PCI" 381 #define PCI_BUS(obj) OBJECT_CHECK(PCIBus, (obj), TYPE_PCI_BUS) 382 #define PCI_BUS_CLASS(klass) OBJECT_CLASS_CHECK(PCIBusClass, (klass), TYPE_PCI_BUS) 383 #define PCI_BUS_GET_CLASS(obj) OBJECT_GET_CLASS(PCIBusClass, (obj), TYPE_PCI_BUS) 384 #define TYPE_PCIE_BUS "PCIE" 385 386 bool pci_bus_is_express(PCIBus *bus); 387 bool pci_bus_is_root(PCIBus *bus); 388 void pci_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent, 389 const char *name, 390 MemoryRegion *address_space_mem, 391 MemoryRegion *address_space_io, 392 uint8_t devfn_min, const char *typename); 393 PCIBus *pci_bus_new(DeviceState *parent, const char *name, 394 MemoryRegion *address_space_mem, 395 MemoryRegion *address_space_io, 396 uint8_t devfn_min, const char *typename); 397 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 398 void *irq_opaque, int nirq); 399 int pci_bus_get_irq_level(PCIBus *bus, int irq_num); 400 /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */ 401 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin); 402 PCIBus *pci_register_bus(DeviceState *parent, const char *name, 403 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 404 void *irq_opaque, 405 MemoryRegion *address_space_mem, 406 MemoryRegion *address_space_io, 407 uint8_t devfn_min, int nirq, const char *typename); 408 void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn); 409 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin); 410 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new); 411 void pci_bus_fire_intx_routing_notifier(PCIBus *bus); 412 void pci_device_set_intx_routing_notifier(PCIDevice *dev, 413 PCIINTxRoutingNotifier notifier); 414 void pci_device_reset(PCIDevice *dev); 415 416 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus, 417 const char *default_model, 418 const char *default_devaddr); 419 420 PCIDevice *pci_vga_init(PCIBus *bus); 421 422 int pci_bus_num(PCIBus *s); 423 int pci_bus_numa_node(PCIBus *bus); 424 void pci_for_each_device(PCIBus *bus, int bus_num, 425 void (*fn)(PCIBus *bus, PCIDevice *d, void *opaque), 426 void *opaque); 427 void pci_for_each_bus_depth_first(PCIBus *bus, 428 void *(*begin)(PCIBus *bus, void *parent_state), 429 void (*end)(PCIBus *bus, void *state), 430 void *parent_state); 431 PCIDevice *pci_get_function_0(PCIDevice *pci_dev); 432 433 /* Use this wrapper when specific scan order is not required. */ 434 static inline 435 void pci_for_each_bus(PCIBus *bus, 436 void (*fn)(PCIBus *bus, void *opaque), 437 void *opaque) 438 { 439 pci_for_each_bus_depth_first(bus, NULL, fn, opaque); 440 } 441 442 PCIBus *pci_find_primary_bus(void); 443 PCIBus *pci_device_root_bus(const PCIDevice *d); 444 const char *pci_root_bus_path(PCIDevice *dev); 445 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn); 446 int pci_qdev_find_device(const char *id, PCIDevice **pdev); 447 void pci_bus_get_w64_range(PCIBus *bus, Range *range); 448 449 void pci_device_deassert_intx(PCIDevice *dev); 450 451 typedef AddressSpace *(*PCIIOMMUFunc)(PCIBus *, void *, int); 452 453 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev); 454 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque); 455 456 static inline void 457 pci_set_byte(uint8_t *config, uint8_t val) 458 { 459 *config = val; 460 } 461 462 static inline uint8_t 463 pci_get_byte(const uint8_t *config) 464 { 465 return *config; 466 } 467 468 static inline void 469 pci_set_word(uint8_t *config, uint16_t val) 470 { 471 stw_le_p(config, val); 472 } 473 474 static inline uint16_t 475 pci_get_word(const uint8_t *config) 476 { 477 return lduw_le_p(config); 478 } 479 480 static inline void 481 pci_set_long(uint8_t *config, uint32_t val) 482 { 483 stl_le_p(config, val); 484 } 485 486 static inline uint32_t 487 pci_get_long(const uint8_t *config) 488 { 489 return ldl_le_p(config); 490 } 491 492 /* 493 * PCI capabilities and/or their fields 494 * are generally DWORD aligned only so 495 * mechanism used by pci_set/get_quad() 496 * must be tolerant to unaligned pointers 497 * 498 */ 499 static inline void 500 pci_set_quad(uint8_t *config, uint64_t val) 501 { 502 stq_le_p(config, val); 503 } 504 505 static inline uint64_t 506 pci_get_quad(const uint8_t *config) 507 { 508 return ldq_le_p(config); 509 } 510 511 static inline void 512 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val) 513 { 514 pci_set_word(&pci_config[PCI_VENDOR_ID], val); 515 } 516 517 static inline void 518 pci_config_set_device_id(uint8_t *pci_config, uint16_t val) 519 { 520 pci_set_word(&pci_config[PCI_DEVICE_ID], val); 521 } 522 523 static inline void 524 pci_config_set_revision(uint8_t *pci_config, uint8_t val) 525 { 526 pci_set_byte(&pci_config[PCI_REVISION_ID], val); 527 } 528 529 static inline void 530 pci_config_set_class(uint8_t *pci_config, uint16_t val) 531 { 532 pci_set_word(&pci_config[PCI_CLASS_DEVICE], val); 533 } 534 535 static inline void 536 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val) 537 { 538 pci_set_byte(&pci_config[PCI_CLASS_PROG], val); 539 } 540 541 static inline void 542 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val) 543 { 544 pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val); 545 } 546 547 /* 548 * helper functions to do bit mask operation on configuration space. 549 * Just to set bit, use test-and-set and discard returned value. 550 * Just to clear bit, use test-and-clear and discard returned value. 551 * NOTE: They aren't atomic. 552 */ 553 static inline uint8_t 554 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask) 555 { 556 uint8_t val = pci_get_byte(config); 557 pci_set_byte(config, val & ~mask); 558 return val & mask; 559 } 560 561 static inline uint8_t 562 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask) 563 { 564 uint8_t val = pci_get_byte(config); 565 pci_set_byte(config, val | mask); 566 return val & mask; 567 } 568 569 static inline uint16_t 570 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask) 571 { 572 uint16_t val = pci_get_word(config); 573 pci_set_word(config, val & ~mask); 574 return val & mask; 575 } 576 577 static inline uint16_t 578 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask) 579 { 580 uint16_t val = pci_get_word(config); 581 pci_set_word(config, val | mask); 582 return val & mask; 583 } 584 585 static inline uint32_t 586 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask) 587 { 588 uint32_t val = pci_get_long(config); 589 pci_set_long(config, val & ~mask); 590 return val & mask; 591 } 592 593 static inline uint32_t 594 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask) 595 { 596 uint32_t val = pci_get_long(config); 597 pci_set_long(config, val | mask); 598 return val & mask; 599 } 600 601 static inline uint64_t 602 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask) 603 { 604 uint64_t val = pci_get_quad(config); 605 pci_set_quad(config, val & ~mask); 606 return val & mask; 607 } 608 609 static inline uint64_t 610 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask) 611 { 612 uint64_t val = pci_get_quad(config); 613 pci_set_quad(config, val | mask); 614 return val & mask; 615 } 616 617 /* Access a register specified by a mask */ 618 static inline void 619 pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg) 620 { 621 uint8_t val = pci_get_byte(config); 622 uint8_t rval = reg << ctz32(mask); 623 pci_set_byte(config, (~mask & val) | (mask & rval)); 624 } 625 626 static inline uint8_t 627 pci_get_byte_by_mask(uint8_t *config, uint8_t mask) 628 { 629 uint8_t val = pci_get_byte(config); 630 return (val & mask) >> ctz32(mask); 631 } 632 633 static inline void 634 pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg) 635 { 636 uint16_t val = pci_get_word(config); 637 uint16_t rval = reg << ctz32(mask); 638 pci_set_word(config, (~mask & val) | (mask & rval)); 639 } 640 641 static inline uint16_t 642 pci_get_word_by_mask(uint8_t *config, uint16_t mask) 643 { 644 uint16_t val = pci_get_word(config); 645 return (val & mask) >> ctz32(mask); 646 } 647 648 static inline void 649 pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg) 650 { 651 uint32_t val = pci_get_long(config); 652 uint32_t rval = reg << ctz32(mask); 653 pci_set_long(config, (~mask & val) | (mask & rval)); 654 } 655 656 static inline uint32_t 657 pci_get_long_by_mask(uint8_t *config, uint32_t mask) 658 { 659 uint32_t val = pci_get_long(config); 660 return (val & mask) >> ctz32(mask); 661 } 662 663 static inline void 664 pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg) 665 { 666 uint64_t val = pci_get_quad(config); 667 uint64_t rval = reg << ctz32(mask); 668 pci_set_quad(config, (~mask & val) | (mask & rval)); 669 } 670 671 static inline uint64_t 672 pci_get_quad_by_mask(uint8_t *config, uint64_t mask) 673 { 674 uint64_t val = pci_get_quad(config); 675 return (val & mask) >> ctz32(mask); 676 } 677 678 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction, 679 const char *name); 680 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, 681 bool multifunction, 682 const char *name); 683 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name); 684 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name); 685 686 qemu_irq pci_allocate_irq(PCIDevice *pci_dev); 687 void pci_set_irq(PCIDevice *pci_dev, int level); 688 689 static inline void pci_irq_assert(PCIDevice *pci_dev) 690 { 691 pci_set_irq(pci_dev, 1); 692 } 693 694 static inline void pci_irq_deassert(PCIDevice *pci_dev) 695 { 696 pci_set_irq(pci_dev, 0); 697 } 698 699 /* 700 * FIXME: PCI does not work this way. 701 * All the callers to this method should be fixed. 702 */ 703 static inline void pci_irq_pulse(PCIDevice *pci_dev) 704 { 705 pci_irq_assert(pci_dev); 706 pci_irq_deassert(pci_dev); 707 } 708 709 static inline int pci_is_express(const PCIDevice *d) 710 { 711 return d->cap_present & QEMU_PCI_CAP_EXPRESS; 712 } 713 714 static inline uint32_t pci_config_size(const PCIDevice *d) 715 { 716 return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE; 717 } 718 719 static inline uint16_t pci_get_bdf(PCIDevice *dev) 720 { 721 return PCI_BUILD_BDF(pci_bus_num(dev->bus), dev->devfn); 722 } 723 724 uint16_t pci_requester_id(PCIDevice *dev); 725 726 /* DMA access functions */ 727 static inline AddressSpace *pci_get_address_space(PCIDevice *dev) 728 { 729 return &dev->bus_master_as; 730 } 731 732 static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr, 733 void *buf, dma_addr_t len, DMADirection dir) 734 { 735 dma_memory_rw(pci_get_address_space(dev), addr, buf, len, dir); 736 return 0; 737 } 738 739 static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr, 740 void *buf, dma_addr_t len) 741 { 742 return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE); 743 } 744 745 static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr, 746 const void *buf, dma_addr_t len) 747 { 748 return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE); 749 } 750 751 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \ 752 static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev, \ 753 dma_addr_t addr) \ 754 { \ 755 return ld##_l##_dma(pci_get_address_space(dev), addr); \ 756 } \ 757 static inline void st##_s##_pci_dma(PCIDevice *dev, \ 758 dma_addr_t addr, uint##_bits##_t val) \ 759 { \ 760 st##_s##_dma(pci_get_address_space(dev), addr, val); \ 761 } 762 763 PCI_DMA_DEFINE_LDST(ub, b, 8); 764 PCI_DMA_DEFINE_LDST(uw_le, w_le, 16) 765 PCI_DMA_DEFINE_LDST(l_le, l_le, 32); 766 PCI_DMA_DEFINE_LDST(q_le, q_le, 64); 767 PCI_DMA_DEFINE_LDST(uw_be, w_be, 16) 768 PCI_DMA_DEFINE_LDST(l_be, l_be, 32); 769 PCI_DMA_DEFINE_LDST(q_be, q_be, 64); 770 771 #undef PCI_DMA_DEFINE_LDST 772 773 static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr, 774 dma_addr_t *plen, DMADirection dir) 775 { 776 void *buf; 777 778 buf = dma_memory_map(pci_get_address_space(dev), addr, plen, dir); 779 return buf; 780 } 781 782 static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len, 783 DMADirection dir, dma_addr_t access_len) 784 { 785 dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len); 786 } 787 788 static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev, 789 int alloc_hint) 790 { 791 qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev)); 792 } 793 794 extern const VMStateDescription vmstate_pci_device; 795 796 #define VMSTATE_PCI_DEVICE(_field, _state) { \ 797 .name = (stringify(_field)), \ 798 .size = sizeof(PCIDevice), \ 799 .vmsd = &vmstate_pci_device, \ 800 .flags = VMS_STRUCT, \ 801 .offset = vmstate_offset_value(_state, _field, PCIDevice), \ 802 } 803 804 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \ 805 .name = (stringify(_field)), \ 806 .size = sizeof(PCIDevice), \ 807 .vmsd = &vmstate_pci_device, \ 808 .flags = VMS_STRUCT|VMS_POINTER, \ 809 .offset = vmstate_offset_pointer(_state, _field, PCIDevice), \ 810 } 811 812 MSIMessage pci_get_msi_message(PCIDevice *dev, int vector); 813 814 #endif 815