xref: /openbmc/qemu/include/hw/pci/pci.h (revision c2387413)
1 #ifndef QEMU_PCI_H
2 #define QEMU_PCI_H
3 
4 #include "exec/memory.h"
5 #include "sysemu/dma.h"
6 
7 /* PCI includes legacy ISA access.  */
8 #include "hw/isa/isa.h"
9 
10 #include "hw/pci/pcie.h"
11 #include "qom/object.h"
12 
13 extern bool pci_available;
14 
15 /* PCI bus */
16 
17 #define PCI_DEVFN(slot, func)   ((((slot) & 0x1f) << 3) | ((func) & 0x07))
18 #define PCI_BUS_NUM(x)          (((x) >> 8) & 0xff)
19 #define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
20 #define PCI_FUNC(devfn)         ((devfn) & 0x07)
21 #define PCI_BUILD_BDF(bus, devfn)     ((bus << 8) | (devfn))
22 #define PCI_BUS_MAX             256
23 #define PCI_DEVFN_MAX           256
24 #define PCI_SLOT_MAX            32
25 #define PCI_FUNC_MAX            8
26 
27 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
28 #include "hw/pci/pci_ids.h"
29 
30 /* QEMU-specific Vendor and Device ID definitions */
31 
32 /* IBM (0x1014) */
33 #define PCI_DEVICE_ID_IBM_440GX          0x027f
34 #define PCI_DEVICE_ID_IBM_OPENPIC2       0xffff
35 
36 /* Hitachi (0x1054) */
37 #define PCI_VENDOR_ID_HITACHI            0x1054
38 #define PCI_DEVICE_ID_HITACHI_SH7751R    0x350e
39 
40 /* Apple (0x106b) */
41 #define PCI_DEVICE_ID_APPLE_343S1201     0x0010
42 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI  0x001e
43 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI    0x001f
44 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL   0x0022
45 #define PCI_DEVICE_ID_APPLE_IPID_USB     0x003f
46 
47 /* Realtek (0x10ec) */
48 #define PCI_DEVICE_ID_REALTEK_8029       0x8029
49 
50 /* Xilinx (0x10ee) */
51 #define PCI_DEVICE_ID_XILINX_XC2VP30     0x0300
52 
53 /* Marvell (0x11ab) */
54 #define PCI_DEVICE_ID_MARVELL_GT6412X    0x4620
55 
56 /* QEMU/Bochs VGA (0x1234) */
57 #define PCI_VENDOR_ID_QEMU               0x1234
58 #define PCI_DEVICE_ID_QEMU_VGA           0x1111
59 #define PCI_DEVICE_ID_QEMU_IPMI          0x1112
60 
61 /* VMWare (0x15ad) */
62 #define PCI_VENDOR_ID_VMWARE             0x15ad
63 #define PCI_DEVICE_ID_VMWARE_SVGA2       0x0405
64 #define PCI_DEVICE_ID_VMWARE_SVGA        0x0710
65 #define PCI_DEVICE_ID_VMWARE_NET         0x0720
66 #define PCI_DEVICE_ID_VMWARE_SCSI        0x0730
67 #define PCI_DEVICE_ID_VMWARE_PVSCSI      0x07C0
68 #define PCI_DEVICE_ID_VMWARE_IDE         0x1729
69 #define PCI_DEVICE_ID_VMWARE_VMXNET3     0x07B0
70 
71 /* Intel (0x8086) */
72 #define PCI_DEVICE_ID_INTEL_82551IT      0x1209
73 #define PCI_DEVICE_ID_INTEL_82557        0x1229
74 #define PCI_DEVICE_ID_INTEL_82801IR      0x2922
75 
76 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
77 #define PCI_VENDOR_ID_REDHAT_QUMRANET    0x1af4
78 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
79 #define PCI_SUBDEVICE_ID_QEMU            0x1100
80 
81 #define PCI_DEVICE_ID_VIRTIO_NET         0x1000
82 #define PCI_DEVICE_ID_VIRTIO_BLOCK       0x1001
83 #define PCI_DEVICE_ID_VIRTIO_BALLOON     0x1002
84 #define PCI_DEVICE_ID_VIRTIO_CONSOLE     0x1003
85 #define PCI_DEVICE_ID_VIRTIO_SCSI        0x1004
86 #define PCI_DEVICE_ID_VIRTIO_RNG         0x1005
87 #define PCI_DEVICE_ID_VIRTIO_9P          0x1009
88 #define PCI_DEVICE_ID_VIRTIO_VSOCK       0x1012
89 #define PCI_DEVICE_ID_VIRTIO_PMEM        0x1013
90 #define PCI_DEVICE_ID_VIRTIO_IOMMU       0x1014
91 #define PCI_DEVICE_ID_VIRTIO_MEM         0x1015
92 
93 #define PCI_VENDOR_ID_REDHAT             0x1b36
94 #define PCI_DEVICE_ID_REDHAT_BRIDGE      0x0001
95 #define PCI_DEVICE_ID_REDHAT_SERIAL      0x0002
96 #define PCI_DEVICE_ID_REDHAT_SERIAL2     0x0003
97 #define PCI_DEVICE_ID_REDHAT_SERIAL4     0x0004
98 #define PCI_DEVICE_ID_REDHAT_TEST        0x0005
99 #define PCI_DEVICE_ID_REDHAT_ROCKER      0x0006
100 #define PCI_DEVICE_ID_REDHAT_SDHCI       0x0007
101 #define PCI_DEVICE_ID_REDHAT_PCIE_HOST   0x0008
102 #define PCI_DEVICE_ID_REDHAT_PXB         0x0009
103 #define PCI_DEVICE_ID_REDHAT_BRIDGE_SEAT 0x000a
104 #define PCI_DEVICE_ID_REDHAT_PXB_PCIE    0x000b
105 #define PCI_DEVICE_ID_REDHAT_PCIE_RP     0x000c
106 #define PCI_DEVICE_ID_REDHAT_XHCI        0x000d
107 #define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000e
108 #define PCI_DEVICE_ID_REDHAT_MDPY        0x000f
109 #define PCI_DEVICE_ID_REDHAT_NVME        0x0010
110 #define PCI_DEVICE_ID_REDHAT_PVPANIC     0x0011
111 #define PCI_DEVICE_ID_REDHAT_QXL         0x0100
112 
113 #define FMT_PCIBUS                      PRIx64
114 
115 typedef uint64_t pcibus_t;
116 
117 struct PCIHostDeviceAddress {
118     unsigned int domain;
119     unsigned int bus;
120     unsigned int slot;
121     unsigned int function;
122 };
123 
124 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
125                                 uint32_t address, uint32_t data, int len);
126 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
127                                    uint32_t address, int len);
128 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
129                                 pcibus_t addr, pcibus_t size, int type);
130 typedef void PCIUnregisterFunc(PCIDevice *pci_dev);
131 
132 typedef struct PCIIORegion {
133     pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
134 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
135     pcibus_t size;
136     uint8_t type;
137     MemoryRegion *memory;
138     MemoryRegion *address_space;
139 } PCIIORegion;
140 
141 #define PCI_ROM_SLOT 6
142 #define PCI_NUM_REGIONS 7
143 
144 enum {
145     QEMU_PCI_VGA_MEM,
146     QEMU_PCI_VGA_IO_LO,
147     QEMU_PCI_VGA_IO_HI,
148     QEMU_PCI_VGA_NUM_REGIONS,
149 };
150 
151 #define QEMU_PCI_VGA_MEM_BASE 0xa0000
152 #define QEMU_PCI_VGA_MEM_SIZE 0x20000
153 #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0
154 #define QEMU_PCI_VGA_IO_LO_SIZE 0xc
155 #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0
156 #define QEMU_PCI_VGA_IO_HI_SIZE 0x20
157 
158 #include "hw/pci/pci_regs.h"
159 
160 /* PCI HEADER_TYPE */
161 #define  PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
162 
163 /* Size of the standard PCI config header */
164 #define PCI_CONFIG_HEADER_SIZE 0x40
165 /* Size of the standard PCI config space */
166 #define PCI_CONFIG_SPACE_SIZE 0x100
167 /* Size of the standard PCIe config space: 4KB */
168 #define PCIE_CONFIG_SPACE_SIZE  0x1000
169 
170 #define PCI_NUM_PINS 4 /* A-D */
171 
172 /* Bits in cap_present field. */
173 enum {
174     QEMU_PCI_CAP_MSI = 0x1,
175     QEMU_PCI_CAP_MSIX = 0x2,
176     QEMU_PCI_CAP_EXPRESS = 0x4,
177 
178     /* multifunction capable device */
179 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR        3
180     QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
181 
182     /* command register SERR bit enabled - unused since QEMU v5.0 */
183 #define QEMU_PCI_CAP_SERR_BITNR 4
184     QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
185     /* Standard hot plug controller. */
186 #define QEMU_PCI_SHPC_BITNR 5
187     QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR),
188 #define QEMU_PCI_SLOTID_BITNR 6
189     QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR),
190     /* PCI Express capability - Power Controller Present */
191 #define QEMU_PCIE_SLTCAP_PCP_BITNR 7
192     QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR),
193     /* Link active status in endpoint capability is always set */
194 #define QEMU_PCIE_LNKSTA_DLLLA_BITNR 8
195     QEMU_PCIE_LNKSTA_DLLLA = (1 << QEMU_PCIE_LNKSTA_DLLLA_BITNR),
196 #define QEMU_PCIE_EXTCAP_INIT_BITNR 9
197     QEMU_PCIE_EXTCAP_INIT = (1 << QEMU_PCIE_EXTCAP_INIT_BITNR),
198 };
199 
200 #define TYPE_PCI_DEVICE "pci-device"
201 typedef struct PCIDeviceClass PCIDeviceClass;
202 DECLARE_OBJ_CHECKERS(PCIDevice, PCIDeviceClass,
203                      PCI_DEVICE, TYPE_PCI_DEVICE)
204 
205 /* Implemented by devices that can be plugged on PCI Express buses */
206 #define INTERFACE_PCIE_DEVICE "pci-express-device"
207 
208 /* Implemented by devices that can be plugged on Conventional PCI buses */
209 #define INTERFACE_CONVENTIONAL_PCI_DEVICE "conventional-pci-device"
210 
211 typedef struct PCIINTxRoute {
212     enum {
213         PCI_INTX_ENABLED,
214         PCI_INTX_INVERTED,
215         PCI_INTX_DISABLED,
216     } mode;
217     int irq;
218 } PCIINTxRoute;
219 
220 struct PCIDeviceClass {
221     DeviceClass parent_class;
222 
223     void (*realize)(PCIDevice *dev, Error **errp);
224     PCIUnregisterFunc *exit;
225     PCIConfigReadFunc *config_read;
226     PCIConfigWriteFunc *config_write;
227 
228     uint16_t vendor_id;
229     uint16_t device_id;
230     uint8_t revision;
231     uint16_t class_id;
232     uint16_t subsystem_vendor_id;       /* only for header type = 0 */
233     uint16_t subsystem_id;              /* only for header type = 0 */
234 
235     /*
236      * pci-to-pci bridge or normal device.
237      * This doesn't mean pci host switch.
238      * When card bus bridge is supported, this would be enhanced.
239      */
240     bool is_bridge;
241 
242     /* rom bar */
243     const char *romfile;
244 };
245 
246 typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev);
247 typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector,
248                                       MSIMessage msg);
249 typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector);
250 typedef void (*MSIVectorPollNotifier)(PCIDevice *dev,
251                                       unsigned int vector_start,
252                                       unsigned int vector_end);
253 
254 enum PCIReqIDType {
255     PCI_REQ_ID_INVALID = 0,
256     PCI_REQ_ID_BDF,
257     PCI_REQ_ID_SECONDARY_BUS,
258     PCI_REQ_ID_MAX,
259 };
260 typedef enum PCIReqIDType PCIReqIDType;
261 
262 struct PCIReqIDCache {
263     PCIDevice *dev;
264     PCIReqIDType type;
265 };
266 typedef struct PCIReqIDCache PCIReqIDCache;
267 
268 struct PCIDevice {
269     DeviceState qdev;
270     bool partially_hotplugged;
271 
272     /* PCI config space */
273     uint8_t *config;
274 
275     /* Used to enable config checks on load. Note that writable bits are
276      * never checked even if set in cmask. */
277     uint8_t *cmask;
278 
279     /* Used to implement R/W bytes */
280     uint8_t *wmask;
281 
282     /* Used to implement RW1C(Write 1 to Clear) bytes */
283     uint8_t *w1cmask;
284 
285     /* Used to allocate config space for capabilities. */
286     uint8_t *used;
287 
288     /* the following fields are read only */
289     int32_t devfn;
290     /* Cached device to fetch requester ID from, to avoid the PCI
291      * tree walking every time we invoke PCI request (e.g.,
292      * MSI). For conventional PCI root complex, this field is
293      * meaningless. */
294     PCIReqIDCache requester_id_cache;
295     char name[64];
296     PCIIORegion io_regions[PCI_NUM_REGIONS];
297     AddressSpace bus_master_as;
298     MemoryRegion bus_master_container_region;
299     MemoryRegion bus_master_enable_region;
300 
301     /* do not access the following fields */
302     PCIConfigReadFunc *config_read;
303     PCIConfigWriteFunc *config_write;
304 
305     /* Legacy PCI VGA regions */
306     MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS];
307     bool has_vga;
308 
309     /* Current IRQ levels.  Used internally by the generic PCI code.  */
310     uint8_t irq_state;
311 
312     /* Capability bits */
313     uint32_t cap_present;
314 
315     /* Offset of MSI-X capability in config space */
316     uint8_t msix_cap;
317 
318     /* MSI-X entries */
319     int msix_entries_nr;
320 
321     /* Space to store MSIX table & pending bit array */
322     uint8_t *msix_table;
323     uint8_t *msix_pba;
324     /* MemoryRegion container for msix exclusive BAR setup */
325     MemoryRegion msix_exclusive_bar;
326     /* Memory Regions for MSIX table and pending bit entries. */
327     MemoryRegion msix_table_mmio;
328     MemoryRegion msix_pba_mmio;
329     /* Reference-count for entries actually in use by driver. */
330     unsigned *msix_entry_used;
331     /* MSIX function mask set or MSIX disabled */
332     bool msix_function_masked;
333     /* Version id needed for VMState */
334     int32_t version_id;
335 
336     /* Offset of MSI capability in config space */
337     uint8_t msi_cap;
338 
339     /* PCI Express */
340     PCIExpressDevice exp;
341 
342     /* SHPC */
343     SHPCDevice *shpc;
344 
345     /* Location of option rom */
346     char *romfile;
347     uint32_t romsize;
348     bool has_rom;
349     MemoryRegion rom;
350     uint32_t rom_bar;
351 
352     /* INTx routing notifier */
353     PCIINTxRoutingNotifier intx_routing_notifier;
354 
355     /* MSI-X notifiers */
356     MSIVectorUseNotifier msix_vector_use_notifier;
357     MSIVectorReleaseNotifier msix_vector_release_notifier;
358     MSIVectorPollNotifier msix_vector_poll_notifier;
359 
360     /* ID of standby device in net_failover pair */
361     char *failover_pair_id;
362 };
363 
364 void pci_register_bar(PCIDevice *pci_dev, int region_num,
365                       uint8_t attr, MemoryRegion *memory);
366 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
367                       MemoryRegion *io_lo, MemoryRegion *io_hi);
368 void pci_unregister_vga(PCIDevice *pci_dev);
369 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
370 
371 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
372                        uint8_t offset, uint8_t size,
373                        Error **errp);
374 
375 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
376 
377 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
378 
379 
380 uint32_t pci_default_read_config(PCIDevice *d,
381                                  uint32_t address, int len);
382 void pci_default_write_config(PCIDevice *d,
383                               uint32_t address, uint32_t val, int len);
384 void pci_device_save(PCIDevice *s, QEMUFile *f);
385 int pci_device_load(PCIDevice *s, QEMUFile *f);
386 MemoryRegion *pci_address_space(PCIDevice *dev);
387 MemoryRegion *pci_address_space_io(PCIDevice *dev);
388 
389 /*
390  * Should not normally be used by devices. For use by sPAPR target
391  * where QEMU emulates firmware.
392  */
393 int pci_bar(PCIDevice *d, int reg);
394 
395 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
396 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
397 typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin);
398 
399 #define TYPE_PCI_BUS "PCI"
400 OBJECT_DECLARE_TYPE(PCIBus, PCIBusClass, PCI_BUS)
401 #define TYPE_PCIE_BUS "PCIE"
402 
403 bool pci_bus_is_express(PCIBus *bus);
404 
405 void pci_root_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent,
406                               const char *name,
407                               MemoryRegion *address_space_mem,
408                               MemoryRegion *address_space_io,
409                               uint8_t devfn_min, const char *typename);
410 PCIBus *pci_root_bus_new(DeviceState *parent, const char *name,
411                          MemoryRegion *address_space_mem,
412                          MemoryRegion *address_space_io,
413                          uint8_t devfn_min, const char *typename);
414 void pci_root_bus_cleanup(PCIBus *bus);
415 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
416                   void *irq_opaque, int nirq);
417 void pci_bus_irqs_cleanup(PCIBus *bus);
418 int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
419 /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */
420 static inline int pci_swizzle(int slot, int pin)
421 {
422     return (slot + pin) % PCI_NUM_PINS;
423 }
424 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin);
425 PCIBus *pci_register_root_bus(DeviceState *parent, const char *name,
426                               pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
427                               void *irq_opaque,
428                               MemoryRegion *address_space_mem,
429                               MemoryRegion *address_space_io,
430                               uint8_t devfn_min, int nirq,
431                               const char *typename);
432 void pci_unregister_root_bus(PCIBus *bus);
433 void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn);
434 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin);
435 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new);
436 void pci_bus_fire_intx_routing_notifier(PCIBus *bus);
437 void pci_device_set_intx_routing_notifier(PCIDevice *dev,
438                                           PCIINTxRoutingNotifier notifier);
439 void pci_device_reset(PCIDevice *dev);
440 
441 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus,
442                                const char *default_model,
443                                const char *default_devaddr);
444 
445 PCIDevice *pci_vga_init(PCIBus *bus);
446 
447 static inline PCIBus *pci_get_bus(const PCIDevice *dev)
448 {
449     return PCI_BUS(qdev_get_parent_bus(DEVICE(dev)));
450 }
451 int pci_bus_num(PCIBus *s);
452 static inline int pci_dev_bus_num(const PCIDevice *dev)
453 {
454     return pci_bus_num(pci_get_bus(dev));
455 }
456 
457 int pci_bus_numa_node(PCIBus *bus);
458 void pci_for_each_device(PCIBus *bus, int bus_num,
459                          void (*fn)(PCIBus *bus, PCIDevice *d, void *opaque),
460                          void *opaque);
461 void pci_for_each_device_reverse(PCIBus *bus, int bus_num,
462                                  void (*fn)(PCIBus *bus, PCIDevice *d,
463                                             void *opaque),
464                                  void *opaque);
465 void pci_for_each_bus_depth_first(PCIBus *bus,
466                                   void *(*begin)(PCIBus *bus, void *parent_state),
467                                   void (*end)(PCIBus *bus, void *state),
468                                   void *parent_state);
469 PCIDevice *pci_get_function_0(PCIDevice *pci_dev);
470 
471 /* Use this wrapper when specific scan order is not required. */
472 static inline
473 void pci_for_each_bus(PCIBus *bus,
474                       void (*fn)(PCIBus *bus, void *opaque),
475                       void *opaque)
476 {
477     pci_for_each_bus_depth_first(bus, NULL, fn, opaque);
478 }
479 
480 PCIBus *pci_device_root_bus(const PCIDevice *d);
481 const char *pci_root_bus_path(PCIDevice *dev);
482 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
483 int pci_qdev_find_device(const char *id, PCIDevice **pdev);
484 void pci_bus_get_w64_range(PCIBus *bus, Range *range);
485 
486 void pci_device_deassert_intx(PCIDevice *dev);
487 
488 typedef AddressSpace *(*PCIIOMMUFunc)(PCIBus *, void *, int);
489 
490 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev);
491 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque);
492 
493 static inline void
494 pci_set_byte(uint8_t *config, uint8_t val)
495 {
496     *config = val;
497 }
498 
499 static inline uint8_t
500 pci_get_byte(const uint8_t *config)
501 {
502     return *config;
503 }
504 
505 static inline void
506 pci_set_word(uint8_t *config, uint16_t val)
507 {
508     stw_le_p(config, val);
509 }
510 
511 static inline uint16_t
512 pci_get_word(const uint8_t *config)
513 {
514     return lduw_le_p(config);
515 }
516 
517 static inline void
518 pci_set_long(uint8_t *config, uint32_t val)
519 {
520     stl_le_p(config, val);
521 }
522 
523 static inline uint32_t
524 pci_get_long(const uint8_t *config)
525 {
526     return ldl_le_p(config);
527 }
528 
529 /*
530  * PCI capabilities and/or their fields
531  * are generally DWORD aligned only so
532  * mechanism used by pci_set/get_quad()
533  * must be tolerant to unaligned pointers
534  *
535  */
536 static inline void
537 pci_set_quad(uint8_t *config, uint64_t val)
538 {
539     stq_le_p(config, val);
540 }
541 
542 static inline uint64_t
543 pci_get_quad(const uint8_t *config)
544 {
545     return ldq_le_p(config);
546 }
547 
548 static inline void
549 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
550 {
551     pci_set_word(&pci_config[PCI_VENDOR_ID], val);
552 }
553 
554 static inline void
555 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
556 {
557     pci_set_word(&pci_config[PCI_DEVICE_ID], val);
558 }
559 
560 static inline void
561 pci_config_set_revision(uint8_t *pci_config, uint8_t val)
562 {
563     pci_set_byte(&pci_config[PCI_REVISION_ID], val);
564 }
565 
566 static inline void
567 pci_config_set_class(uint8_t *pci_config, uint16_t val)
568 {
569     pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
570 }
571 
572 static inline void
573 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
574 {
575     pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
576 }
577 
578 static inline void
579 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
580 {
581     pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
582 }
583 
584 /*
585  * helper functions to do bit mask operation on configuration space.
586  * Just to set bit, use test-and-set and discard returned value.
587  * Just to clear bit, use test-and-clear and discard returned value.
588  * NOTE: They aren't atomic.
589  */
590 static inline uint8_t
591 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask)
592 {
593     uint8_t val = pci_get_byte(config);
594     pci_set_byte(config, val & ~mask);
595     return val & mask;
596 }
597 
598 static inline uint8_t
599 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask)
600 {
601     uint8_t val = pci_get_byte(config);
602     pci_set_byte(config, val | mask);
603     return val & mask;
604 }
605 
606 static inline uint16_t
607 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask)
608 {
609     uint16_t val = pci_get_word(config);
610     pci_set_word(config, val & ~mask);
611     return val & mask;
612 }
613 
614 static inline uint16_t
615 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask)
616 {
617     uint16_t val = pci_get_word(config);
618     pci_set_word(config, val | mask);
619     return val & mask;
620 }
621 
622 static inline uint32_t
623 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask)
624 {
625     uint32_t val = pci_get_long(config);
626     pci_set_long(config, val & ~mask);
627     return val & mask;
628 }
629 
630 static inline uint32_t
631 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask)
632 {
633     uint32_t val = pci_get_long(config);
634     pci_set_long(config, val | mask);
635     return val & mask;
636 }
637 
638 static inline uint64_t
639 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask)
640 {
641     uint64_t val = pci_get_quad(config);
642     pci_set_quad(config, val & ~mask);
643     return val & mask;
644 }
645 
646 static inline uint64_t
647 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask)
648 {
649     uint64_t val = pci_get_quad(config);
650     pci_set_quad(config, val | mask);
651     return val & mask;
652 }
653 
654 /* Access a register specified by a mask */
655 static inline void
656 pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg)
657 {
658     uint8_t val = pci_get_byte(config);
659     uint8_t rval = reg << ctz32(mask);
660     pci_set_byte(config, (~mask & val) | (mask & rval));
661 }
662 
663 static inline uint8_t
664 pci_get_byte_by_mask(uint8_t *config, uint8_t mask)
665 {
666     uint8_t val = pci_get_byte(config);
667     return (val & mask) >> ctz32(mask);
668 }
669 
670 static inline void
671 pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg)
672 {
673     uint16_t val = pci_get_word(config);
674     uint16_t rval = reg << ctz32(mask);
675     pci_set_word(config, (~mask & val) | (mask & rval));
676 }
677 
678 static inline uint16_t
679 pci_get_word_by_mask(uint8_t *config, uint16_t mask)
680 {
681     uint16_t val = pci_get_word(config);
682     return (val & mask) >> ctz32(mask);
683 }
684 
685 static inline void
686 pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg)
687 {
688     uint32_t val = pci_get_long(config);
689     uint32_t rval = reg << ctz32(mask);
690     pci_set_long(config, (~mask & val) | (mask & rval));
691 }
692 
693 static inline uint32_t
694 pci_get_long_by_mask(uint8_t *config, uint32_t mask)
695 {
696     uint32_t val = pci_get_long(config);
697     return (val & mask) >> ctz32(mask);
698 }
699 
700 static inline void
701 pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg)
702 {
703     uint64_t val = pci_get_quad(config);
704     uint64_t rval = reg << ctz32(mask);
705     pci_set_quad(config, (~mask & val) | (mask & rval));
706 }
707 
708 static inline uint64_t
709 pci_get_quad_by_mask(uint8_t *config, uint64_t mask)
710 {
711     uint64_t val = pci_get_quad(config);
712     return (val & mask) >> ctz32(mask);
713 }
714 
715 PCIDevice *pci_new_multifunction(int devfn, bool multifunction,
716                                     const char *name);
717 PCIDevice *pci_new(int devfn, const char *name);
718 bool pci_realize_and_unref(PCIDevice *dev, PCIBus *bus, Error **errp);
719 
720 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
721                                            bool multifunction,
722                                            const char *name);
723 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
724 
725 void lsi53c8xx_handle_legacy_cmdline(DeviceState *lsi_dev);
726 
727 qemu_irq pci_allocate_irq(PCIDevice *pci_dev);
728 void pci_set_irq(PCIDevice *pci_dev, int level);
729 
730 static inline void pci_irq_assert(PCIDevice *pci_dev)
731 {
732     pci_set_irq(pci_dev, 1);
733 }
734 
735 static inline void pci_irq_deassert(PCIDevice *pci_dev)
736 {
737     pci_set_irq(pci_dev, 0);
738 }
739 
740 /*
741  * FIXME: PCI does not work this way.
742  * All the callers to this method should be fixed.
743  */
744 static inline void pci_irq_pulse(PCIDevice *pci_dev)
745 {
746     pci_irq_assert(pci_dev);
747     pci_irq_deassert(pci_dev);
748 }
749 
750 static inline int pci_is_express(const PCIDevice *d)
751 {
752     return d->cap_present & QEMU_PCI_CAP_EXPRESS;
753 }
754 
755 static inline int pci_is_express_downstream_port(const PCIDevice *d)
756 {
757     uint8_t type;
758 
759     if (!pci_is_express(d) || !d->exp.exp_cap) {
760         return 0;
761     }
762 
763     type = pcie_cap_get_type(d);
764 
765     return type == PCI_EXP_TYPE_DOWNSTREAM || type == PCI_EXP_TYPE_ROOT_PORT;
766 }
767 
768 static inline uint32_t pci_config_size(const PCIDevice *d)
769 {
770     return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
771 }
772 
773 static inline uint16_t pci_get_bdf(PCIDevice *dev)
774 {
775     return PCI_BUILD_BDF(pci_bus_num(pci_get_bus(dev)), dev->devfn);
776 }
777 
778 uint16_t pci_requester_id(PCIDevice *dev);
779 
780 /* DMA access functions */
781 static inline AddressSpace *pci_get_address_space(PCIDevice *dev)
782 {
783     return &dev->bus_master_as;
784 }
785 
786 /**
787  * pci_dma_rw: Read from or write to an address space from PCI device.
788  *
789  * Return a MemTxResult indicating whether the operation succeeded
790  * or failed (eg unassigned memory, device rejected the transaction,
791  * IOMMU fault).
792  *
793  * @dev: #PCIDevice doing the memory access
794  * @addr: address within the #PCIDevice address space
795  * @buf: buffer with the data transferred
796  * @len: the number of bytes to read or write
797  * @dir: indicates the transfer direction
798  */
799 static inline MemTxResult pci_dma_rw(PCIDevice *dev, dma_addr_t addr,
800                                      void *buf, dma_addr_t len,
801                                      DMADirection dir)
802 {
803     return dma_memory_rw(pci_get_address_space(dev), addr, buf, len, dir);
804 }
805 
806 /**
807  * pci_dma_read: Read from an address space from PCI device.
808  *
809  * Return a MemTxResult indicating whether the operation succeeded
810  * or failed (eg unassigned memory, device rejected the transaction,
811  * IOMMU fault).  Called within RCU critical section.
812  *
813  * @dev: #PCIDevice doing the memory access
814  * @addr: address within the #PCIDevice address space
815  * @buf: buffer with the data transferred
816  * @len: length of the data transferred
817  */
818 static inline MemTxResult pci_dma_read(PCIDevice *dev, dma_addr_t addr,
819                                        void *buf, dma_addr_t len)
820 {
821     return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE);
822 }
823 
824 /**
825  * pci_dma_write: Write to address space from PCI device.
826  *
827  * Return a MemTxResult indicating whether the operation succeeded
828  * or failed (eg unassigned memory, device rejected the transaction,
829  * IOMMU fault).
830  *
831  * @dev: #PCIDevice doing the memory access
832  * @addr: address within the #PCIDevice address space
833  * @buf: buffer with the data transferred
834  * @len: the number of bytes to write
835  */
836 static inline MemTxResult pci_dma_write(PCIDevice *dev, dma_addr_t addr,
837                                         const void *buf, dma_addr_t len)
838 {
839     return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE);
840 }
841 
842 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits)                              \
843     static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev,      \
844                                                    dma_addr_t addr)     \
845     {                                                                   \
846         return ld##_l##_dma(pci_get_address_space(dev), addr);          \
847     }                                                                   \
848     static inline void st##_s##_pci_dma(PCIDevice *dev,                 \
849                                         dma_addr_t addr, uint##_bits##_t val) \
850     {                                                                   \
851         st##_s##_dma(pci_get_address_space(dev), addr, val);            \
852     }
853 
854 PCI_DMA_DEFINE_LDST(ub, b, 8);
855 PCI_DMA_DEFINE_LDST(uw_le, w_le, 16)
856 PCI_DMA_DEFINE_LDST(l_le, l_le, 32);
857 PCI_DMA_DEFINE_LDST(q_le, q_le, 64);
858 PCI_DMA_DEFINE_LDST(uw_be, w_be, 16)
859 PCI_DMA_DEFINE_LDST(l_be, l_be, 32);
860 PCI_DMA_DEFINE_LDST(q_be, q_be, 64);
861 
862 #undef PCI_DMA_DEFINE_LDST
863 
864 static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr,
865                                 dma_addr_t *plen, DMADirection dir)
866 {
867     void *buf;
868 
869     buf = dma_memory_map(pci_get_address_space(dev), addr, plen, dir);
870     return buf;
871 }
872 
873 static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len,
874                                  DMADirection dir, dma_addr_t access_len)
875 {
876     dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len);
877 }
878 
879 static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev,
880                                        int alloc_hint)
881 {
882     qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev));
883 }
884 
885 extern const VMStateDescription vmstate_pci_device;
886 
887 #define VMSTATE_PCI_DEVICE(_field, _state) {                         \
888     .name       = (stringify(_field)),                               \
889     .size       = sizeof(PCIDevice),                                 \
890     .vmsd       = &vmstate_pci_device,                               \
891     .flags      = VMS_STRUCT,                                        \
892     .offset     = vmstate_offset_value(_state, _field, PCIDevice),   \
893 }
894 
895 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) {                 \
896     .name       = (stringify(_field)),                               \
897     .size       = sizeof(PCIDevice),                                 \
898     .vmsd       = &vmstate_pci_device,                               \
899     .flags      = VMS_STRUCT|VMS_POINTER,                            \
900     .offset     = vmstate_offset_pointer(_state, _field, PCIDevice), \
901 }
902 
903 MSIMessage pci_get_msi_message(PCIDevice *dev, int vector);
904 
905 #endif
906