xref: /openbmc/qemu/include/hw/pci/pci.h (revision bc5c4f21)
1 #ifndef QEMU_PCI_H
2 #define QEMU_PCI_H
3 
4 #include "hw/qdev.h"
5 #include "exec/memory.h"
6 #include "sysemu/dma.h"
7 
8 /* PCI includes legacy ISA access.  */
9 #include "hw/isa/isa.h"
10 
11 #include "hw/pci/pcie.h"
12 
13 /* PCI bus */
14 
15 #define PCI_DEVFN(slot, func)   ((((slot) & 0x1f) << 3) | ((func) & 0x07))
16 #define PCI_BUS_NUM(x)          (((x) >> 8) & 0xff)
17 #define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
18 #define PCI_FUNC(devfn)         ((devfn) & 0x07)
19 #define PCI_BUILD_BDF(bus, devfn)     ((bus << 8) | (devfn))
20 #define PCI_BUS_MAX             256
21 #define PCI_DEVFN_MAX           256
22 #define PCI_SLOT_MAX            32
23 #define PCI_FUNC_MAX            8
24 
25 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
26 #include "hw/pci/pci_ids.h"
27 
28 /* QEMU-specific Vendor and Device ID definitions */
29 
30 /* IBM (0x1014) */
31 #define PCI_DEVICE_ID_IBM_440GX          0x027f
32 #define PCI_DEVICE_ID_IBM_OPENPIC2       0xffff
33 
34 /* Hitachi (0x1054) */
35 #define PCI_VENDOR_ID_HITACHI            0x1054
36 #define PCI_DEVICE_ID_HITACHI_SH7751R    0x350e
37 
38 /* Apple (0x106b) */
39 #define PCI_DEVICE_ID_APPLE_343S1201     0x0010
40 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI  0x001e
41 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI    0x001f
42 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL   0x0022
43 #define PCI_DEVICE_ID_APPLE_IPID_USB     0x003f
44 
45 /* Realtek (0x10ec) */
46 #define PCI_DEVICE_ID_REALTEK_8029       0x8029
47 
48 /* Xilinx (0x10ee) */
49 #define PCI_DEVICE_ID_XILINX_XC2VP30     0x0300
50 
51 /* Marvell (0x11ab) */
52 #define PCI_DEVICE_ID_MARVELL_GT6412X    0x4620
53 
54 /* QEMU/Bochs VGA (0x1234) */
55 #define PCI_VENDOR_ID_QEMU               0x1234
56 #define PCI_DEVICE_ID_QEMU_VGA           0x1111
57 
58 /* VMWare (0x15ad) */
59 #define PCI_VENDOR_ID_VMWARE             0x15ad
60 #define PCI_DEVICE_ID_VMWARE_SVGA2       0x0405
61 #define PCI_DEVICE_ID_VMWARE_SVGA        0x0710
62 #define PCI_DEVICE_ID_VMWARE_NET         0x0720
63 #define PCI_DEVICE_ID_VMWARE_SCSI        0x0730
64 #define PCI_DEVICE_ID_VMWARE_PVSCSI      0x07C0
65 #define PCI_DEVICE_ID_VMWARE_IDE         0x1729
66 #define PCI_DEVICE_ID_VMWARE_VMXNET3     0x07B0
67 
68 /* Intel (0x8086) */
69 #define PCI_DEVICE_ID_INTEL_82551IT      0x1209
70 #define PCI_DEVICE_ID_INTEL_82557        0x1229
71 #define PCI_DEVICE_ID_INTEL_82801IR      0x2922
72 
73 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
74 #define PCI_VENDOR_ID_REDHAT_QUMRANET    0x1af4
75 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
76 #define PCI_SUBDEVICE_ID_QEMU            0x1100
77 
78 #define PCI_DEVICE_ID_VIRTIO_NET         0x1000
79 #define PCI_DEVICE_ID_VIRTIO_BLOCK       0x1001
80 #define PCI_DEVICE_ID_VIRTIO_BALLOON     0x1002
81 #define PCI_DEVICE_ID_VIRTIO_CONSOLE     0x1003
82 #define PCI_DEVICE_ID_VIRTIO_SCSI        0x1004
83 #define PCI_DEVICE_ID_VIRTIO_RNG         0x1005
84 #define PCI_DEVICE_ID_VIRTIO_9P          0x1009
85 #define PCI_DEVICE_ID_VIRTIO_VSOCK       0x1012
86 
87 #define PCI_VENDOR_ID_REDHAT             0x1b36
88 #define PCI_DEVICE_ID_REDHAT_BRIDGE      0x0001
89 #define PCI_DEVICE_ID_REDHAT_SERIAL      0x0002
90 #define PCI_DEVICE_ID_REDHAT_SERIAL2     0x0003
91 #define PCI_DEVICE_ID_REDHAT_SERIAL4     0x0004
92 #define PCI_DEVICE_ID_REDHAT_TEST        0x0005
93 #define PCI_DEVICE_ID_REDHAT_ROCKER      0x0006
94 #define PCI_DEVICE_ID_REDHAT_SDHCI       0x0007
95 #define PCI_DEVICE_ID_REDHAT_PCIE_HOST   0x0008
96 #define PCI_DEVICE_ID_REDHAT_PXB         0x0009
97 #define PCI_DEVICE_ID_REDHAT_BRIDGE_SEAT 0x000a
98 #define PCI_DEVICE_ID_REDHAT_PXB_PCIE    0x000b
99 #define PCI_DEVICE_ID_REDHAT_PCIE_RP     0x000c
100 #define PCI_DEVICE_ID_REDHAT_QXL         0x0100
101 
102 #define FMT_PCIBUS                      PRIx64
103 
104 typedef uint64_t pcibus_t;
105 
106 struct PCIHostDeviceAddress {
107     unsigned int domain;
108     unsigned int bus;
109     unsigned int slot;
110     unsigned int function;
111 };
112 
113 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
114                                 uint32_t address, uint32_t data, int len);
115 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
116                                    uint32_t address, int len);
117 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
118                                 pcibus_t addr, pcibus_t size, int type);
119 typedef void PCIUnregisterFunc(PCIDevice *pci_dev);
120 
121 typedef struct PCIIORegion {
122     pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
123 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
124     pcibus_t size;
125     uint8_t type;
126     MemoryRegion *memory;
127     MemoryRegion *address_space;
128 } PCIIORegion;
129 
130 #define PCI_ROM_SLOT 6
131 #define PCI_NUM_REGIONS 7
132 
133 enum {
134     QEMU_PCI_VGA_MEM,
135     QEMU_PCI_VGA_IO_LO,
136     QEMU_PCI_VGA_IO_HI,
137     QEMU_PCI_VGA_NUM_REGIONS,
138 };
139 
140 #define QEMU_PCI_VGA_MEM_BASE 0xa0000
141 #define QEMU_PCI_VGA_MEM_SIZE 0x20000
142 #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0
143 #define QEMU_PCI_VGA_IO_LO_SIZE 0xc
144 #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0
145 #define QEMU_PCI_VGA_IO_HI_SIZE 0x20
146 
147 #include "hw/pci/pci_regs.h"
148 
149 /* PCI HEADER_TYPE */
150 #define  PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
151 
152 /* Size of the standard PCI config header */
153 #define PCI_CONFIG_HEADER_SIZE 0x40
154 /* Size of the standard PCI config space */
155 #define PCI_CONFIG_SPACE_SIZE 0x100
156 /* Size of the standard PCIe config space: 4KB */
157 #define PCIE_CONFIG_SPACE_SIZE  0x1000
158 
159 #define PCI_NUM_PINS 4 /* A-D */
160 
161 /* Bits in cap_present field. */
162 enum {
163     QEMU_PCI_CAP_MSI = 0x1,
164     QEMU_PCI_CAP_MSIX = 0x2,
165     QEMU_PCI_CAP_EXPRESS = 0x4,
166 
167     /* multifunction capable device */
168 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR        3
169     QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
170 
171     /* command register SERR bit enabled */
172 #define QEMU_PCI_CAP_SERR_BITNR 4
173     QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
174     /* Standard hot plug controller. */
175 #define QEMU_PCI_SHPC_BITNR 5
176     QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR),
177 #define QEMU_PCI_SLOTID_BITNR 6
178     QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR),
179     /* PCI Express capability - Power Controller Present */
180 #define QEMU_PCIE_SLTCAP_PCP_BITNR 7
181     QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR),
182     /* Link active status in endpoint capability is always set */
183 #define QEMU_PCIE_LNKSTA_DLLLA_BITNR 8
184     QEMU_PCIE_LNKSTA_DLLLA = (1 << QEMU_PCIE_LNKSTA_DLLLA_BITNR),
185 };
186 
187 #define TYPE_PCI_DEVICE "pci-device"
188 #define PCI_DEVICE(obj) \
189      OBJECT_CHECK(PCIDevice, (obj), TYPE_PCI_DEVICE)
190 #define PCI_DEVICE_CLASS(klass) \
191      OBJECT_CLASS_CHECK(PCIDeviceClass, (klass), TYPE_PCI_DEVICE)
192 #define PCI_DEVICE_GET_CLASS(obj) \
193      OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE)
194 
195 typedef struct PCIINTxRoute {
196     enum {
197         PCI_INTX_ENABLED,
198         PCI_INTX_INVERTED,
199         PCI_INTX_DISABLED,
200     } mode;
201     int irq;
202 } PCIINTxRoute;
203 
204 typedef struct PCIDeviceClass {
205     DeviceClass parent_class;
206 
207     void (*realize)(PCIDevice *dev, Error **errp);
208     int (*init)(PCIDevice *dev);/* TODO convert to realize() and remove */
209     PCIUnregisterFunc *exit;
210     PCIConfigReadFunc *config_read;
211     PCIConfigWriteFunc *config_write;
212 
213     uint16_t vendor_id;
214     uint16_t device_id;
215     uint8_t revision;
216     uint16_t class_id;
217     uint16_t subsystem_vendor_id;       /* only for header type = 0 */
218     uint16_t subsystem_id;              /* only for header type = 0 */
219 
220     /*
221      * pci-to-pci bridge or normal device.
222      * This doesn't mean pci host switch.
223      * When card bus bridge is supported, this would be enhanced.
224      */
225     int is_bridge;
226 
227     /* pcie stuff */
228     int is_express;   /* is this device pci express? */
229 
230     /* rom bar */
231     const char *romfile;
232 } PCIDeviceClass;
233 
234 typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev);
235 typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector,
236                                       MSIMessage msg);
237 typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector);
238 typedef void (*MSIVectorPollNotifier)(PCIDevice *dev,
239                                       unsigned int vector_start,
240                                       unsigned int vector_end);
241 
242 enum PCIReqIDType {
243     PCI_REQ_ID_INVALID = 0,
244     PCI_REQ_ID_BDF,
245     PCI_REQ_ID_SECONDARY_BUS,
246     PCI_REQ_ID_MAX,
247 };
248 typedef enum PCIReqIDType PCIReqIDType;
249 
250 struct PCIReqIDCache {
251     PCIDevice *dev;
252     PCIReqIDType type;
253 };
254 typedef struct PCIReqIDCache PCIReqIDCache;
255 
256 struct PCIDevice {
257     DeviceState qdev;
258 
259     /* PCI config space */
260     uint8_t *config;
261 
262     /* Used to enable config checks on load. Note that writable bits are
263      * never checked even if set in cmask. */
264     uint8_t *cmask;
265 
266     /* Used to implement R/W bytes */
267     uint8_t *wmask;
268 
269     /* Used to implement RW1C(Write 1 to Clear) bytes */
270     uint8_t *w1cmask;
271 
272     /* Used to allocate config space for capabilities. */
273     uint8_t *used;
274 
275     /* the following fields are read only */
276     PCIBus *bus;
277     int32_t devfn;
278     /* Cached device to fetch requester ID from, to avoid the PCI
279      * tree walking every time we invoke PCI request (e.g.,
280      * MSI). For conventional PCI root complex, this field is
281      * meaningless. */
282     PCIReqIDCache requester_id_cache;
283     char name[64];
284     PCIIORegion io_regions[PCI_NUM_REGIONS];
285     AddressSpace bus_master_as;
286     MemoryRegion bus_master_enable_region;
287 
288     /* do not access the following fields */
289     PCIConfigReadFunc *config_read;
290     PCIConfigWriteFunc *config_write;
291 
292     /* Legacy PCI VGA regions */
293     MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS];
294     bool has_vga;
295 
296     /* Current IRQ levels.  Used internally by the generic PCI code.  */
297     uint8_t irq_state;
298 
299     /* Capability bits */
300     uint32_t cap_present;
301 
302     /* Offset of MSI-X capability in config space */
303     uint8_t msix_cap;
304 
305     /* MSI-X entries */
306     int msix_entries_nr;
307 
308     /* Space to store MSIX table & pending bit array */
309     uint8_t *msix_table;
310     uint8_t *msix_pba;
311     /* MemoryRegion container for msix exclusive BAR setup */
312     MemoryRegion msix_exclusive_bar;
313     /* Memory Regions for MSIX table and pending bit entries. */
314     MemoryRegion msix_table_mmio;
315     MemoryRegion msix_pba_mmio;
316     /* Reference-count for entries actually in use by driver. */
317     unsigned *msix_entry_used;
318     /* MSIX function mask set or MSIX disabled */
319     bool msix_function_masked;
320     /* Version id needed for VMState */
321     int32_t version_id;
322 
323     /* Offset of MSI capability in config space */
324     uint8_t msi_cap;
325 
326     /* PCI Express */
327     PCIExpressDevice exp;
328 
329     /* SHPC */
330     SHPCDevice *shpc;
331 
332     /* Location of option rom */
333     char *romfile;
334     bool has_rom;
335     MemoryRegion rom;
336     uint32_t rom_bar;
337 
338     /* INTx routing notifier */
339     PCIINTxRoutingNotifier intx_routing_notifier;
340 
341     /* MSI-X notifiers */
342     MSIVectorUseNotifier msix_vector_use_notifier;
343     MSIVectorReleaseNotifier msix_vector_release_notifier;
344     MSIVectorPollNotifier msix_vector_poll_notifier;
345 };
346 
347 void pci_register_bar(PCIDevice *pci_dev, int region_num,
348                       uint8_t attr, MemoryRegion *memory);
349 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
350                       MemoryRegion *io_lo, MemoryRegion *io_hi);
351 void pci_unregister_vga(PCIDevice *pci_dev);
352 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
353 
354 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
355                        uint8_t offset, uint8_t size);
356 int pci_add_capability2(PCIDevice *pdev, uint8_t cap_id,
357                        uint8_t offset, uint8_t size,
358                        Error **errp);
359 
360 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
361 
362 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
363 
364 
365 uint32_t pci_default_read_config(PCIDevice *d,
366                                  uint32_t address, int len);
367 void pci_default_write_config(PCIDevice *d,
368                               uint32_t address, uint32_t val, int len);
369 void pci_device_save(PCIDevice *s, QEMUFile *f);
370 int pci_device_load(PCIDevice *s, QEMUFile *f);
371 MemoryRegion *pci_address_space(PCIDevice *dev);
372 MemoryRegion *pci_address_space_io(PCIDevice *dev);
373 
374 /*
375  * Should not normally be used by devices. For use by sPAPR target
376  * where QEMU emulates firmware.
377  */
378 int pci_bar(PCIDevice *d, int reg);
379 
380 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
381 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
382 typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin);
383 
384 #define TYPE_PCI_BUS "PCI"
385 #define PCI_BUS(obj) OBJECT_CHECK(PCIBus, (obj), TYPE_PCI_BUS)
386 #define PCI_BUS_CLASS(klass) OBJECT_CLASS_CHECK(PCIBusClass, (klass), TYPE_PCI_BUS)
387 #define PCI_BUS_GET_CLASS(obj) OBJECT_GET_CLASS(PCIBusClass, (obj), TYPE_PCI_BUS)
388 #define TYPE_PCIE_BUS "PCIE"
389 
390 bool pci_bus_is_express(PCIBus *bus);
391 bool pci_bus_is_root(PCIBus *bus);
392 void pci_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent,
393                          const char *name,
394                          MemoryRegion *address_space_mem,
395                          MemoryRegion *address_space_io,
396                          uint8_t devfn_min, const char *typename);
397 PCIBus *pci_bus_new(DeviceState *parent, const char *name,
398                     MemoryRegion *address_space_mem,
399                     MemoryRegion *address_space_io,
400                     uint8_t devfn_min, const char *typename);
401 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
402                   void *irq_opaque, int nirq);
403 int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
404 /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */
405 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin);
406 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
407                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
408                          void *irq_opaque,
409                          MemoryRegion *address_space_mem,
410                          MemoryRegion *address_space_io,
411                          uint8_t devfn_min, int nirq, const char *typename);
412 void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn);
413 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin);
414 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new);
415 void pci_bus_fire_intx_routing_notifier(PCIBus *bus);
416 void pci_device_set_intx_routing_notifier(PCIDevice *dev,
417                                           PCIINTxRoutingNotifier notifier);
418 void pci_device_reset(PCIDevice *dev);
419 
420 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus,
421                                const char *default_model,
422                                const char *default_devaddr);
423 
424 PCIDevice *pci_vga_init(PCIBus *bus);
425 
426 int pci_bus_num(PCIBus *s);
427 int pci_bus_numa_node(PCIBus *bus);
428 void pci_for_each_device(PCIBus *bus, int bus_num,
429                          void (*fn)(PCIBus *bus, PCIDevice *d, void *opaque),
430                          void *opaque);
431 void pci_for_each_bus_depth_first(PCIBus *bus,
432                                   void *(*begin)(PCIBus *bus, void *parent_state),
433                                   void (*end)(PCIBus *bus, void *state),
434                                   void *parent_state);
435 PCIDevice *pci_get_function_0(PCIDevice *pci_dev);
436 
437 /* Use this wrapper when specific scan order is not required. */
438 static inline
439 void pci_for_each_bus(PCIBus *bus,
440                       void (*fn)(PCIBus *bus, void *opaque),
441                       void *opaque)
442 {
443     pci_for_each_bus_depth_first(bus, NULL, fn, opaque);
444 }
445 
446 PCIBus *pci_find_primary_bus(void);
447 PCIBus *pci_device_root_bus(const PCIDevice *d);
448 const char *pci_root_bus_path(PCIDevice *dev);
449 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
450 int pci_qdev_find_device(const char *id, PCIDevice **pdev);
451 void pci_bus_get_w64_range(PCIBus *bus, Range *range);
452 
453 void pci_device_deassert_intx(PCIDevice *dev);
454 
455 typedef AddressSpace *(*PCIIOMMUFunc)(PCIBus *, void *, int);
456 
457 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev);
458 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque);
459 
460 static inline void
461 pci_set_byte(uint8_t *config, uint8_t val)
462 {
463     *config = val;
464 }
465 
466 static inline uint8_t
467 pci_get_byte(const uint8_t *config)
468 {
469     return *config;
470 }
471 
472 static inline void
473 pci_set_word(uint8_t *config, uint16_t val)
474 {
475     stw_le_p(config, val);
476 }
477 
478 static inline uint16_t
479 pci_get_word(const uint8_t *config)
480 {
481     return lduw_le_p(config);
482 }
483 
484 static inline void
485 pci_set_long(uint8_t *config, uint32_t val)
486 {
487     stl_le_p(config, val);
488 }
489 
490 static inline uint32_t
491 pci_get_long(const uint8_t *config)
492 {
493     return ldl_le_p(config);
494 }
495 
496 /*
497  * PCI capabilities and/or their fields
498  * are generally DWORD aligned only so
499  * mechanism used by pci_set/get_quad()
500  * must be tolerant to unaligned pointers
501  *
502  */
503 static inline void
504 pci_set_quad(uint8_t *config, uint64_t val)
505 {
506     stq_le_p(config, val);
507 }
508 
509 static inline uint64_t
510 pci_get_quad(const uint8_t *config)
511 {
512     return ldq_le_p(config);
513 }
514 
515 static inline void
516 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
517 {
518     pci_set_word(&pci_config[PCI_VENDOR_ID], val);
519 }
520 
521 static inline void
522 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
523 {
524     pci_set_word(&pci_config[PCI_DEVICE_ID], val);
525 }
526 
527 static inline void
528 pci_config_set_revision(uint8_t *pci_config, uint8_t val)
529 {
530     pci_set_byte(&pci_config[PCI_REVISION_ID], val);
531 }
532 
533 static inline void
534 pci_config_set_class(uint8_t *pci_config, uint16_t val)
535 {
536     pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
537 }
538 
539 static inline void
540 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
541 {
542     pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
543 }
544 
545 static inline void
546 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
547 {
548     pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
549 }
550 
551 /*
552  * helper functions to do bit mask operation on configuration space.
553  * Just to set bit, use test-and-set and discard returned value.
554  * Just to clear bit, use test-and-clear and discard returned value.
555  * NOTE: They aren't atomic.
556  */
557 static inline uint8_t
558 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask)
559 {
560     uint8_t val = pci_get_byte(config);
561     pci_set_byte(config, val & ~mask);
562     return val & mask;
563 }
564 
565 static inline uint8_t
566 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask)
567 {
568     uint8_t val = pci_get_byte(config);
569     pci_set_byte(config, val | mask);
570     return val & mask;
571 }
572 
573 static inline uint16_t
574 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask)
575 {
576     uint16_t val = pci_get_word(config);
577     pci_set_word(config, val & ~mask);
578     return val & mask;
579 }
580 
581 static inline uint16_t
582 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask)
583 {
584     uint16_t val = pci_get_word(config);
585     pci_set_word(config, val | mask);
586     return val & mask;
587 }
588 
589 static inline uint32_t
590 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask)
591 {
592     uint32_t val = pci_get_long(config);
593     pci_set_long(config, val & ~mask);
594     return val & mask;
595 }
596 
597 static inline uint32_t
598 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask)
599 {
600     uint32_t val = pci_get_long(config);
601     pci_set_long(config, val | mask);
602     return val & mask;
603 }
604 
605 static inline uint64_t
606 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask)
607 {
608     uint64_t val = pci_get_quad(config);
609     pci_set_quad(config, val & ~mask);
610     return val & mask;
611 }
612 
613 static inline uint64_t
614 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask)
615 {
616     uint64_t val = pci_get_quad(config);
617     pci_set_quad(config, val | mask);
618     return val & mask;
619 }
620 
621 /* Access a register specified by a mask */
622 static inline void
623 pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg)
624 {
625     uint8_t val = pci_get_byte(config);
626     uint8_t rval = reg << ctz32(mask);
627     pci_set_byte(config, (~mask & val) | (mask & rval));
628 }
629 
630 static inline uint8_t
631 pci_get_byte_by_mask(uint8_t *config, uint8_t mask)
632 {
633     uint8_t val = pci_get_byte(config);
634     return (val & mask) >> ctz32(mask);
635 }
636 
637 static inline void
638 pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg)
639 {
640     uint16_t val = pci_get_word(config);
641     uint16_t rval = reg << ctz32(mask);
642     pci_set_word(config, (~mask & val) | (mask & rval));
643 }
644 
645 static inline uint16_t
646 pci_get_word_by_mask(uint8_t *config, uint16_t mask)
647 {
648     uint16_t val = pci_get_word(config);
649     return (val & mask) >> ctz32(mask);
650 }
651 
652 static inline void
653 pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg)
654 {
655     uint32_t val = pci_get_long(config);
656     uint32_t rval = reg << ctz32(mask);
657     pci_set_long(config, (~mask & val) | (mask & rval));
658 }
659 
660 static inline uint32_t
661 pci_get_long_by_mask(uint8_t *config, uint32_t mask)
662 {
663     uint32_t val = pci_get_long(config);
664     return (val & mask) >> ctz32(mask);
665 }
666 
667 static inline void
668 pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg)
669 {
670     uint64_t val = pci_get_quad(config);
671     uint64_t rval = reg << ctz32(mask);
672     pci_set_quad(config, (~mask & val) | (mask & rval));
673 }
674 
675 static inline uint64_t
676 pci_get_quad_by_mask(uint8_t *config, uint64_t mask)
677 {
678     uint64_t val = pci_get_quad(config);
679     return (val & mask) >> ctz32(mask);
680 }
681 
682 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
683                                     const char *name);
684 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
685                                            bool multifunction,
686                                            const char *name);
687 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name);
688 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
689 
690 qemu_irq pci_allocate_irq(PCIDevice *pci_dev);
691 void pci_set_irq(PCIDevice *pci_dev, int level);
692 
693 static inline void pci_irq_assert(PCIDevice *pci_dev)
694 {
695     pci_set_irq(pci_dev, 1);
696 }
697 
698 static inline void pci_irq_deassert(PCIDevice *pci_dev)
699 {
700     pci_set_irq(pci_dev, 0);
701 }
702 
703 /*
704  * FIXME: PCI does not work this way.
705  * All the callers to this method should be fixed.
706  */
707 static inline void pci_irq_pulse(PCIDevice *pci_dev)
708 {
709     pci_irq_assert(pci_dev);
710     pci_irq_deassert(pci_dev);
711 }
712 
713 static inline int pci_is_express(const PCIDevice *d)
714 {
715     return d->cap_present & QEMU_PCI_CAP_EXPRESS;
716 }
717 
718 static inline uint32_t pci_config_size(const PCIDevice *d)
719 {
720     return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
721 }
722 
723 static inline uint16_t pci_get_bdf(PCIDevice *dev)
724 {
725     return PCI_BUILD_BDF(pci_bus_num(dev->bus), dev->devfn);
726 }
727 
728 uint16_t pci_requester_id(PCIDevice *dev);
729 
730 /* DMA access functions */
731 static inline AddressSpace *pci_get_address_space(PCIDevice *dev)
732 {
733     return &dev->bus_master_as;
734 }
735 
736 static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr,
737                              void *buf, dma_addr_t len, DMADirection dir)
738 {
739     dma_memory_rw(pci_get_address_space(dev), addr, buf, len, dir);
740     return 0;
741 }
742 
743 static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr,
744                                void *buf, dma_addr_t len)
745 {
746     return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE);
747 }
748 
749 static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr,
750                                 const void *buf, dma_addr_t len)
751 {
752     return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE);
753 }
754 
755 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits)                              \
756     static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev,      \
757                                                    dma_addr_t addr)     \
758     {                                                                   \
759         return ld##_l##_dma(pci_get_address_space(dev), addr);          \
760     }                                                                   \
761     static inline void st##_s##_pci_dma(PCIDevice *dev,                 \
762                                         dma_addr_t addr, uint##_bits##_t val) \
763     {                                                                   \
764         st##_s##_dma(pci_get_address_space(dev), addr, val);            \
765     }
766 
767 PCI_DMA_DEFINE_LDST(ub, b, 8);
768 PCI_DMA_DEFINE_LDST(uw_le, w_le, 16)
769 PCI_DMA_DEFINE_LDST(l_le, l_le, 32);
770 PCI_DMA_DEFINE_LDST(q_le, q_le, 64);
771 PCI_DMA_DEFINE_LDST(uw_be, w_be, 16)
772 PCI_DMA_DEFINE_LDST(l_be, l_be, 32);
773 PCI_DMA_DEFINE_LDST(q_be, q_be, 64);
774 
775 #undef PCI_DMA_DEFINE_LDST
776 
777 static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr,
778                                 dma_addr_t *plen, DMADirection dir)
779 {
780     void *buf;
781 
782     buf = dma_memory_map(pci_get_address_space(dev), addr, plen, dir);
783     return buf;
784 }
785 
786 static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len,
787                                  DMADirection dir, dma_addr_t access_len)
788 {
789     dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len);
790 }
791 
792 static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev,
793                                        int alloc_hint)
794 {
795     qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev));
796 }
797 
798 extern const VMStateDescription vmstate_pci_device;
799 
800 #define VMSTATE_PCI_DEVICE(_field, _state) {                         \
801     .name       = (stringify(_field)),                               \
802     .size       = sizeof(PCIDevice),                                 \
803     .vmsd       = &vmstate_pci_device,                               \
804     .flags      = VMS_STRUCT,                                        \
805     .offset     = vmstate_offset_value(_state, _field, PCIDevice),   \
806 }
807 
808 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) {                 \
809     .name       = (stringify(_field)),                               \
810     .size       = sizeof(PCIDevice),                                 \
811     .vmsd       = &vmstate_pci_device,                               \
812     .flags      = VMS_STRUCT|VMS_POINTER,                            \
813     .offset     = vmstate_offset_pointer(_state, _field, PCIDevice), \
814 }
815 
816 MSIMessage pci_get_msi_message(PCIDevice *dev, int vector);
817 
818 #endif
819