1 #ifndef QEMU_PCI_H 2 #define QEMU_PCI_H 3 4 #include "hw/qdev.h" 5 #include "exec/memory.h" 6 #include "sysemu/dma.h" 7 8 /* PCI includes legacy ISA access. */ 9 #include "hw/isa/isa.h" 10 11 #include "hw/pci/pcie.h" 12 13 /* PCI bus */ 14 15 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 16 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 17 #define PCI_FUNC(devfn) ((devfn) & 0x07) 18 #define PCI_BUILD_BDF(bus, devfn) ((bus << 8) | (devfn)) 19 #define PCI_SLOT_MAX 32 20 #define PCI_FUNC_MAX 8 21 22 /* Class, Vendor and Device IDs from Linux's pci_ids.h */ 23 #include "hw/pci/pci_ids.h" 24 25 /* QEMU-specific Vendor and Device ID definitions */ 26 27 /* IBM (0x1014) */ 28 #define PCI_DEVICE_ID_IBM_440GX 0x027f 29 #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff 30 31 /* Hitachi (0x1054) */ 32 #define PCI_VENDOR_ID_HITACHI 0x1054 33 #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e 34 35 /* Apple (0x106b) */ 36 #define PCI_DEVICE_ID_APPLE_343S1201 0x0010 37 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e 38 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f 39 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022 40 #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f 41 42 /* Realtek (0x10ec) */ 43 #define PCI_DEVICE_ID_REALTEK_8029 0x8029 44 45 /* Xilinx (0x10ee) */ 46 #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300 47 48 /* Marvell (0x11ab) */ 49 #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620 50 51 /* QEMU/Bochs VGA (0x1234) */ 52 #define PCI_VENDOR_ID_QEMU 0x1234 53 #define PCI_DEVICE_ID_QEMU_VGA 0x1111 54 55 /* VMWare (0x15ad) */ 56 #define PCI_VENDOR_ID_VMWARE 0x15ad 57 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 58 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710 59 #define PCI_DEVICE_ID_VMWARE_NET 0x0720 60 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730 61 #define PCI_DEVICE_ID_VMWARE_PVSCSI 0x07C0 62 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729 63 #define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0 64 65 /* Intel (0x8086) */ 66 #define PCI_DEVICE_ID_INTEL_82551IT 0x1209 67 #define PCI_DEVICE_ID_INTEL_82557 0x1229 68 #define PCI_DEVICE_ID_INTEL_82801IR 0x2922 69 70 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */ 71 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 72 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 73 #define PCI_SUBDEVICE_ID_QEMU 0x1100 74 75 #define PCI_DEVICE_ID_VIRTIO_NET 0x1000 76 #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001 77 #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002 78 #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003 79 #define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004 80 #define PCI_DEVICE_ID_VIRTIO_RNG 0x1005 81 #define PCI_DEVICE_ID_VIRTIO_9P 0x1009 82 83 #define PCI_VENDOR_ID_REDHAT 0x1b36 84 #define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001 85 #define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002 86 #define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003 87 #define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004 88 #define PCI_DEVICE_ID_REDHAT_TEST 0x0005 89 #define PCI_DEVICE_ID_REDHAT_ROCKER 0x0006 90 #define PCI_DEVICE_ID_REDHAT_SDHCI 0x0007 91 #define PCI_DEVICE_ID_REDHAT_PCIE_HOST 0x0008 92 #define PCI_DEVICE_ID_REDHAT_PXB 0x0009 93 #define PCI_DEVICE_ID_REDHAT_BRIDGE_SEAT 0x000a 94 #define PCI_DEVICE_ID_REDHAT_PXB_PCIE 0x000b 95 #define PCI_DEVICE_ID_REDHAT_QXL 0x0100 96 97 #define FMT_PCIBUS PRIx64 98 99 typedef uint64_t pcibus_t; 100 101 struct PCIHostDeviceAddress { 102 unsigned int domain; 103 unsigned int bus; 104 unsigned int slot; 105 unsigned int function; 106 }; 107 108 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, 109 uint32_t address, uint32_t data, int len); 110 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev, 111 uint32_t address, int len); 112 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, 113 pcibus_t addr, pcibus_t size, int type); 114 typedef void PCIUnregisterFunc(PCIDevice *pci_dev); 115 116 typedef struct PCIIORegion { 117 pcibus_t addr; /* current PCI mapping address. -1 means not mapped */ 118 #define PCI_BAR_UNMAPPED (~(pcibus_t)0) 119 pcibus_t size; 120 uint8_t type; 121 MemoryRegion *memory; 122 MemoryRegion *address_space; 123 } PCIIORegion; 124 125 #define PCI_ROM_SLOT 6 126 #define PCI_NUM_REGIONS 7 127 128 enum { 129 QEMU_PCI_VGA_MEM, 130 QEMU_PCI_VGA_IO_LO, 131 QEMU_PCI_VGA_IO_HI, 132 QEMU_PCI_VGA_NUM_REGIONS, 133 }; 134 135 #define QEMU_PCI_VGA_MEM_BASE 0xa0000 136 #define QEMU_PCI_VGA_MEM_SIZE 0x20000 137 #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0 138 #define QEMU_PCI_VGA_IO_LO_SIZE 0xc 139 #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0 140 #define QEMU_PCI_VGA_IO_HI_SIZE 0x20 141 142 #include "hw/pci/pci_regs.h" 143 144 /* PCI HEADER_TYPE */ 145 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80 146 147 /* Size of the standard PCI config header */ 148 #define PCI_CONFIG_HEADER_SIZE 0x40 149 /* Size of the standard PCI config space */ 150 #define PCI_CONFIG_SPACE_SIZE 0x100 151 /* Size of the standard PCIe config space: 4KB */ 152 #define PCIE_CONFIG_SPACE_SIZE 0x1000 153 154 #define PCI_NUM_PINS 4 /* A-D */ 155 156 /* Bits in cap_present field. */ 157 enum { 158 QEMU_PCI_CAP_MSI = 0x1, 159 QEMU_PCI_CAP_MSIX = 0x2, 160 QEMU_PCI_CAP_EXPRESS = 0x4, 161 162 /* multifunction capable device */ 163 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3 164 QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR), 165 166 /* command register SERR bit enabled */ 167 #define QEMU_PCI_CAP_SERR_BITNR 4 168 QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR), 169 /* Standard hot plug controller. */ 170 #define QEMU_PCI_SHPC_BITNR 5 171 QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR), 172 #define QEMU_PCI_SLOTID_BITNR 6 173 QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR), 174 /* PCI Express capability - Power Controller Present */ 175 #define QEMU_PCIE_SLTCAP_PCP_BITNR 7 176 QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR), 177 /* Link active status in endpoint capability is always set */ 178 #define QEMU_PCIE_LNKSTA_DLLLA_BITNR 8 179 QEMU_PCIE_LNKSTA_DLLLA = (1 << QEMU_PCIE_LNKSTA_DLLLA_BITNR), 180 }; 181 182 #define TYPE_PCI_DEVICE "pci-device" 183 #define PCI_DEVICE(obj) \ 184 OBJECT_CHECK(PCIDevice, (obj), TYPE_PCI_DEVICE) 185 #define PCI_DEVICE_CLASS(klass) \ 186 OBJECT_CLASS_CHECK(PCIDeviceClass, (klass), TYPE_PCI_DEVICE) 187 #define PCI_DEVICE_GET_CLASS(obj) \ 188 OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE) 189 190 typedef struct PCIINTxRoute { 191 enum { 192 PCI_INTX_ENABLED, 193 PCI_INTX_INVERTED, 194 PCI_INTX_DISABLED, 195 } mode; 196 int irq; 197 } PCIINTxRoute; 198 199 typedef struct PCIDeviceClass { 200 DeviceClass parent_class; 201 202 void (*realize)(PCIDevice *dev, Error **errp); 203 int (*init)(PCIDevice *dev);/* TODO convert to realize() and remove */ 204 PCIUnregisterFunc *exit; 205 PCIConfigReadFunc *config_read; 206 PCIConfigWriteFunc *config_write; 207 208 uint16_t vendor_id; 209 uint16_t device_id; 210 uint8_t revision; 211 uint16_t class_id; 212 uint16_t subsystem_vendor_id; /* only for header type = 0 */ 213 uint16_t subsystem_id; /* only for header type = 0 */ 214 215 /* 216 * pci-to-pci bridge or normal device. 217 * This doesn't mean pci host switch. 218 * When card bus bridge is supported, this would be enhanced. 219 */ 220 int is_bridge; 221 222 /* pcie stuff */ 223 int is_express; /* is this device pci express? */ 224 225 /* rom bar */ 226 const char *romfile; 227 } PCIDeviceClass; 228 229 typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev); 230 typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector, 231 MSIMessage msg); 232 typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector); 233 typedef void (*MSIVectorPollNotifier)(PCIDevice *dev, 234 unsigned int vector_start, 235 unsigned int vector_end); 236 237 enum PCIReqIDType { 238 PCI_REQ_ID_INVALID = 0, 239 PCI_REQ_ID_BDF, 240 PCI_REQ_ID_SECONDARY_BUS, 241 PCI_REQ_ID_MAX, 242 }; 243 typedef enum PCIReqIDType PCIReqIDType; 244 245 struct PCIReqIDCache { 246 PCIDevice *dev; 247 PCIReqIDType type; 248 }; 249 typedef struct PCIReqIDCache PCIReqIDCache; 250 251 struct PCIDevice { 252 DeviceState qdev; 253 254 /* PCI config space */ 255 uint8_t *config; 256 257 /* Used to enable config checks on load. Note that writable bits are 258 * never checked even if set in cmask. */ 259 uint8_t *cmask; 260 261 /* Used to implement R/W bytes */ 262 uint8_t *wmask; 263 264 /* Used to implement RW1C(Write 1 to Clear) bytes */ 265 uint8_t *w1cmask; 266 267 /* Used to allocate config space for capabilities. */ 268 uint8_t *used; 269 270 /* the following fields are read only */ 271 PCIBus *bus; 272 int32_t devfn; 273 /* Cached device to fetch requester ID from, to avoid the PCI 274 * tree walking every time we invoke PCI request (e.g., 275 * MSI). For conventional PCI root complex, this field is 276 * meaningless. */ 277 PCIReqIDCache requester_id_cache; 278 char name[64]; 279 PCIIORegion io_regions[PCI_NUM_REGIONS]; 280 AddressSpace bus_master_as; 281 MemoryRegion bus_master_enable_region; 282 283 /* do not access the following fields */ 284 PCIConfigReadFunc *config_read; 285 PCIConfigWriteFunc *config_write; 286 287 /* Legacy PCI VGA regions */ 288 MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS]; 289 bool has_vga; 290 291 /* Current IRQ levels. Used internally by the generic PCI code. */ 292 uint8_t irq_state; 293 294 /* Capability bits */ 295 uint32_t cap_present; 296 297 /* Offset of MSI-X capability in config space */ 298 uint8_t msix_cap; 299 300 /* MSI-X entries */ 301 int msix_entries_nr; 302 303 /* Space to store MSIX table & pending bit array */ 304 uint8_t *msix_table; 305 uint8_t *msix_pba; 306 /* MemoryRegion container for msix exclusive BAR setup */ 307 MemoryRegion msix_exclusive_bar; 308 /* Memory Regions for MSIX table and pending bit entries. */ 309 MemoryRegion msix_table_mmio; 310 MemoryRegion msix_pba_mmio; 311 /* Reference-count for entries actually in use by driver. */ 312 unsigned *msix_entry_used; 313 /* MSIX function mask set or MSIX disabled */ 314 bool msix_function_masked; 315 /* Version id needed for VMState */ 316 int32_t version_id; 317 318 /* Offset of MSI capability in config space */ 319 uint8_t msi_cap; 320 321 /* PCI Express */ 322 PCIExpressDevice exp; 323 324 /* SHPC */ 325 SHPCDevice *shpc; 326 327 /* Location of option rom */ 328 char *romfile; 329 bool has_rom; 330 MemoryRegion rom; 331 uint32_t rom_bar; 332 333 /* INTx routing notifier */ 334 PCIINTxRoutingNotifier intx_routing_notifier; 335 336 /* MSI-X notifiers */ 337 MSIVectorUseNotifier msix_vector_use_notifier; 338 MSIVectorReleaseNotifier msix_vector_release_notifier; 339 MSIVectorPollNotifier msix_vector_poll_notifier; 340 }; 341 342 void pci_register_bar(PCIDevice *pci_dev, int region_num, 343 uint8_t attr, MemoryRegion *memory); 344 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, 345 MemoryRegion *io_lo, MemoryRegion *io_hi); 346 void pci_unregister_vga(PCIDevice *pci_dev); 347 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num); 348 349 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, 350 uint8_t offset, uint8_t size); 351 int pci_add_capability2(PCIDevice *pdev, uint8_t cap_id, 352 uint8_t offset, uint8_t size, 353 Error **errp); 354 355 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size); 356 357 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id); 358 359 360 uint32_t pci_default_read_config(PCIDevice *d, 361 uint32_t address, int len); 362 void pci_default_write_config(PCIDevice *d, 363 uint32_t address, uint32_t val, int len); 364 void pci_device_save(PCIDevice *s, QEMUFile *f); 365 int pci_device_load(PCIDevice *s, QEMUFile *f); 366 MemoryRegion *pci_address_space(PCIDevice *dev); 367 MemoryRegion *pci_address_space_io(PCIDevice *dev); 368 369 /* 370 * Should not normally be used by devices. For use by sPAPR target 371 * where QEMU emulates firmware. 372 */ 373 int pci_bar(PCIDevice *d, int reg); 374 375 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level); 376 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); 377 typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin); 378 379 #define TYPE_PCI_BUS "PCI" 380 #define PCI_BUS(obj) OBJECT_CHECK(PCIBus, (obj), TYPE_PCI_BUS) 381 #define PCI_BUS_CLASS(klass) OBJECT_CLASS_CHECK(PCIBusClass, (klass), TYPE_PCI_BUS) 382 #define PCI_BUS_GET_CLASS(obj) OBJECT_GET_CLASS(PCIBusClass, (obj), TYPE_PCI_BUS) 383 #define TYPE_PCIE_BUS "PCIE" 384 385 bool pci_bus_is_express(PCIBus *bus); 386 bool pci_bus_is_root(PCIBus *bus); 387 void pci_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent, 388 const char *name, 389 MemoryRegion *address_space_mem, 390 MemoryRegion *address_space_io, 391 uint8_t devfn_min, const char *typename); 392 PCIBus *pci_bus_new(DeviceState *parent, const char *name, 393 MemoryRegion *address_space_mem, 394 MemoryRegion *address_space_io, 395 uint8_t devfn_min, const char *typename); 396 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 397 void *irq_opaque, int nirq); 398 int pci_bus_get_irq_level(PCIBus *bus, int irq_num); 399 /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */ 400 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin); 401 PCIBus *pci_register_bus(DeviceState *parent, const char *name, 402 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 403 void *irq_opaque, 404 MemoryRegion *address_space_mem, 405 MemoryRegion *address_space_io, 406 uint8_t devfn_min, int nirq, const char *typename); 407 void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn); 408 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin); 409 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new); 410 void pci_bus_fire_intx_routing_notifier(PCIBus *bus); 411 void pci_device_set_intx_routing_notifier(PCIDevice *dev, 412 PCIINTxRoutingNotifier notifier); 413 void pci_device_reset(PCIDevice *dev); 414 415 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus, 416 const char *default_model, 417 const char *default_devaddr); 418 419 PCIDevice *pci_vga_init(PCIBus *bus); 420 421 int pci_bus_num(PCIBus *s); 422 int pci_bus_numa_node(PCIBus *bus); 423 void pci_for_each_device(PCIBus *bus, int bus_num, 424 void (*fn)(PCIBus *bus, PCIDevice *d, void *opaque), 425 void *opaque); 426 void pci_for_each_bus_depth_first(PCIBus *bus, 427 void *(*begin)(PCIBus *bus, void *parent_state), 428 void (*end)(PCIBus *bus, void *state), 429 void *parent_state); 430 PCIDevice *pci_get_function_0(PCIDevice *pci_dev); 431 432 /* Use this wrapper when specific scan order is not required. */ 433 static inline 434 void pci_for_each_bus(PCIBus *bus, 435 void (*fn)(PCIBus *bus, void *opaque), 436 void *opaque) 437 { 438 pci_for_each_bus_depth_first(bus, NULL, fn, opaque); 439 } 440 441 PCIBus *pci_find_primary_bus(void); 442 PCIBus *pci_device_root_bus(const PCIDevice *d); 443 const char *pci_root_bus_path(PCIDevice *dev); 444 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn); 445 int pci_qdev_find_device(const char *id, PCIDevice **pdev); 446 void pci_bus_get_w64_range(PCIBus *bus, Range *range); 447 448 void pci_device_deassert_intx(PCIDevice *dev); 449 450 typedef AddressSpace *(*PCIIOMMUFunc)(PCIBus *, void *, int); 451 452 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev); 453 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque); 454 455 static inline void 456 pci_set_byte(uint8_t *config, uint8_t val) 457 { 458 *config = val; 459 } 460 461 static inline uint8_t 462 pci_get_byte(const uint8_t *config) 463 { 464 return *config; 465 } 466 467 static inline void 468 pci_set_word(uint8_t *config, uint16_t val) 469 { 470 stw_le_p(config, val); 471 } 472 473 static inline uint16_t 474 pci_get_word(const uint8_t *config) 475 { 476 return lduw_le_p(config); 477 } 478 479 static inline void 480 pci_set_long(uint8_t *config, uint32_t val) 481 { 482 stl_le_p(config, val); 483 } 484 485 static inline uint32_t 486 pci_get_long(const uint8_t *config) 487 { 488 return ldl_le_p(config); 489 } 490 491 /* 492 * PCI capabilities and/or their fields 493 * are generally DWORD aligned only so 494 * mechanism used by pci_set/get_quad() 495 * must be tolerant to unaligned pointers 496 * 497 */ 498 static inline void 499 pci_set_quad(uint8_t *config, uint64_t val) 500 { 501 stq_le_p(config, val); 502 } 503 504 static inline uint64_t 505 pci_get_quad(const uint8_t *config) 506 { 507 return ldq_le_p(config); 508 } 509 510 static inline void 511 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val) 512 { 513 pci_set_word(&pci_config[PCI_VENDOR_ID], val); 514 } 515 516 static inline void 517 pci_config_set_device_id(uint8_t *pci_config, uint16_t val) 518 { 519 pci_set_word(&pci_config[PCI_DEVICE_ID], val); 520 } 521 522 static inline void 523 pci_config_set_revision(uint8_t *pci_config, uint8_t val) 524 { 525 pci_set_byte(&pci_config[PCI_REVISION_ID], val); 526 } 527 528 static inline void 529 pci_config_set_class(uint8_t *pci_config, uint16_t val) 530 { 531 pci_set_word(&pci_config[PCI_CLASS_DEVICE], val); 532 } 533 534 static inline void 535 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val) 536 { 537 pci_set_byte(&pci_config[PCI_CLASS_PROG], val); 538 } 539 540 static inline void 541 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val) 542 { 543 pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val); 544 } 545 546 /* 547 * helper functions to do bit mask operation on configuration space. 548 * Just to set bit, use test-and-set and discard returned value. 549 * Just to clear bit, use test-and-clear and discard returned value. 550 * NOTE: They aren't atomic. 551 */ 552 static inline uint8_t 553 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask) 554 { 555 uint8_t val = pci_get_byte(config); 556 pci_set_byte(config, val & ~mask); 557 return val & mask; 558 } 559 560 static inline uint8_t 561 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask) 562 { 563 uint8_t val = pci_get_byte(config); 564 pci_set_byte(config, val | mask); 565 return val & mask; 566 } 567 568 static inline uint16_t 569 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask) 570 { 571 uint16_t val = pci_get_word(config); 572 pci_set_word(config, val & ~mask); 573 return val & mask; 574 } 575 576 static inline uint16_t 577 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask) 578 { 579 uint16_t val = pci_get_word(config); 580 pci_set_word(config, val | mask); 581 return val & mask; 582 } 583 584 static inline uint32_t 585 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask) 586 { 587 uint32_t val = pci_get_long(config); 588 pci_set_long(config, val & ~mask); 589 return val & mask; 590 } 591 592 static inline uint32_t 593 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask) 594 { 595 uint32_t val = pci_get_long(config); 596 pci_set_long(config, val | mask); 597 return val & mask; 598 } 599 600 static inline uint64_t 601 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask) 602 { 603 uint64_t val = pci_get_quad(config); 604 pci_set_quad(config, val & ~mask); 605 return val & mask; 606 } 607 608 static inline uint64_t 609 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask) 610 { 611 uint64_t val = pci_get_quad(config); 612 pci_set_quad(config, val | mask); 613 return val & mask; 614 } 615 616 /* Access a register specified by a mask */ 617 static inline void 618 pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg) 619 { 620 uint8_t val = pci_get_byte(config); 621 uint8_t rval = reg << ctz32(mask); 622 pci_set_byte(config, (~mask & val) | (mask & rval)); 623 } 624 625 static inline uint8_t 626 pci_get_byte_by_mask(uint8_t *config, uint8_t mask) 627 { 628 uint8_t val = pci_get_byte(config); 629 return (val & mask) >> ctz32(mask); 630 } 631 632 static inline void 633 pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg) 634 { 635 uint16_t val = pci_get_word(config); 636 uint16_t rval = reg << ctz32(mask); 637 pci_set_word(config, (~mask & val) | (mask & rval)); 638 } 639 640 static inline uint16_t 641 pci_get_word_by_mask(uint8_t *config, uint16_t mask) 642 { 643 uint16_t val = pci_get_word(config); 644 return (val & mask) >> ctz32(mask); 645 } 646 647 static inline void 648 pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg) 649 { 650 uint32_t val = pci_get_long(config); 651 uint32_t rval = reg << ctz32(mask); 652 pci_set_long(config, (~mask & val) | (mask & rval)); 653 } 654 655 static inline uint32_t 656 pci_get_long_by_mask(uint8_t *config, uint32_t mask) 657 { 658 uint32_t val = pci_get_long(config); 659 return (val & mask) >> ctz32(mask); 660 } 661 662 static inline void 663 pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg) 664 { 665 uint64_t val = pci_get_quad(config); 666 uint64_t rval = reg << ctz32(mask); 667 pci_set_quad(config, (~mask & val) | (mask & rval)); 668 } 669 670 static inline uint64_t 671 pci_get_quad_by_mask(uint8_t *config, uint64_t mask) 672 { 673 uint64_t val = pci_get_quad(config); 674 return (val & mask) >> ctz32(mask); 675 } 676 677 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction, 678 const char *name); 679 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, 680 bool multifunction, 681 const char *name); 682 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name); 683 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name); 684 685 qemu_irq pci_allocate_irq(PCIDevice *pci_dev); 686 void pci_set_irq(PCIDevice *pci_dev, int level); 687 688 static inline void pci_irq_assert(PCIDevice *pci_dev) 689 { 690 pci_set_irq(pci_dev, 1); 691 } 692 693 static inline void pci_irq_deassert(PCIDevice *pci_dev) 694 { 695 pci_set_irq(pci_dev, 0); 696 } 697 698 /* 699 * FIXME: PCI does not work this way. 700 * All the callers to this method should be fixed. 701 */ 702 static inline void pci_irq_pulse(PCIDevice *pci_dev) 703 { 704 pci_irq_assert(pci_dev); 705 pci_irq_deassert(pci_dev); 706 } 707 708 static inline int pci_is_express(const PCIDevice *d) 709 { 710 return d->cap_present & QEMU_PCI_CAP_EXPRESS; 711 } 712 713 static inline uint32_t pci_config_size(const PCIDevice *d) 714 { 715 return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE; 716 } 717 718 static inline uint16_t pci_get_bdf(PCIDevice *dev) 719 { 720 return PCI_BUILD_BDF(pci_bus_num(dev->bus), dev->devfn); 721 } 722 723 uint16_t pci_requester_id(PCIDevice *dev); 724 725 /* DMA access functions */ 726 static inline AddressSpace *pci_get_address_space(PCIDevice *dev) 727 { 728 return &dev->bus_master_as; 729 } 730 731 static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr, 732 void *buf, dma_addr_t len, DMADirection dir) 733 { 734 dma_memory_rw(pci_get_address_space(dev), addr, buf, len, dir); 735 return 0; 736 } 737 738 static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr, 739 void *buf, dma_addr_t len) 740 { 741 return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE); 742 } 743 744 static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr, 745 const void *buf, dma_addr_t len) 746 { 747 return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE); 748 } 749 750 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \ 751 static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev, \ 752 dma_addr_t addr) \ 753 { \ 754 return ld##_l##_dma(pci_get_address_space(dev), addr); \ 755 } \ 756 static inline void st##_s##_pci_dma(PCIDevice *dev, \ 757 dma_addr_t addr, uint##_bits##_t val) \ 758 { \ 759 st##_s##_dma(pci_get_address_space(dev), addr, val); \ 760 } 761 762 PCI_DMA_DEFINE_LDST(ub, b, 8); 763 PCI_DMA_DEFINE_LDST(uw_le, w_le, 16) 764 PCI_DMA_DEFINE_LDST(l_le, l_le, 32); 765 PCI_DMA_DEFINE_LDST(q_le, q_le, 64); 766 PCI_DMA_DEFINE_LDST(uw_be, w_be, 16) 767 PCI_DMA_DEFINE_LDST(l_be, l_be, 32); 768 PCI_DMA_DEFINE_LDST(q_be, q_be, 64); 769 770 #undef PCI_DMA_DEFINE_LDST 771 772 static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr, 773 dma_addr_t *plen, DMADirection dir) 774 { 775 void *buf; 776 777 buf = dma_memory_map(pci_get_address_space(dev), addr, plen, dir); 778 return buf; 779 } 780 781 static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len, 782 DMADirection dir, dma_addr_t access_len) 783 { 784 dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len); 785 } 786 787 static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev, 788 int alloc_hint) 789 { 790 qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev)); 791 } 792 793 extern const VMStateDescription vmstate_pci_device; 794 795 #define VMSTATE_PCI_DEVICE(_field, _state) { \ 796 .name = (stringify(_field)), \ 797 .size = sizeof(PCIDevice), \ 798 .vmsd = &vmstate_pci_device, \ 799 .flags = VMS_STRUCT, \ 800 .offset = vmstate_offset_value(_state, _field, PCIDevice), \ 801 } 802 803 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \ 804 .name = (stringify(_field)), \ 805 .size = sizeof(PCIDevice), \ 806 .vmsd = &vmstate_pci_device, \ 807 .flags = VMS_STRUCT|VMS_POINTER, \ 808 .offset = vmstate_offset_pointer(_state, _field, PCIDevice), \ 809 } 810 811 MSIMessage pci_get_msi_message(PCIDevice *dev, int vector); 812 813 #endif 814