1 #ifndef QEMU_PCI_H 2 #define QEMU_PCI_H 3 4 #include "qemu-common.h" 5 6 #include "hw/qdev.h" 7 #include "exec/memory.h" 8 #include "sysemu/dma.h" 9 #include "qapi/error.h" 10 11 /* PCI includes legacy ISA access. */ 12 #include "hw/isa/isa.h" 13 14 #include "hw/pci/pcie.h" 15 16 /* PCI bus */ 17 18 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 19 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 20 #define PCI_FUNC(devfn) ((devfn) & 0x07) 21 #define PCI_SLOT_MAX 32 22 #define PCI_FUNC_MAX 8 23 24 /* Class, Vendor and Device IDs from Linux's pci_ids.h */ 25 #include "hw/pci/pci_ids.h" 26 27 /* QEMU-specific Vendor and Device ID definitions */ 28 29 /* IBM (0x1014) */ 30 #define PCI_DEVICE_ID_IBM_440GX 0x027f 31 #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff 32 33 /* Hitachi (0x1054) */ 34 #define PCI_VENDOR_ID_HITACHI 0x1054 35 #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e 36 37 /* Apple (0x106b) */ 38 #define PCI_DEVICE_ID_APPLE_343S1201 0x0010 39 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e 40 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f 41 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022 42 #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f 43 44 /* Realtek (0x10ec) */ 45 #define PCI_DEVICE_ID_REALTEK_8029 0x8029 46 47 /* Xilinx (0x10ee) */ 48 #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300 49 50 /* Marvell (0x11ab) */ 51 #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620 52 53 /* QEMU/Bochs VGA (0x1234) */ 54 #define PCI_VENDOR_ID_QEMU 0x1234 55 #define PCI_DEVICE_ID_QEMU_VGA 0x1111 56 57 /* VMWare (0x15ad) */ 58 #define PCI_VENDOR_ID_VMWARE 0x15ad 59 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 60 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710 61 #define PCI_DEVICE_ID_VMWARE_NET 0x0720 62 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730 63 #define PCI_DEVICE_ID_VMWARE_PVSCSI 0x07C0 64 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729 65 #define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0 66 67 /* Intel (0x8086) */ 68 #define PCI_DEVICE_ID_INTEL_82551IT 0x1209 69 #define PCI_DEVICE_ID_INTEL_82557 0x1229 70 #define PCI_DEVICE_ID_INTEL_82801IR 0x2922 71 72 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */ 73 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 74 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 75 #define PCI_SUBDEVICE_ID_QEMU 0x1100 76 77 #define PCI_DEVICE_ID_VIRTIO_NET 0x1000 78 #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001 79 #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002 80 #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003 81 #define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004 82 #define PCI_DEVICE_ID_VIRTIO_RNG 0x1005 83 #define PCI_DEVICE_ID_VIRTIO_9P 0x1009 84 85 #define PCI_VENDOR_ID_REDHAT 0x1b36 86 #define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001 87 #define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002 88 #define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003 89 #define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004 90 #define PCI_DEVICE_ID_REDHAT_TEST 0x0005 91 #define PCI_DEVICE_ID_REDHAT_ROCKER 0x0006 92 #define PCI_DEVICE_ID_REDHAT_SDHCI 0x0007 93 #define PCI_DEVICE_ID_REDHAT_PCIE_HOST 0x0008 94 #define PCI_DEVICE_ID_REDHAT_QXL 0x0100 95 96 #define FMT_PCIBUS PRIx64 97 98 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, 99 uint32_t address, uint32_t data, int len); 100 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev, 101 uint32_t address, int len); 102 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, 103 pcibus_t addr, pcibus_t size, int type); 104 typedef void PCIUnregisterFunc(PCIDevice *pci_dev); 105 106 typedef struct PCIIORegion { 107 pcibus_t addr; /* current PCI mapping address. -1 means not mapped */ 108 #define PCI_BAR_UNMAPPED (~(pcibus_t)0) 109 pcibus_t size; 110 uint8_t type; 111 MemoryRegion *memory; 112 MemoryRegion *address_space; 113 } PCIIORegion; 114 115 #define PCI_ROM_SLOT 6 116 #define PCI_NUM_REGIONS 7 117 118 enum { 119 QEMU_PCI_VGA_MEM, 120 QEMU_PCI_VGA_IO_LO, 121 QEMU_PCI_VGA_IO_HI, 122 QEMU_PCI_VGA_NUM_REGIONS, 123 }; 124 125 #define QEMU_PCI_VGA_MEM_BASE 0xa0000 126 #define QEMU_PCI_VGA_MEM_SIZE 0x20000 127 #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0 128 #define QEMU_PCI_VGA_IO_LO_SIZE 0xc 129 #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0 130 #define QEMU_PCI_VGA_IO_HI_SIZE 0x20 131 132 #include "hw/pci/pci_regs.h" 133 134 /* PCI HEADER_TYPE */ 135 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80 136 137 /* Size of the standard PCI config header */ 138 #define PCI_CONFIG_HEADER_SIZE 0x40 139 /* Size of the standard PCI config space */ 140 #define PCI_CONFIG_SPACE_SIZE 0x100 141 /* Size of the standard PCIe config space: 4KB */ 142 #define PCIE_CONFIG_SPACE_SIZE 0x1000 143 144 #define PCI_NUM_PINS 4 /* A-D */ 145 146 /* Bits in cap_present field. */ 147 enum { 148 QEMU_PCI_CAP_MSI = 0x1, 149 QEMU_PCI_CAP_MSIX = 0x2, 150 QEMU_PCI_CAP_EXPRESS = 0x4, 151 152 /* multifunction capable device */ 153 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3 154 QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR), 155 156 /* command register SERR bit enabled */ 157 #define QEMU_PCI_CAP_SERR_BITNR 4 158 QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR), 159 /* Standard hot plug controller. */ 160 #define QEMU_PCI_SHPC_BITNR 5 161 QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR), 162 #define QEMU_PCI_SLOTID_BITNR 6 163 QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR), 164 /* PCI Express capability - Power Controller Present */ 165 #define QEMU_PCIE_SLTCAP_PCP_BITNR 7 166 QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR), 167 }; 168 169 #define TYPE_PCI_DEVICE "pci-device" 170 #define PCI_DEVICE(obj) \ 171 OBJECT_CHECK(PCIDevice, (obj), TYPE_PCI_DEVICE) 172 #define PCI_DEVICE_CLASS(klass) \ 173 OBJECT_CLASS_CHECK(PCIDeviceClass, (klass), TYPE_PCI_DEVICE) 174 #define PCI_DEVICE_GET_CLASS(obj) \ 175 OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE) 176 177 typedef struct PCIINTxRoute { 178 enum { 179 PCI_INTX_ENABLED, 180 PCI_INTX_INVERTED, 181 PCI_INTX_DISABLED, 182 } mode; 183 int irq; 184 } PCIINTxRoute; 185 186 typedef struct PCIDeviceClass { 187 DeviceClass parent_class; 188 189 void (*realize)(PCIDevice *dev, Error **errp); 190 int (*init)(PCIDevice *dev);/* TODO convert to realize() and remove */ 191 PCIUnregisterFunc *exit; 192 PCIConfigReadFunc *config_read; 193 PCIConfigWriteFunc *config_write; 194 195 uint16_t vendor_id; 196 uint16_t device_id; 197 uint8_t revision; 198 uint16_t class_id; 199 uint16_t subsystem_vendor_id; /* only for header type = 0 */ 200 uint16_t subsystem_id; /* only for header type = 0 */ 201 202 /* 203 * pci-to-pci bridge or normal device. 204 * This doesn't mean pci host switch. 205 * When card bus bridge is supported, this would be enhanced. 206 */ 207 int is_bridge; 208 209 /* pcie stuff */ 210 int is_express; /* is this device pci express? */ 211 212 /* rom bar */ 213 const char *romfile; 214 } PCIDeviceClass; 215 216 typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev); 217 typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector, 218 MSIMessage msg); 219 typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector); 220 typedef void (*MSIVectorPollNotifier)(PCIDevice *dev, 221 unsigned int vector_start, 222 unsigned int vector_end); 223 224 struct PCIDevice { 225 DeviceState qdev; 226 227 /* PCI config space */ 228 uint8_t *config; 229 230 /* Used to enable config checks on load. Note that writable bits are 231 * never checked even if set in cmask. */ 232 uint8_t *cmask; 233 234 /* Used to implement R/W bytes */ 235 uint8_t *wmask; 236 237 /* Used to implement RW1C(Write 1 to Clear) bytes */ 238 uint8_t *w1cmask; 239 240 /* Used to allocate config space for capabilities. */ 241 uint8_t *used; 242 243 /* the following fields are read only */ 244 PCIBus *bus; 245 int32_t devfn; 246 char name[64]; 247 PCIIORegion io_regions[PCI_NUM_REGIONS]; 248 AddressSpace bus_master_as; 249 MemoryRegion bus_master_enable_region; 250 251 /* do not access the following fields */ 252 PCIConfigReadFunc *config_read; 253 PCIConfigWriteFunc *config_write; 254 255 /* Legacy PCI VGA regions */ 256 MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS]; 257 bool has_vga; 258 259 /* Current IRQ levels. Used internally by the generic PCI code. */ 260 uint8_t irq_state; 261 262 /* Capability bits */ 263 uint32_t cap_present; 264 265 /* Offset of MSI-X capability in config space */ 266 uint8_t msix_cap; 267 268 /* MSI-X entries */ 269 int msix_entries_nr; 270 271 /* Space to store MSIX table & pending bit array */ 272 uint8_t *msix_table; 273 uint8_t *msix_pba; 274 /* MemoryRegion container for msix exclusive BAR setup */ 275 MemoryRegion msix_exclusive_bar; 276 /* Memory Regions for MSIX table and pending bit entries. */ 277 MemoryRegion msix_table_mmio; 278 MemoryRegion msix_pba_mmio; 279 /* Reference-count for entries actually in use by driver. */ 280 unsigned *msix_entry_used; 281 /* MSIX function mask set or MSIX disabled */ 282 bool msix_function_masked; 283 /* Version id needed for VMState */ 284 int32_t version_id; 285 286 /* Offset of MSI capability in config space */ 287 uint8_t msi_cap; 288 289 /* PCI Express */ 290 PCIExpressDevice exp; 291 292 /* SHPC */ 293 SHPCDevice *shpc; 294 295 /* Location of option rom */ 296 char *romfile; 297 bool has_rom; 298 MemoryRegion rom; 299 uint32_t rom_bar; 300 301 /* INTx routing notifier */ 302 PCIINTxRoutingNotifier intx_routing_notifier; 303 304 /* MSI-X notifiers */ 305 MSIVectorUseNotifier msix_vector_use_notifier; 306 MSIVectorReleaseNotifier msix_vector_release_notifier; 307 MSIVectorPollNotifier msix_vector_poll_notifier; 308 }; 309 310 void pci_register_bar(PCIDevice *pci_dev, int region_num, 311 uint8_t attr, MemoryRegion *memory); 312 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, 313 MemoryRegion *io_lo, MemoryRegion *io_hi); 314 void pci_unregister_vga(PCIDevice *pci_dev); 315 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num); 316 317 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, 318 uint8_t offset, uint8_t size); 319 int pci_add_capability2(PCIDevice *pdev, uint8_t cap_id, 320 uint8_t offset, uint8_t size, 321 Error **errp); 322 323 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size); 324 325 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id); 326 327 328 uint32_t pci_default_read_config(PCIDevice *d, 329 uint32_t address, int len); 330 void pci_default_write_config(PCIDevice *d, 331 uint32_t address, uint32_t val, int len); 332 void pci_device_save(PCIDevice *s, QEMUFile *f); 333 int pci_device_load(PCIDevice *s, QEMUFile *f); 334 MemoryRegion *pci_address_space(PCIDevice *dev); 335 MemoryRegion *pci_address_space_io(PCIDevice *dev); 336 337 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level); 338 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); 339 typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin); 340 341 #define TYPE_PCI_BUS "PCI" 342 #define PCI_BUS(obj) OBJECT_CHECK(PCIBus, (obj), TYPE_PCI_BUS) 343 #define TYPE_PCIE_BUS "PCIE" 344 345 bool pci_bus_is_express(PCIBus *bus); 346 bool pci_bus_is_root(PCIBus *bus); 347 void pci_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent, 348 const char *name, 349 MemoryRegion *address_space_mem, 350 MemoryRegion *address_space_io, 351 uint8_t devfn_min, const char *typename); 352 PCIBus *pci_bus_new(DeviceState *parent, const char *name, 353 MemoryRegion *address_space_mem, 354 MemoryRegion *address_space_io, 355 uint8_t devfn_min, const char *typename); 356 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 357 void *irq_opaque, int nirq); 358 int pci_bus_get_irq_level(PCIBus *bus, int irq_num); 359 /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */ 360 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin); 361 PCIBus *pci_register_bus(DeviceState *parent, const char *name, 362 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 363 void *irq_opaque, 364 MemoryRegion *address_space_mem, 365 MemoryRegion *address_space_io, 366 uint8_t devfn_min, int nirq, const char *typename); 367 void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn); 368 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin); 369 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new); 370 void pci_bus_fire_intx_routing_notifier(PCIBus *bus); 371 void pci_device_set_intx_routing_notifier(PCIDevice *dev, 372 PCIINTxRoutingNotifier notifier); 373 void pci_device_reset(PCIDevice *dev); 374 375 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus, 376 const char *default_model, 377 const char *default_devaddr); 378 379 PCIDevice *pci_vga_init(PCIBus *bus); 380 381 int pci_bus_num(PCIBus *s); 382 void pci_for_each_device(PCIBus *bus, int bus_num, 383 void (*fn)(PCIBus *bus, PCIDevice *d, void *opaque), 384 void *opaque); 385 void pci_for_each_bus_depth_first(PCIBus *bus, 386 void *(*begin)(PCIBus *bus, void *parent_state), 387 void (*end)(PCIBus *bus, void *state), 388 void *parent_state); 389 390 /* Use this wrapper when specific scan order is not required. */ 391 static inline 392 void pci_for_each_bus(PCIBus *bus, 393 void (*fn)(PCIBus *bus, void *opaque), 394 void *opaque) 395 { 396 pci_for_each_bus_depth_first(bus, NULL, fn, opaque); 397 } 398 399 PCIBus *pci_find_primary_bus(void); 400 PCIBus *pci_device_root_bus(const PCIDevice *d); 401 const char *pci_root_bus_path(PCIDevice *dev); 402 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn); 403 int pci_qdev_find_device(const char *id, PCIDevice **pdev); 404 void pci_bus_get_w64_range(PCIBus *bus, Range *range); 405 406 void pci_device_deassert_intx(PCIDevice *dev); 407 408 typedef AddressSpace *(*PCIIOMMUFunc)(PCIBus *, void *, int); 409 410 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev); 411 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque); 412 413 static inline void 414 pci_set_byte(uint8_t *config, uint8_t val) 415 { 416 *config = val; 417 } 418 419 static inline uint8_t 420 pci_get_byte(const uint8_t *config) 421 { 422 return *config; 423 } 424 425 static inline void 426 pci_set_word(uint8_t *config, uint16_t val) 427 { 428 stw_le_p(config, val); 429 } 430 431 static inline uint16_t 432 pci_get_word(const uint8_t *config) 433 { 434 return lduw_le_p(config); 435 } 436 437 static inline void 438 pci_set_long(uint8_t *config, uint32_t val) 439 { 440 stl_le_p(config, val); 441 } 442 443 static inline uint32_t 444 pci_get_long(const uint8_t *config) 445 { 446 return ldl_le_p(config); 447 } 448 449 static inline void 450 pci_set_quad(uint8_t *config, uint64_t val) 451 { 452 cpu_to_le64w((uint64_t *)config, val); 453 } 454 455 static inline uint64_t 456 pci_get_quad(const uint8_t *config) 457 { 458 return le64_to_cpup((const uint64_t *)config); 459 } 460 461 static inline void 462 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val) 463 { 464 pci_set_word(&pci_config[PCI_VENDOR_ID], val); 465 } 466 467 static inline void 468 pci_config_set_device_id(uint8_t *pci_config, uint16_t val) 469 { 470 pci_set_word(&pci_config[PCI_DEVICE_ID], val); 471 } 472 473 static inline void 474 pci_config_set_revision(uint8_t *pci_config, uint8_t val) 475 { 476 pci_set_byte(&pci_config[PCI_REVISION_ID], val); 477 } 478 479 static inline void 480 pci_config_set_class(uint8_t *pci_config, uint16_t val) 481 { 482 pci_set_word(&pci_config[PCI_CLASS_DEVICE], val); 483 } 484 485 static inline void 486 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val) 487 { 488 pci_set_byte(&pci_config[PCI_CLASS_PROG], val); 489 } 490 491 static inline void 492 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val) 493 { 494 pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val); 495 } 496 497 /* 498 * helper functions to do bit mask operation on configuration space. 499 * Just to set bit, use test-and-set and discard returned value. 500 * Just to clear bit, use test-and-clear and discard returned value. 501 * NOTE: They aren't atomic. 502 */ 503 static inline uint8_t 504 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask) 505 { 506 uint8_t val = pci_get_byte(config); 507 pci_set_byte(config, val & ~mask); 508 return val & mask; 509 } 510 511 static inline uint8_t 512 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask) 513 { 514 uint8_t val = pci_get_byte(config); 515 pci_set_byte(config, val | mask); 516 return val & mask; 517 } 518 519 static inline uint16_t 520 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask) 521 { 522 uint16_t val = pci_get_word(config); 523 pci_set_word(config, val & ~mask); 524 return val & mask; 525 } 526 527 static inline uint16_t 528 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask) 529 { 530 uint16_t val = pci_get_word(config); 531 pci_set_word(config, val | mask); 532 return val & mask; 533 } 534 535 static inline uint32_t 536 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask) 537 { 538 uint32_t val = pci_get_long(config); 539 pci_set_long(config, val & ~mask); 540 return val & mask; 541 } 542 543 static inline uint32_t 544 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask) 545 { 546 uint32_t val = pci_get_long(config); 547 pci_set_long(config, val | mask); 548 return val & mask; 549 } 550 551 static inline uint64_t 552 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask) 553 { 554 uint64_t val = pci_get_quad(config); 555 pci_set_quad(config, val & ~mask); 556 return val & mask; 557 } 558 559 static inline uint64_t 560 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask) 561 { 562 uint64_t val = pci_get_quad(config); 563 pci_set_quad(config, val | mask); 564 return val & mask; 565 } 566 567 /* Access a register specified by a mask */ 568 static inline void 569 pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg) 570 { 571 uint8_t val = pci_get_byte(config); 572 uint8_t rval = reg << ctz32(mask); 573 pci_set_byte(config, (~mask & val) | (mask & rval)); 574 } 575 576 static inline uint8_t 577 pci_get_byte_by_mask(uint8_t *config, uint8_t mask) 578 { 579 uint8_t val = pci_get_byte(config); 580 return (val & mask) >> ctz32(mask); 581 } 582 583 static inline void 584 pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg) 585 { 586 uint16_t val = pci_get_word(config); 587 uint16_t rval = reg << ctz32(mask); 588 pci_set_word(config, (~mask & val) | (mask & rval)); 589 } 590 591 static inline uint16_t 592 pci_get_word_by_mask(uint8_t *config, uint16_t mask) 593 { 594 uint16_t val = pci_get_word(config); 595 return (val & mask) >> ctz32(mask); 596 } 597 598 static inline void 599 pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg) 600 { 601 uint32_t val = pci_get_long(config); 602 uint32_t rval = reg << ctz32(mask); 603 pci_set_long(config, (~mask & val) | (mask & rval)); 604 } 605 606 static inline uint32_t 607 pci_get_long_by_mask(uint8_t *config, uint32_t mask) 608 { 609 uint32_t val = pci_get_long(config); 610 return (val & mask) >> ctz32(mask); 611 } 612 613 static inline void 614 pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg) 615 { 616 uint64_t val = pci_get_quad(config); 617 uint64_t rval = reg << ctz32(mask); 618 pci_set_quad(config, (~mask & val) | (mask & rval)); 619 } 620 621 static inline uint64_t 622 pci_get_quad_by_mask(uint8_t *config, uint64_t mask) 623 { 624 uint64_t val = pci_get_quad(config); 625 return (val & mask) >> ctz32(mask); 626 } 627 628 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction, 629 const char *name); 630 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, 631 bool multifunction, 632 const char *name); 633 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name); 634 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name); 635 636 qemu_irq pci_allocate_irq(PCIDevice *pci_dev); 637 void pci_set_irq(PCIDevice *pci_dev, int level); 638 639 static inline void pci_irq_assert(PCIDevice *pci_dev) 640 { 641 pci_set_irq(pci_dev, 1); 642 } 643 644 static inline void pci_irq_deassert(PCIDevice *pci_dev) 645 { 646 pci_set_irq(pci_dev, 0); 647 } 648 649 /* 650 * FIXME: PCI does not work this way. 651 * All the callers to this method should be fixed. 652 */ 653 static inline void pci_irq_pulse(PCIDevice *pci_dev) 654 { 655 pci_irq_assert(pci_dev); 656 pci_irq_deassert(pci_dev); 657 } 658 659 static inline int pci_is_express(const PCIDevice *d) 660 { 661 return d->cap_present & QEMU_PCI_CAP_EXPRESS; 662 } 663 664 static inline uint32_t pci_config_size(const PCIDevice *d) 665 { 666 return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE; 667 } 668 669 /* DMA access functions */ 670 static inline AddressSpace *pci_get_address_space(PCIDevice *dev) 671 { 672 return &dev->bus_master_as; 673 } 674 675 static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr, 676 void *buf, dma_addr_t len, DMADirection dir) 677 { 678 dma_memory_rw(pci_get_address_space(dev), addr, buf, len, dir); 679 return 0; 680 } 681 682 static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr, 683 void *buf, dma_addr_t len) 684 { 685 return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE); 686 } 687 688 static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr, 689 const void *buf, dma_addr_t len) 690 { 691 return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE); 692 } 693 694 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \ 695 static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev, \ 696 dma_addr_t addr) \ 697 { \ 698 return ld##_l##_dma(pci_get_address_space(dev), addr); \ 699 } \ 700 static inline void st##_s##_pci_dma(PCIDevice *dev, \ 701 dma_addr_t addr, uint##_bits##_t val) \ 702 { \ 703 st##_s##_dma(pci_get_address_space(dev), addr, val); \ 704 } 705 706 PCI_DMA_DEFINE_LDST(ub, b, 8); 707 PCI_DMA_DEFINE_LDST(uw_le, w_le, 16) 708 PCI_DMA_DEFINE_LDST(l_le, l_le, 32); 709 PCI_DMA_DEFINE_LDST(q_le, q_le, 64); 710 PCI_DMA_DEFINE_LDST(uw_be, w_be, 16) 711 PCI_DMA_DEFINE_LDST(l_be, l_be, 32); 712 PCI_DMA_DEFINE_LDST(q_be, q_be, 64); 713 714 #undef PCI_DMA_DEFINE_LDST 715 716 static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr, 717 dma_addr_t *plen, DMADirection dir) 718 { 719 void *buf; 720 721 buf = dma_memory_map(pci_get_address_space(dev), addr, plen, dir); 722 return buf; 723 } 724 725 static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len, 726 DMADirection dir, dma_addr_t access_len) 727 { 728 dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len); 729 } 730 731 static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev, 732 int alloc_hint) 733 { 734 qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev)); 735 } 736 737 extern const VMStateDescription vmstate_pci_device; 738 739 #define VMSTATE_PCI_DEVICE(_field, _state) { \ 740 .name = (stringify(_field)), \ 741 .size = sizeof(PCIDevice), \ 742 .vmsd = &vmstate_pci_device, \ 743 .flags = VMS_STRUCT, \ 744 .offset = vmstate_offset_value(_state, _field, PCIDevice), \ 745 } 746 747 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \ 748 .name = (stringify(_field)), \ 749 .size = sizeof(PCIDevice), \ 750 .vmsd = &vmstate_pci_device, \ 751 .flags = VMS_STRUCT|VMS_POINTER, \ 752 .offset = vmstate_offset_pointer(_state, _field, PCIDevice), \ 753 } 754 755 #endif 756