1 #ifndef QEMU_PCI_H 2 #define QEMU_PCI_H 3 4 #include "qemu-common.h" 5 6 #include "hw/qdev.h" 7 #include "exec/memory.h" 8 #include "sysemu/dma.h" 9 #include "qapi/error.h" 10 11 /* PCI includes legacy ISA access. */ 12 #include "hw/isa/isa.h" 13 14 #include "hw/pci/pcie.h" 15 16 /* PCI bus */ 17 18 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 19 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 20 #define PCI_FUNC(devfn) ((devfn) & 0x07) 21 #define PCI_SLOT_MAX 32 22 #define PCI_FUNC_MAX 8 23 24 /* Class, Vendor and Device IDs from Linux's pci_ids.h */ 25 #include "hw/pci/pci_ids.h" 26 27 /* QEMU-specific Vendor and Device ID definitions */ 28 29 /* IBM (0x1014) */ 30 #define PCI_DEVICE_ID_IBM_440GX 0x027f 31 #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff 32 33 /* Hitachi (0x1054) */ 34 #define PCI_VENDOR_ID_HITACHI 0x1054 35 #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e 36 37 /* Apple (0x106b) */ 38 #define PCI_DEVICE_ID_APPLE_343S1201 0x0010 39 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e 40 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f 41 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022 42 #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f 43 44 /* Realtek (0x10ec) */ 45 #define PCI_DEVICE_ID_REALTEK_8029 0x8029 46 47 /* Xilinx (0x10ee) */ 48 #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300 49 50 /* Marvell (0x11ab) */ 51 #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620 52 53 /* QEMU/Bochs VGA (0x1234) */ 54 #define PCI_VENDOR_ID_QEMU 0x1234 55 #define PCI_DEVICE_ID_QEMU_VGA 0x1111 56 57 /* VMWare (0x15ad) */ 58 #define PCI_VENDOR_ID_VMWARE 0x15ad 59 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 60 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710 61 #define PCI_DEVICE_ID_VMWARE_NET 0x0720 62 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730 63 #define PCI_DEVICE_ID_VMWARE_PVSCSI 0x07C0 64 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729 65 #define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0 66 67 /* Intel (0x8086) */ 68 #define PCI_DEVICE_ID_INTEL_82551IT 0x1209 69 #define PCI_DEVICE_ID_INTEL_82557 0x1229 70 #define PCI_DEVICE_ID_INTEL_82801IR 0x2922 71 72 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */ 73 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 74 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 75 #define PCI_SUBDEVICE_ID_QEMU 0x1100 76 77 #define PCI_DEVICE_ID_VIRTIO_NET 0x1000 78 #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001 79 #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002 80 #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003 81 #define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004 82 #define PCI_DEVICE_ID_VIRTIO_RNG 0x1005 83 #define PCI_DEVICE_ID_VIRTIO_9P 0x1009 84 85 #define PCI_VENDOR_ID_REDHAT 0x1b36 86 #define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001 87 #define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002 88 #define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003 89 #define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004 90 #define PCI_DEVICE_ID_REDHAT_TEST 0x0005 91 #define PCI_DEVICE_ID_REDHAT_QXL 0x0100 92 93 #define FMT_PCIBUS PRIx64 94 95 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, 96 uint32_t address, uint32_t data, int len); 97 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev, 98 uint32_t address, int len); 99 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, 100 pcibus_t addr, pcibus_t size, int type); 101 typedef void PCIUnregisterFunc(PCIDevice *pci_dev); 102 103 typedef struct PCIIORegion { 104 pcibus_t addr; /* current PCI mapping address. -1 means not mapped */ 105 #define PCI_BAR_UNMAPPED (~(pcibus_t)0) 106 pcibus_t size; 107 uint8_t type; 108 MemoryRegion *memory; 109 MemoryRegion *address_space; 110 } PCIIORegion; 111 112 #define PCI_ROM_SLOT 6 113 #define PCI_NUM_REGIONS 7 114 115 enum { 116 QEMU_PCI_VGA_MEM, 117 QEMU_PCI_VGA_IO_LO, 118 QEMU_PCI_VGA_IO_HI, 119 QEMU_PCI_VGA_NUM_REGIONS, 120 }; 121 122 #define QEMU_PCI_VGA_MEM_BASE 0xa0000 123 #define QEMU_PCI_VGA_MEM_SIZE 0x20000 124 #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0 125 #define QEMU_PCI_VGA_IO_LO_SIZE 0xc 126 #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0 127 #define QEMU_PCI_VGA_IO_HI_SIZE 0x20 128 129 #include "hw/pci/pci_regs.h" 130 131 /* PCI HEADER_TYPE */ 132 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80 133 134 /* Size of the standard PCI config header */ 135 #define PCI_CONFIG_HEADER_SIZE 0x40 136 /* Size of the standard PCI config space */ 137 #define PCI_CONFIG_SPACE_SIZE 0x100 138 /* Size of the standart PCIe config space: 4KB */ 139 #define PCIE_CONFIG_SPACE_SIZE 0x1000 140 141 #define PCI_NUM_PINS 4 /* A-D */ 142 143 /* Bits in cap_present field. */ 144 enum { 145 QEMU_PCI_CAP_MSI = 0x1, 146 QEMU_PCI_CAP_MSIX = 0x2, 147 QEMU_PCI_CAP_EXPRESS = 0x4, 148 149 /* multifunction capable device */ 150 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3 151 QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR), 152 153 /* command register SERR bit enabled */ 154 #define QEMU_PCI_CAP_SERR_BITNR 4 155 QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR), 156 /* Standard hot plug controller. */ 157 #define QEMU_PCI_SHPC_BITNR 5 158 QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR), 159 #define QEMU_PCI_SLOTID_BITNR 6 160 QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR), 161 }; 162 163 #define TYPE_PCI_DEVICE "pci-device" 164 #define PCI_DEVICE(obj) \ 165 OBJECT_CHECK(PCIDevice, (obj), TYPE_PCI_DEVICE) 166 #define PCI_DEVICE_CLASS(klass) \ 167 OBJECT_CLASS_CHECK(PCIDeviceClass, (klass), TYPE_PCI_DEVICE) 168 #define PCI_DEVICE_GET_CLASS(obj) \ 169 OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE) 170 171 typedef struct PCIINTxRoute { 172 enum { 173 PCI_INTX_ENABLED, 174 PCI_INTX_INVERTED, 175 PCI_INTX_DISABLED, 176 } mode; 177 int irq; 178 } PCIINTxRoute; 179 180 typedef struct PCIDeviceClass { 181 DeviceClass parent_class; 182 183 int (*init)(PCIDevice *dev); 184 PCIUnregisterFunc *exit; 185 PCIConfigReadFunc *config_read; 186 PCIConfigWriteFunc *config_write; 187 188 uint16_t vendor_id; 189 uint16_t device_id; 190 uint8_t revision; 191 uint16_t class_id; 192 uint16_t subsystem_vendor_id; /* only for header type = 0 */ 193 uint16_t subsystem_id; /* only for header type = 0 */ 194 195 /* 196 * pci-to-pci bridge or normal device. 197 * This doesn't mean pci host switch. 198 * When card bus bridge is supported, this would be enhanced. 199 */ 200 int is_bridge; 201 202 /* pcie stuff */ 203 int is_express; /* is this device pci express? */ 204 205 /* rom bar */ 206 const char *romfile; 207 } PCIDeviceClass; 208 209 typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev); 210 typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector, 211 MSIMessage msg); 212 typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector); 213 typedef void (*MSIVectorPollNotifier)(PCIDevice *dev, 214 unsigned int vector_start, 215 unsigned int vector_end); 216 217 struct PCIDevice { 218 DeviceState qdev; 219 220 /* PCI config space */ 221 uint8_t *config; 222 223 /* Used to enable config checks on load. Note that writable bits are 224 * never checked even if set in cmask. */ 225 uint8_t *cmask; 226 227 /* Used to implement R/W bytes */ 228 uint8_t *wmask; 229 230 /* Used to implement RW1C(Write 1 to Clear) bytes */ 231 uint8_t *w1cmask; 232 233 /* Used to allocate config space for capabilities. */ 234 uint8_t *used; 235 236 /* the following fields are read only */ 237 PCIBus *bus; 238 int32_t devfn; 239 char name[64]; 240 PCIIORegion io_regions[PCI_NUM_REGIONS]; 241 AddressSpace bus_master_as; 242 MemoryRegion bus_master_enable_region; 243 244 /* do not access the following fields */ 245 PCIConfigReadFunc *config_read; 246 PCIConfigWriteFunc *config_write; 247 248 /* Legacy PCI VGA regions */ 249 MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS]; 250 bool has_vga; 251 252 /* Current IRQ levels. Used internally by the generic PCI code. */ 253 uint8_t irq_state; 254 255 /* Capability bits */ 256 uint32_t cap_present; 257 258 /* Offset of MSI-X capability in config space */ 259 uint8_t msix_cap; 260 261 /* MSI-X entries */ 262 int msix_entries_nr; 263 264 /* Space to store MSIX table & pending bit array */ 265 uint8_t *msix_table; 266 uint8_t *msix_pba; 267 /* MemoryRegion container for msix exclusive BAR setup */ 268 MemoryRegion msix_exclusive_bar; 269 /* Memory Regions for MSIX table and pending bit entries. */ 270 MemoryRegion msix_table_mmio; 271 MemoryRegion msix_pba_mmio; 272 /* Reference-count for entries actually in use by driver. */ 273 unsigned *msix_entry_used; 274 /* MSIX function mask set or MSIX disabled */ 275 bool msix_function_masked; 276 /* Version id needed for VMState */ 277 int32_t version_id; 278 279 /* Offset of MSI capability in config space */ 280 uint8_t msi_cap; 281 282 /* PCI Express */ 283 PCIExpressDevice exp; 284 285 /* SHPC */ 286 SHPCDevice *shpc; 287 288 /* Location of option rom */ 289 char *romfile; 290 bool has_rom; 291 MemoryRegion rom; 292 uint32_t rom_bar; 293 294 /* INTx routing notifier */ 295 PCIINTxRoutingNotifier intx_routing_notifier; 296 297 /* MSI-X notifiers */ 298 MSIVectorUseNotifier msix_vector_use_notifier; 299 MSIVectorReleaseNotifier msix_vector_release_notifier; 300 MSIVectorPollNotifier msix_vector_poll_notifier; 301 }; 302 303 void pci_register_bar(PCIDevice *pci_dev, int region_num, 304 uint8_t attr, MemoryRegion *memory); 305 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, 306 MemoryRegion *io_lo, MemoryRegion *io_hi); 307 void pci_unregister_vga(PCIDevice *pci_dev); 308 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num); 309 310 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, 311 uint8_t offset, uint8_t size); 312 int pci_add_capability2(PCIDevice *pdev, uint8_t cap_id, 313 uint8_t offset, uint8_t size, 314 Error **errp); 315 316 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size); 317 318 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id); 319 320 321 uint32_t pci_default_read_config(PCIDevice *d, 322 uint32_t address, int len); 323 void pci_default_write_config(PCIDevice *d, 324 uint32_t address, uint32_t val, int len); 325 void pci_device_save(PCIDevice *s, QEMUFile *f); 326 int pci_device_load(PCIDevice *s, QEMUFile *f); 327 MemoryRegion *pci_address_space(PCIDevice *dev); 328 MemoryRegion *pci_address_space_io(PCIDevice *dev); 329 330 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level); 331 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); 332 typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin); 333 334 #define TYPE_PCI_BUS "PCI" 335 #define PCI_BUS(obj) OBJECT_CHECK(PCIBus, (obj), TYPE_PCI_BUS) 336 #define TYPE_PCIE_BUS "PCIE" 337 338 bool pci_bus_is_express(PCIBus *bus); 339 bool pci_bus_is_root(PCIBus *bus); 340 void pci_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent, 341 const char *name, 342 MemoryRegion *address_space_mem, 343 MemoryRegion *address_space_io, 344 uint8_t devfn_min, const char *typename); 345 PCIBus *pci_bus_new(DeviceState *parent, const char *name, 346 MemoryRegion *address_space_mem, 347 MemoryRegion *address_space_io, 348 uint8_t devfn_min, const char *typename); 349 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 350 void *irq_opaque, int nirq); 351 int pci_bus_get_irq_level(PCIBus *bus, int irq_num); 352 /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */ 353 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin); 354 PCIBus *pci_register_bus(DeviceState *parent, const char *name, 355 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 356 void *irq_opaque, 357 MemoryRegion *address_space_mem, 358 MemoryRegion *address_space_io, 359 uint8_t devfn_min, int nirq, const char *typename); 360 void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn); 361 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin); 362 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new); 363 void pci_bus_fire_intx_routing_notifier(PCIBus *bus); 364 void pci_device_set_intx_routing_notifier(PCIDevice *dev, 365 PCIINTxRoutingNotifier notifier); 366 void pci_device_reset(PCIDevice *dev); 367 368 PCIDevice *pci_nic_init(NICInfo *nd, PCIBus *rootbus, 369 const char *default_model, 370 const char *default_devaddr); 371 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus, 372 const char *default_model, 373 const char *default_devaddr); 374 375 PCIDevice *pci_vga_init(PCIBus *bus); 376 377 int pci_bus_num(PCIBus *s); 378 void pci_for_each_device(PCIBus *bus, int bus_num, 379 void (*fn)(PCIBus *bus, PCIDevice *d, void *opaque), 380 void *opaque); 381 void pci_for_each_bus_depth_first(PCIBus *bus, 382 void *(*begin)(PCIBus *bus, void *parent_state), 383 void (*end)(PCIBus *bus, void *state), 384 void *parent_state); 385 386 /* Use this wrapper when specific scan order is not required. */ 387 static inline 388 void pci_for_each_bus(PCIBus *bus, 389 void (*fn)(PCIBus *bus, void *opaque), 390 void *opaque) 391 { 392 pci_for_each_bus_depth_first(bus, NULL, fn, opaque); 393 } 394 395 PCIBus *pci_find_primary_bus(void); 396 PCIBus *pci_device_root_bus(const PCIDevice *d); 397 const char *pci_root_bus_path(PCIDevice *dev); 398 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn); 399 int pci_qdev_find_device(const char *id, PCIDevice **pdev); 400 PCIBus *pci_get_bus_devfn(int *devfnp, PCIBus *root, const char *devaddr); 401 void pci_bus_get_w64_range(PCIBus *bus, Range *range); 402 403 int pci_parse_devaddr(const char *addr, int *domp, int *busp, 404 unsigned int *slotp, unsigned int *funcp); 405 406 void pci_device_deassert_intx(PCIDevice *dev); 407 408 typedef AddressSpace *(*PCIIOMMUFunc)(PCIBus *, void *, int); 409 410 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev); 411 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque); 412 413 static inline void 414 pci_set_byte(uint8_t *config, uint8_t val) 415 { 416 *config = val; 417 } 418 419 static inline uint8_t 420 pci_get_byte(const uint8_t *config) 421 { 422 return *config; 423 } 424 425 static inline void 426 pci_set_word(uint8_t *config, uint16_t val) 427 { 428 stw_le_p(config, val); 429 } 430 431 static inline uint16_t 432 pci_get_word(const uint8_t *config) 433 { 434 return lduw_le_p(config); 435 } 436 437 static inline void 438 pci_set_long(uint8_t *config, uint32_t val) 439 { 440 stl_le_p(config, val); 441 } 442 443 static inline uint32_t 444 pci_get_long(const uint8_t *config) 445 { 446 return ldl_le_p(config); 447 } 448 449 static inline void 450 pci_set_quad(uint8_t *config, uint64_t val) 451 { 452 cpu_to_le64w((uint64_t *)config, val); 453 } 454 455 static inline uint64_t 456 pci_get_quad(const uint8_t *config) 457 { 458 return le64_to_cpup((const uint64_t *)config); 459 } 460 461 static inline void 462 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val) 463 { 464 pci_set_word(&pci_config[PCI_VENDOR_ID], val); 465 } 466 467 static inline void 468 pci_config_set_device_id(uint8_t *pci_config, uint16_t val) 469 { 470 pci_set_word(&pci_config[PCI_DEVICE_ID], val); 471 } 472 473 static inline void 474 pci_config_set_revision(uint8_t *pci_config, uint8_t val) 475 { 476 pci_set_byte(&pci_config[PCI_REVISION_ID], val); 477 } 478 479 static inline void 480 pci_config_set_class(uint8_t *pci_config, uint16_t val) 481 { 482 pci_set_word(&pci_config[PCI_CLASS_DEVICE], val); 483 } 484 485 static inline void 486 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val) 487 { 488 pci_set_byte(&pci_config[PCI_CLASS_PROG], val); 489 } 490 491 static inline void 492 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val) 493 { 494 pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val); 495 } 496 497 /* 498 * helper functions to do bit mask operation on configuration space. 499 * Just to set bit, use test-and-set and discard returned value. 500 * Just to clear bit, use test-and-clear and discard returned value. 501 * NOTE: They aren't atomic. 502 */ 503 static inline uint8_t 504 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask) 505 { 506 uint8_t val = pci_get_byte(config); 507 pci_set_byte(config, val & ~mask); 508 return val & mask; 509 } 510 511 static inline uint8_t 512 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask) 513 { 514 uint8_t val = pci_get_byte(config); 515 pci_set_byte(config, val | mask); 516 return val & mask; 517 } 518 519 static inline uint16_t 520 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask) 521 { 522 uint16_t val = pci_get_word(config); 523 pci_set_word(config, val & ~mask); 524 return val & mask; 525 } 526 527 static inline uint16_t 528 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask) 529 { 530 uint16_t val = pci_get_word(config); 531 pci_set_word(config, val | mask); 532 return val & mask; 533 } 534 535 static inline uint32_t 536 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask) 537 { 538 uint32_t val = pci_get_long(config); 539 pci_set_long(config, val & ~mask); 540 return val & mask; 541 } 542 543 static inline uint32_t 544 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask) 545 { 546 uint32_t val = pci_get_long(config); 547 pci_set_long(config, val | mask); 548 return val & mask; 549 } 550 551 static inline uint64_t 552 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask) 553 { 554 uint64_t val = pci_get_quad(config); 555 pci_set_quad(config, val & ~mask); 556 return val & mask; 557 } 558 559 static inline uint64_t 560 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask) 561 { 562 uint64_t val = pci_get_quad(config); 563 pci_set_quad(config, val | mask); 564 return val & mask; 565 } 566 567 /* Access a register specified by a mask */ 568 static inline void 569 pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg) 570 { 571 uint8_t val = pci_get_byte(config); 572 uint8_t rval = reg << (ffs(mask) - 1); 573 pci_set_byte(config, (~mask & val) | (mask & rval)); 574 } 575 576 static inline uint8_t 577 pci_get_byte_by_mask(uint8_t *config, uint8_t mask) 578 { 579 uint8_t val = pci_get_byte(config); 580 return (val & mask) >> (ffs(mask) - 1); 581 } 582 583 static inline void 584 pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg) 585 { 586 uint16_t val = pci_get_word(config); 587 uint16_t rval = reg << (ffs(mask) - 1); 588 pci_set_word(config, (~mask & val) | (mask & rval)); 589 } 590 591 static inline uint16_t 592 pci_get_word_by_mask(uint8_t *config, uint16_t mask) 593 { 594 uint16_t val = pci_get_word(config); 595 return (val & mask) >> (ffs(mask) - 1); 596 } 597 598 static inline void 599 pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg) 600 { 601 uint32_t val = pci_get_long(config); 602 uint32_t rval = reg << (ffs(mask) - 1); 603 pci_set_long(config, (~mask & val) | (mask & rval)); 604 } 605 606 static inline uint32_t 607 pci_get_long_by_mask(uint8_t *config, uint32_t mask) 608 { 609 uint32_t val = pci_get_long(config); 610 return (val & mask) >> (ffs(mask) - 1); 611 } 612 613 static inline void 614 pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg) 615 { 616 uint64_t val = pci_get_quad(config); 617 uint64_t rval = reg << (ffs(mask) - 1); 618 pci_set_quad(config, (~mask & val) | (mask & rval)); 619 } 620 621 static inline uint64_t 622 pci_get_quad_by_mask(uint8_t *config, uint64_t mask) 623 { 624 uint64_t val = pci_get_quad(config); 625 return (val & mask) >> (ffs(mask) - 1); 626 } 627 628 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction, 629 const char *name); 630 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, 631 bool multifunction, 632 const char *name); 633 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name); 634 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name); 635 636 qemu_irq pci_allocate_irq(PCIDevice *pci_dev); 637 void pci_set_irq(PCIDevice *pci_dev, int level); 638 639 static inline void pci_irq_assert(PCIDevice *pci_dev) 640 { 641 pci_set_irq(pci_dev, 1); 642 } 643 644 static inline void pci_irq_deassert(PCIDevice *pci_dev) 645 { 646 pci_set_irq(pci_dev, 0); 647 } 648 649 /* 650 * FIXME: PCI does not work this way. 651 * All the callers to this method should be fixed. 652 */ 653 static inline void pci_irq_pulse(PCIDevice *pci_dev) 654 { 655 pci_irq_assert(pci_dev); 656 pci_irq_deassert(pci_dev); 657 } 658 659 static inline int pci_is_express(const PCIDevice *d) 660 { 661 return d->cap_present & QEMU_PCI_CAP_EXPRESS; 662 } 663 664 static inline uint32_t pci_config_size(const PCIDevice *d) 665 { 666 return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE; 667 } 668 669 /* DMA access functions */ 670 static inline AddressSpace *pci_get_address_space(PCIDevice *dev) 671 { 672 return &dev->bus_master_as; 673 } 674 675 static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr, 676 void *buf, dma_addr_t len, DMADirection dir) 677 { 678 dma_memory_rw(pci_get_address_space(dev), addr, buf, len, dir); 679 return 0; 680 } 681 682 static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr, 683 void *buf, dma_addr_t len) 684 { 685 return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE); 686 } 687 688 static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr, 689 const void *buf, dma_addr_t len) 690 { 691 return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE); 692 } 693 694 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \ 695 static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev, \ 696 dma_addr_t addr) \ 697 { \ 698 return ld##_l##_dma(pci_get_address_space(dev), addr); \ 699 } \ 700 static inline void st##_s##_pci_dma(PCIDevice *dev, \ 701 dma_addr_t addr, uint##_bits##_t val) \ 702 { \ 703 st##_s##_dma(pci_get_address_space(dev), addr, val); \ 704 } 705 706 PCI_DMA_DEFINE_LDST(ub, b, 8); 707 PCI_DMA_DEFINE_LDST(uw_le, w_le, 16) 708 PCI_DMA_DEFINE_LDST(l_le, l_le, 32); 709 PCI_DMA_DEFINE_LDST(q_le, q_le, 64); 710 PCI_DMA_DEFINE_LDST(uw_be, w_be, 16) 711 PCI_DMA_DEFINE_LDST(l_be, l_be, 32); 712 PCI_DMA_DEFINE_LDST(q_be, q_be, 64); 713 714 #undef PCI_DMA_DEFINE_LDST 715 716 static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr, 717 dma_addr_t *plen, DMADirection dir) 718 { 719 void *buf; 720 721 buf = dma_memory_map(pci_get_address_space(dev), addr, plen, dir); 722 return buf; 723 } 724 725 static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len, 726 DMADirection dir, dma_addr_t access_len) 727 { 728 dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len); 729 } 730 731 static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev, 732 int alloc_hint) 733 { 734 qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev)); 735 } 736 737 extern const VMStateDescription vmstate_pci_device; 738 739 #define VMSTATE_PCI_DEVICE(_field, _state) { \ 740 .name = (stringify(_field)), \ 741 .size = sizeof(PCIDevice), \ 742 .vmsd = &vmstate_pci_device, \ 743 .flags = VMS_STRUCT, \ 744 .offset = vmstate_offset_value(_state, _field, PCIDevice), \ 745 } 746 747 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \ 748 .name = (stringify(_field)), \ 749 .size = sizeof(PCIDevice), \ 750 .vmsd = &vmstate_pci_device, \ 751 .flags = VMS_STRUCT|VMS_POINTER, \ 752 .offset = vmstate_offset_pointer(_state, _field, PCIDevice), \ 753 } 754 755 #endif 756