1 #ifndef QEMU_PCI_H 2 #define QEMU_PCI_H 3 4 #include "qemu-common.h" 5 6 #include "hw/qdev.h" 7 #include "exec/memory.h" 8 #include "sysemu/dma.h" 9 #include "qapi/error.h" 10 11 /* PCI includes legacy ISA access. */ 12 #include "hw/isa/isa.h" 13 14 #include "hw/pci/pcie.h" 15 16 /* PCI bus */ 17 18 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 19 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 20 #define PCI_FUNC(devfn) ((devfn) & 0x07) 21 #define PCI_SLOT_MAX 32 22 #define PCI_FUNC_MAX 8 23 24 /* Class, Vendor and Device IDs from Linux's pci_ids.h */ 25 #include "hw/pci/pci_ids.h" 26 27 /* QEMU-specific Vendor and Device ID definitions */ 28 29 /* IBM (0x1014) */ 30 #define PCI_DEVICE_ID_IBM_440GX 0x027f 31 #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff 32 33 /* Hitachi (0x1054) */ 34 #define PCI_VENDOR_ID_HITACHI 0x1054 35 #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e 36 37 /* Apple (0x106b) */ 38 #define PCI_DEVICE_ID_APPLE_343S1201 0x0010 39 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e 40 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f 41 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022 42 #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f 43 44 /* Realtek (0x10ec) */ 45 #define PCI_DEVICE_ID_REALTEK_8029 0x8029 46 47 /* Xilinx (0x10ee) */ 48 #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300 49 50 /* Marvell (0x11ab) */ 51 #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620 52 53 /* QEMU/Bochs VGA (0x1234) */ 54 #define PCI_VENDOR_ID_QEMU 0x1234 55 #define PCI_DEVICE_ID_QEMU_VGA 0x1111 56 57 /* VMWare (0x15ad) */ 58 #define PCI_VENDOR_ID_VMWARE 0x15ad 59 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 60 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710 61 #define PCI_DEVICE_ID_VMWARE_NET 0x0720 62 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730 63 #define PCI_DEVICE_ID_VMWARE_PVSCSI 0x07C0 64 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729 65 #define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0 66 67 /* Intel (0x8086) */ 68 #define PCI_DEVICE_ID_INTEL_82551IT 0x1209 69 #define PCI_DEVICE_ID_INTEL_82557 0x1229 70 #define PCI_DEVICE_ID_INTEL_82801IR 0x2922 71 72 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */ 73 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 74 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 75 #define PCI_SUBDEVICE_ID_QEMU 0x1100 76 77 #define PCI_DEVICE_ID_VIRTIO_NET 0x1000 78 #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001 79 #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002 80 #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003 81 #define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004 82 #define PCI_DEVICE_ID_VIRTIO_RNG 0x1005 83 #define PCI_DEVICE_ID_VIRTIO_9P 0x1009 84 85 #define PCI_VENDOR_ID_REDHAT 0x1b36 86 #define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001 87 #define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002 88 #define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003 89 #define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004 90 #define PCI_DEVICE_ID_REDHAT_TEST 0x0005 91 #define PCI_DEVICE_ID_REDHAT_ROCKER 0x0006 92 #define PCI_DEVICE_ID_REDHAT_SDHCI 0x0007 93 #define PCI_DEVICE_ID_REDHAT_PCIE_HOST 0x0008 94 #define PCI_DEVICE_ID_REDHAT_PXB 0x0009 95 #define PCI_DEVICE_ID_REDHAT_BRIDGE_SEAT 0x000a 96 #define PCI_DEVICE_ID_REDHAT_PXB_PCIE 0x000b 97 #define PCI_DEVICE_ID_REDHAT_QXL 0x0100 98 99 #define FMT_PCIBUS PRIx64 100 101 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, 102 uint32_t address, uint32_t data, int len); 103 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev, 104 uint32_t address, int len); 105 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, 106 pcibus_t addr, pcibus_t size, int type); 107 typedef void PCIUnregisterFunc(PCIDevice *pci_dev); 108 109 typedef struct PCIIORegion { 110 pcibus_t addr; /* current PCI mapping address. -1 means not mapped */ 111 #define PCI_BAR_UNMAPPED (~(pcibus_t)0) 112 pcibus_t size; 113 uint8_t type; 114 MemoryRegion *memory; 115 MemoryRegion *address_space; 116 } PCIIORegion; 117 118 #define PCI_ROM_SLOT 6 119 #define PCI_NUM_REGIONS 7 120 121 enum { 122 QEMU_PCI_VGA_MEM, 123 QEMU_PCI_VGA_IO_LO, 124 QEMU_PCI_VGA_IO_HI, 125 QEMU_PCI_VGA_NUM_REGIONS, 126 }; 127 128 #define QEMU_PCI_VGA_MEM_BASE 0xa0000 129 #define QEMU_PCI_VGA_MEM_SIZE 0x20000 130 #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0 131 #define QEMU_PCI_VGA_IO_LO_SIZE 0xc 132 #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0 133 #define QEMU_PCI_VGA_IO_HI_SIZE 0x20 134 135 #include "hw/pci/pci_regs.h" 136 137 /* PCI HEADER_TYPE */ 138 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80 139 140 /* Size of the standard PCI config header */ 141 #define PCI_CONFIG_HEADER_SIZE 0x40 142 /* Size of the standard PCI config space */ 143 #define PCI_CONFIG_SPACE_SIZE 0x100 144 /* Size of the standard PCIe config space: 4KB */ 145 #define PCIE_CONFIG_SPACE_SIZE 0x1000 146 147 #define PCI_NUM_PINS 4 /* A-D */ 148 149 /* Bits in cap_present field. */ 150 enum { 151 QEMU_PCI_CAP_MSI = 0x1, 152 QEMU_PCI_CAP_MSIX = 0x2, 153 QEMU_PCI_CAP_EXPRESS = 0x4, 154 155 /* multifunction capable device */ 156 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3 157 QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR), 158 159 /* command register SERR bit enabled */ 160 #define QEMU_PCI_CAP_SERR_BITNR 4 161 QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR), 162 /* Standard hot plug controller. */ 163 #define QEMU_PCI_SHPC_BITNR 5 164 QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR), 165 #define QEMU_PCI_SLOTID_BITNR 6 166 QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR), 167 /* PCI Express capability - Power Controller Present */ 168 #define QEMU_PCIE_SLTCAP_PCP_BITNR 7 169 QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR), 170 }; 171 172 #define TYPE_PCI_DEVICE "pci-device" 173 #define PCI_DEVICE(obj) \ 174 OBJECT_CHECK(PCIDevice, (obj), TYPE_PCI_DEVICE) 175 #define PCI_DEVICE_CLASS(klass) \ 176 OBJECT_CLASS_CHECK(PCIDeviceClass, (klass), TYPE_PCI_DEVICE) 177 #define PCI_DEVICE_GET_CLASS(obj) \ 178 OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE) 179 180 typedef struct PCIINTxRoute { 181 enum { 182 PCI_INTX_ENABLED, 183 PCI_INTX_INVERTED, 184 PCI_INTX_DISABLED, 185 } mode; 186 int irq; 187 } PCIINTxRoute; 188 189 typedef struct PCIDeviceClass { 190 DeviceClass parent_class; 191 192 void (*realize)(PCIDevice *dev, Error **errp); 193 int (*init)(PCIDevice *dev);/* TODO convert to realize() and remove */ 194 PCIUnregisterFunc *exit; 195 PCIConfigReadFunc *config_read; 196 PCIConfigWriteFunc *config_write; 197 198 uint16_t vendor_id; 199 uint16_t device_id; 200 uint8_t revision; 201 uint16_t class_id; 202 uint16_t subsystem_vendor_id; /* only for header type = 0 */ 203 uint16_t subsystem_id; /* only for header type = 0 */ 204 205 /* 206 * pci-to-pci bridge or normal device. 207 * This doesn't mean pci host switch. 208 * When card bus bridge is supported, this would be enhanced. 209 */ 210 int is_bridge; 211 212 /* pcie stuff */ 213 int is_express; /* is this device pci express? */ 214 215 /* rom bar */ 216 const char *romfile; 217 } PCIDeviceClass; 218 219 typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev); 220 typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector, 221 MSIMessage msg); 222 typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector); 223 typedef void (*MSIVectorPollNotifier)(PCIDevice *dev, 224 unsigned int vector_start, 225 unsigned int vector_end); 226 227 struct PCIDevice { 228 DeviceState qdev; 229 230 /* PCI config space */ 231 uint8_t *config; 232 233 /* Used to enable config checks on load. Note that writable bits are 234 * never checked even if set in cmask. */ 235 uint8_t *cmask; 236 237 /* Used to implement R/W bytes */ 238 uint8_t *wmask; 239 240 /* Used to implement RW1C(Write 1 to Clear) bytes */ 241 uint8_t *w1cmask; 242 243 /* Used to allocate config space for capabilities. */ 244 uint8_t *used; 245 246 /* the following fields are read only */ 247 PCIBus *bus; 248 int32_t devfn; 249 char name[64]; 250 PCIIORegion io_regions[PCI_NUM_REGIONS]; 251 AddressSpace bus_master_as; 252 MemoryRegion bus_master_enable_region; 253 254 /* do not access the following fields */ 255 PCIConfigReadFunc *config_read; 256 PCIConfigWriteFunc *config_write; 257 258 /* Legacy PCI VGA regions */ 259 MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS]; 260 bool has_vga; 261 262 /* Current IRQ levels. Used internally by the generic PCI code. */ 263 uint8_t irq_state; 264 265 /* Capability bits */ 266 uint32_t cap_present; 267 268 /* Offset of MSI-X capability in config space */ 269 uint8_t msix_cap; 270 271 /* MSI-X entries */ 272 int msix_entries_nr; 273 274 /* Space to store MSIX table & pending bit array */ 275 uint8_t *msix_table; 276 uint8_t *msix_pba; 277 /* MemoryRegion container for msix exclusive BAR setup */ 278 MemoryRegion msix_exclusive_bar; 279 /* Memory Regions for MSIX table and pending bit entries. */ 280 MemoryRegion msix_table_mmio; 281 MemoryRegion msix_pba_mmio; 282 /* Reference-count for entries actually in use by driver. */ 283 unsigned *msix_entry_used; 284 /* MSIX function mask set or MSIX disabled */ 285 bool msix_function_masked; 286 /* Version id needed for VMState */ 287 int32_t version_id; 288 289 /* Offset of MSI capability in config space */ 290 uint8_t msi_cap; 291 292 /* PCI Express */ 293 PCIExpressDevice exp; 294 295 /* SHPC */ 296 SHPCDevice *shpc; 297 298 /* Location of option rom */ 299 char *romfile; 300 bool has_rom; 301 MemoryRegion rom; 302 uint32_t rom_bar; 303 304 /* INTx routing notifier */ 305 PCIINTxRoutingNotifier intx_routing_notifier; 306 307 /* MSI-X notifiers */ 308 MSIVectorUseNotifier msix_vector_use_notifier; 309 MSIVectorReleaseNotifier msix_vector_release_notifier; 310 MSIVectorPollNotifier msix_vector_poll_notifier; 311 }; 312 313 void pci_register_bar(PCIDevice *pci_dev, int region_num, 314 uint8_t attr, MemoryRegion *memory); 315 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, 316 MemoryRegion *io_lo, MemoryRegion *io_hi); 317 void pci_unregister_vga(PCIDevice *pci_dev); 318 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num); 319 320 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, 321 uint8_t offset, uint8_t size); 322 int pci_add_capability2(PCIDevice *pdev, uint8_t cap_id, 323 uint8_t offset, uint8_t size, 324 Error **errp); 325 326 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size); 327 328 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id); 329 330 331 uint32_t pci_default_read_config(PCIDevice *d, 332 uint32_t address, int len); 333 void pci_default_write_config(PCIDevice *d, 334 uint32_t address, uint32_t val, int len); 335 void pci_device_save(PCIDevice *s, QEMUFile *f); 336 int pci_device_load(PCIDevice *s, QEMUFile *f); 337 MemoryRegion *pci_address_space(PCIDevice *dev); 338 MemoryRegion *pci_address_space_io(PCIDevice *dev); 339 340 /* 341 * Should not normally be used by devices. For use by sPAPR target 342 * where QEMU emulates firmware. 343 */ 344 int pci_bar(PCIDevice *d, int reg); 345 346 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level); 347 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); 348 typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin); 349 350 #define TYPE_PCI_BUS "PCI" 351 #define PCI_BUS(obj) OBJECT_CHECK(PCIBus, (obj), TYPE_PCI_BUS) 352 #define PCI_BUS_CLASS(klass) OBJECT_CLASS_CHECK(PCIBusClass, (klass), TYPE_PCI_BUS) 353 #define PCI_BUS_GET_CLASS(obj) OBJECT_GET_CLASS(PCIBusClass, (obj), TYPE_PCI_BUS) 354 #define TYPE_PCIE_BUS "PCIE" 355 356 bool pci_bus_is_express(PCIBus *bus); 357 bool pci_bus_is_root(PCIBus *bus); 358 void pci_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent, 359 const char *name, 360 MemoryRegion *address_space_mem, 361 MemoryRegion *address_space_io, 362 uint8_t devfn_min, const char *typename); 363 PCIBus *pci_bus_new(DeviceState *parent, const char *name, 364 MemoryRegion *address_space_mem, 365 MemoryRegion *address_space_io, 366 uint8_t devfn_min, const char *typename); 367 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 368 void *irq_opaque, int nirq); 369 int pci_bus_get_irq_level(PCIBus *bus, int irq_num); 370 /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */ 371 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin); 372 PCIBus *pci_register_bus(DeviceState *parent, const char *name, 373 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 374 void *irq_opaque, 375 MemoryRegion *address_space_mem, 376 MemoryRegion *address_space_io, 377 uint8_t devfn_min, int nirq, const char *typename); 378 void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn); 379 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin); 380 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new); 381 void pci_bus_fire_intx_routing_notifier(PCIBus *bus); 382 void pci_device_set_intx_routing_notifier(PCIDevice *dev, 383 PCIINTxRoutingNotifier notifier); 384 void pci_device_reset(PCIDevice *dev); 385 386 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus, 387 const char *default_model, 388 const char *default_devaddr); 389 390 PCIDevice *pci_vga_init(PCIBus *bus); 391 392 int pci_bus_num(PCIBus *s); 393 int pci_bus_numa_node(PCIBus *bus); 394 void pci_for_each_device(PCIBus *bus, int bus_num, 395 void (*fn)(PCIBus *bus, PCIDevice *d, void *opaque), 396 void *opaque); 397 void pci_for_each_bus_depth_first(PCIBus *bus, 398 void *(*begin)(PCIBus *bus, void *parent_state), 399 void (*end)(PCIBus *bus, void *state), 400 void *parent_state); 401 PCIDevice *pci_get_function_0(PCIDevice *pci_dev); 402 403 /* Use this wrapper when specific scan order is not required. */ 404 static inline 405 void pci_for_each_bus(PCIBus *bus, 406 void (*fn)(PCIBus *bus, void *opaque), 407 void *opaque) 408 { 409 pci_for_each_bus_depth_first(bus, NULL, fn, opaque); 410 } 411 412 PCIBus *pci_find_primary_bus(void); 413 PCIBus *pci_device_root_bus(const PCIDevice *d); 414 const char *pci_root_bus_path(PCIDevice *dev); 415 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn); 416 int pci_qdev_find_device(const char *id, PCIDevice **pdev); 417 void pci_bus_get_w64_range(PCIBus *bus, Range *range); 418 419 void pci_device_deassert_intx(PCIDevice *dev); 420 421 typedef AddressSpace *(*PCIIOMMUFunc)(PCIBus *, void *, int); 422 423 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev); 424 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque); 425 426 static inline void 427 pci_set_byte(uint8_t *config, uint8_t val) 428 { 429 *config = val; 430 } 431 432 static inline uint8_t 433 pci_get_byte(const uint8_t *config) 434 { 435 return *config; 436 } 437 438 static inline void 439 pci_set_word(uint8_t *config, uint16_t val) 440 { 441 stw_le_p(config, val); 442 } 443 444 static inline uint16_t 445 pci_get_word(const uint8_t *config) 446 { 447 return lduw_le_p(config); 448 } 449 450 static inline void 451 pci_set_long(uint8_t *config, uint32_t val) 452 { 453 stl_le_p(config, val); 454 } 455 456 static inline uint32_t 457 pci_get_long(const uint8_t *config) 458 { 459 return ldl_le_p(config); 460 } 461 462 static inline void 463 pci_set_quad(uint8_t *config, uint64_t val) 464 { 465 cpu_to_le64w((uint64_t *)config, val); 466 } 467 468 static inline uint64_t 469 pci_get_quad(const uint8_t *config) 470 { 471 return le64_to_cpup((const uint64_t *)config); 472 } 473 474 static inline void 475 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val) 476 { 477 pci_set_word(&pci_config[PCI_VENDOR_ID], val); 478 } 479 480 static inline void 481 pci_config_set_device_id(uint8_t *pci_config, uint16_t val) 482 { 483 pci_set_word(&pci_config[PCI_DEVICE_ID], val); 484 } 485 486 static inline void 487 pci_config_set_revision(uint8_t *pci_config, uint8_t val) 488 { 489 pci_set_byte(&pci_config[PCI_REVISION_ID], val); 490 } 491 492 static inline void 493 pci_config_set_class(uint8_t *pci_config, uint16_t val) 494 { 495 pci_set_word(&pci_config[PCI_CLASS_DEVICE], val); 496 } 497 498 static inline void 499 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val) 500 { 501 pci_set_byte(&pci_config[PCI_CLASS_PROG], val); 502 } 503 504 static inline void 505 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val) 506 { 507 pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val); 508 } 509 510 /* 511 * helper functions to do bit mask operation on configuration space. 512 * Just to set bit, use test-and-set and discard returned value. 513 * Just to clear bit, use test-and-clear and discard returned value. 514 * NOTE: They aren't atomic. 515 */ 516 static inline uint8_t 517 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask) 518 { 519 uint8_t val = pci_get_byte(config); 520 pci_set_byte(config, val & ~mask); 521 return val & mask; 522 } 523 524 static inline uint8_t 525 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask) 526 { 527 uint8_t val = pci_get_byte(config); 528 pci_set_byte(config, val | mask); 529 return val & mask; 530 } 531 532 static inline uint16_t 533 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask) 534 { 535 uint16_t val = pci_get_word(config); 536 pci_set_word(config, val & ~mask); 537 return val & mask; 538 } 539 540 static inline uint16_t 541 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask) 542 { 543 uint16_t val = pci_get_word(config); 544 pci_set_word(config, val | mask); 545 return val & mask; 546 } 547 548 static inline uint32_t 549 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask) 550 { 551 uint32_t val = pci_get_long(config); 552 pci_set_long(config, val & ~mask); 553 return val & mask; 554 } 555 556 static inline uint32_t 557 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask) 558 { 559 uint32_t val = pci_get_long(config); 560 pci_set_long(config, val | mask); 561 return val & mask; 562 } 563 564 static inline uint64_t 565 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask) 566 { 567 uint64_t val = pci_get_quad(config); 568 pci_set_quad(config, val & ~mask); 569 return val & mask; 570 } 571 572 static inline uint64_t 573 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask) 574 { 575 uint64_t val = pci_get_quad(config); 576 pci_set_quad(config, val | mask); 577 return val & mask; 578 } 579 580 /* Access a register specified by a mask */ 581 static inline void 582 pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg) 583 { 584 uint8_t val = pci_get_byte(config); 585 uint8_t rval = reg << ctz32(mask); 586 pci_set_byte(config, (~mask & val) | (mask & rval)); 587 } 588 589 static inline uint8_t 590 pci_get_byte_by_mask(uint8_t *config, uint8_t mask) 591 { 592 uint8_t val = pci_get_byte(config); 593 return (val & mask) >> ctz32(mask); 594 } 595 596 static inline void 597 pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg) 598 { 599 uint16_t val = pci_get_word(config); 600 uint16_t rval = reg << ctz32(mask); 601 pci_set_word(config, (~mask & val) | (mask & rval)); 602 } 603 604 static inline uint16_t 605 pci_get_word_by_mask(uint8_t *config, uint16_t mask) 606 { 607 uint16_t val = pci_get_word(config); 608 return (val & mask) >> ctz32(mask); 609 } 610 611 static inline void 612 pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg) 613 { 614 uint32_t val = pci_get_long(config); 615 uint32_t rval = reg << ctz32(mask); 616 pci_set_long(config, (~mask & val) | (mask & rval)); 617 } 618 619 static inline uint32_t 620 pci_get_long_by_mask(uint8_t *config, uint32_t mask) 621 { 622 uint32_t val = pci_get_long(config); 623 return (val & mask) >> ctz32(mask); 624 } 625 626 static inline void 627 pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg) 628 { 629 uint64_t val = pci_get_quad(config); 630 uint64_t rval = reg << ctz32(mask); 631 pci_set_quad(config, (~mask & val) | (mask & rval)); 632 } 633 634 static inline uint64_t 635 pci_get_quad_by_mask(uint8_t *config, uint64_t mask) 636 { 637 uint64_t val = pci_get_quad(config); 638 return (val & mask) >> ctz32(mask); 639 } 640 641 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction, 642 const char *name); 643 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, 644 bool multifunction, 645 const char *name); 646 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name); 647 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name); 648 649 qemu_irq pci_allocate_irq(PCIDevice *pci_dev); 650 void pci_set_irq(PCIDevice *pci_dev, int level); 651 652 static inline void pci_irq_assert(PCIDevice *pci_dev) 653 { 654 pci_set_irq(pci_dev, 1); 655 } 656 657 static inline void pci_irq_deassert(PCIDevice *pci_dev) 658 { 659 pci_set_irq(pci_dev, 0); 660 } 661 662 /* 663 * FIXME: PCI does not work this way. 664 * All the callers to this method should be fixed. 665 */ 666 static inline void pci_irq_pulse(PCIDevice *pci_dev) 667 { 668 pci_irq_assert(pci_dev); 669 pci_irq_deassert(pci_dev); 670 } 671 672 static inline int pci_is_express(const PCIDevice *d) 673 { 674 return d->cap_present & QEMU_PCI_CAP_EXPRESS; 675 } 676 677 static inline uint32_t pci_config_size(const PCIDevice *d) 678 { 679 return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE; 680 } 681 682 static inline uint16_t pci_requester_id(PCIDevice *dev) 683 { 684 return (pci_bus_num(dev->bus) << 8) | dev->devfn; 685 } 686 687 /* DMA access functions */ 688 static inline AddressSpace *pci_get_address_space(PCIDevice *dev) 689 { 690 return &dev->bus_master_as; 691 } 692 693 static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr, 694 void *buf, dma_addr_t len, DMADirection dir) 695 { 696 dma_memory_rw(pci_get_address_space(dev), addr, buf, len, dir); 697 return 0; 698 } 699 700 static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr, 701 void *buf, dma_addr_t len) 702 { 703 return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE); 704 } 705 706 static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr, 707 const void *buf, dma_addr_t len) 708 { 709 return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE); 710 } 711 712 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \ 713 static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev, \ 714 dma_addr_t addr) \ 715 { \ 716 return ld##_l##_dma(pci_get_address_space(dev), addr); \ 717 } \ 718 static inline void st##_s##_pci_dma(PCIDevice *dev, \ 719 dma_addr_t addr, uint##_bits##_t val) \ 720 { \ 721 st##_s##_dma(pci_get_address_space(dev), addr, val); \ 722 } 723 724 PCI_DMA_DEFINE_LDST(ub, b, 8); 725 PCI_DMA_DEFINE_LDST(uw_le, w_le, 16) 726 PCI_DMA_DEFINE_LDST(l_le, l_le, 32); 727 PCI_DMA_DEFINE_LDST(q_le, q_le, 64); 728 PCI_DMA_DEFINE_LDST(uw_be, w_be, 16) 729 PCI_DMA_DEFINE_LDST(l_be, l_be, 32); 730 PCI_DMA_DEFINE_LDST(q_be, q_be, 64); 731 732 #undef PCI_DMA_DEFINE_LDST 733 734 static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr, 735 dma_addr_t *plen, DMADirection dir) 736 { 737 void *buf; 738 739 buf = dma_memory_map(pci_get_address_space(dev), addr, plen, dir); 740 return buf; 741 } 742 743 static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len, 744 DMADirection dir, dma_addr_t access_len) 745 { 746 dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len); 747 } 748 749 static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev, 750 int alloc_hint) 751 { 752 qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev)); 753 } 754 755 extern const VMStateDescription vmstate_pci_device; 756 757 #define VMSTATE_PCI_DEVICE(_field, _state) { \ 758 .name = (stringify(_field)), \ 759 .size = sizeof(PCIDevice), \ 760 .vmsd = &vmstate_pci_device, \ 761 .flags = VMS_STRUCT, \ 762 .offset = vmstate_offset_value(_state, _field, PCIDevice), \ 763 } 764 765 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \ 766 .name = (stringify(_field)), \ 767 .size = sizeof(PCIDevice), \ 768 .vmsd = &vmstate_pci_device, \ 769 .flags = VMS_STRUCT|VMS_POINTER, \ 770 .offset = vmstate_offset_pointer(_state, _field, PCIDevice), \ 771 } 772 773 #endif 774