1 #ifndef QEMU_PCI_H 2 #define QEMU_PCI_H 3 4 #include "qemu-common.h" 5 6 #include "hw/qdev.h" 7 #include "exec/memory.h" 8 #include "sysemu/dma.h" 9 #include "qapi/error.h" 10 11 /* PCI includes legacy ISA access. */ 12 #include "hw/isa/isa.h" 13 14 #include "hw/pci/pcie.h" 15 16 /* PCI bus */ 17 18 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 19 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 20 #define PCI_FUNC(devfn) ((devfn) & 0x07) 21 #define PCI_SLOT_MAX 32 22 #define PCI_FUNC_MAX 8 23 24 /* Class, Vendor and Device IDs from Linux's pci_ids.h */ 25 #include "hw/pci/pci_ids.h" 26 27 /* QEMU-specific Vendor and Device ID definitions */ 28 29 /* IBM (0x1014) */ 30 #define PCI_DEVICE_ID_IBM_440GX 0x027f 31 #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff 32 33 /* Hitachi (0x1054) */ 34 #define PCI_VENDOR_ID_HITACHI 0x1054 35 #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e 36 37 /* Apple (0x106b) */ 38 #define PCI_DEVICE_ID_APPLE_343S1201 0x0010 39 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e 40 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f 41 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022 42 #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f 43 44 /* Realtek (0x10ec) */ 45 #define PCI_DEVICE_ID_REALTEK_8029 0x8029 46 47 /* Xilinx (0x10ee) */ 48 #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300 49 50 /* Marvell (0x11ab) */ 51 #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620 52 53 /* QEMU/Bochs VGA (0x1234) */ 54 #define PCI_VENDOR_ID_QEMU 0x1234 55 #define PCI_DEVICE_ID_QEMU_VGA 0x1111 56 57 /* VMWare (0x15ad) */ 58 #define PCI_VENDOR_ID_VMWARE 0x15ad 59 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 60 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710 61 #define PCI_DEVICE_ID_VMWARE_NET 0x0720 62 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730 63 #define PCI_DEVICE_ID_VMWARE_PVSCSI 0x07C0 64 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729 65 #define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0 66 67 /* Intel (0x8086) */ 68 #define PCI_DEVICE_ID_INTEL_82551IT 0x1209 69 #define PCI_DEVICE_ID_INTEL_82557 0x1229 70 #define PCI_DEVICE_ID_INTEL_82801IR 0x2922 71 72 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */ 73 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 74 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 75 #define PCI_SUBDEVICE_ID_QEMU 0x1100 76 77 #define PCI_DEVICE_ID_VIRTIO_NET 0x1000 78 #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001 79 #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002 80 #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003 81 #define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004 82 #define PCI_DEVICE_ID_VIRTIO_RNG 0x1005 83 #define PCI_DEVICE_ID_VIRTIO_9P 0x1009 84 85 #define PCI_VENDOR_ID_REDHAT 0x1b36 86 #define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001 87 #define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002 88 #define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003 89 #define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004 90 #define PCI_DEVICE_ID_REDHAT_TEST 0x0005 91 #define PCI_DEVICE_ID_REDHAT_SDHCI 0x0007 92 #define PCI_DEVICE_ID_REDHAT_PCIE_HOST 0x0008 93 #define PCI_DEVICE_ID_REDHAT_QXL 0x0100 94 95 #define FMT_PCIBUS PRIx64 96 97 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, 98 uint32_t address, uint32_t data, int len); 99 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev, 100 uint32_t address, int len); 101 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, 102 pcibus_t addr, pcibus_t size, int type); 103 typedef void PCIUnregisterFunc(PCIDevice *pci_dev); 104 105 typedef struct PCIIORegion { 106 pcibus_t addr; /* current PCI mapping address. -1 means not mapped */ 107 #define PCI_BAR_UNMAPPED (~(pcibus_t)0) 108 pcibus_t size; 109 uint8_t type; 110 MemoryRegion *memory; 111 MemoryRegion *address_space; 112 } PCIIORegion; 113 114 #define PCI_ROM_SLOT 6 115 #define PCI_NUM_REGIONS 7 116 117 enum { 118 QEMU_PCI_VGA_MEM, 119 QEMU_PCI_VGA_IO_LO, 120 QEMU_PCI_VGA_IO_HI, 121 QEMU_PCI_VGA_NUM_REGIONS, 122 }; 123 124 #define QEMU_PCI_VGA_MEM_BASE 0xa0000 125 #define QEMU_PCI_VGA_MEM_SIZE 0x20000 126 #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0 127 #define QEMU_PCI_VGA_IO_LO_SIZE 0xc 128 #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0 129 #define QEMU_PCI_VGA_IO_HI_SIZE 0x20 130 131 #include "hw/pci/pci_regs.h" 132 133 /* PCI HEADER_TYPE */ 134 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80 135 136 /* Size of the standard PCI config header */ 137 #define PCI_CONFIG_HEADER_SIZE 0x40 138 /* Size of the standard PCI config space */ 139 #define PCI_CONFIG_SPACE_SIZE 0x100 140 /* Size of the standard PCIe config space: 4KB */ 141 #define PCIE_CONFIG_SPACE_SIZE 0x1000 142 143 #define PCI_NUM_PINS 4 /* A-D */ 144 145 /* Bits in cap_present field. */ 146 enum { 147 QEMU_PCI_CAP_MSI = 0x1, 148 QEMU_PCI_CAP_MSIX = 0x2, 149 QEMU_PCI_CAP_EXPRESS = 0x4, 150 151 /* multifunction capable device */ 152 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3 153 QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR), 154 155 /* command register SERR bit enabled */ 156 #define QEMU_PCI_CAP_SERR_BITNR 4 157 QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR), 158 /* Standard hot plug controller. */ 159 #define QEMU_PCI_SHPC_BITNR 5 160 QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR), 161 #define QEMU_PCI_SLOTID_BITNR 6 162 QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR), 163 /* PCI Express capability - Power Controller Present */ 164 #define QEMU_PCIE_SLTCAP_PCP_BITNR 7 165 QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR), 166 }; 167 168 #define TYPE_PCI_DEVICE "pci-device" 169 #define PCI_DEVICE(obj) \ 170 OBJECT_CHECK(PCIDevice, (obj), TYPE_PCI_DEVICE) 171 #define PCI_DEVICE_CLASS(klass) \ 172 OBJECT_CLASS_CHECK(PCIDeviceClass, (klass), TYPE_PCI_DEVICE) 173 #define PCI_DEVICE_GET_CLASS(obj) \ 174 OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE) 175 176 typedef struct PCIINTxRoute { 177 enum { 178 PCI_INTX_ENABLED, 179 PCI_INTX_INVERTED, 180 PCI_INTX_DISABLED, 181 } mode; 182 int irq; 183 } PCIINTxRoute; 184 185 typedef struct PCIDeviceClass { 186 DeviceClass parent_class; 187 188 void (*realize)(PCIDevice *dev, Error **errp); 189 int (*init)(PCIDevice *dev);/* TODO convert to realize() and remove */ 190 PCIUnregisterFunc *exit; 191 PCIConfigReadFunc *config_read; 192 PCIConfigWriteFunc *config_write; 193 194 uint16_t vendor_id; 195 uint16_t device_id; 196 uint8_t revision; 197 uint16_t class_id; 198 uint16_t subsystem_vendor_id; /* only for header type = 0 */ 199 uint16_t subsystem_id; /* only for header type = 0 */ 200 201 /* 202 * pci-to-pci bridge or normal device. 203 * This doesn't mean pci host switch. 204 * When card bus bridge is supported, this would be enhanced. 205 */ 206 int is_bridge; 207 208 /* pcie stuff */ 209 int is_express; /* is this device pci express? */ 210 211 /* rom bar */ 212 const char *romfile; 213 } PCIDeviceClass; 214 215 typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev); 216 typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector, 217 MSIMessage msg); 218 typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector); 219 typedef void (*MSIVectorPollNotifier)(PCIDevice *dev, 220 unsigned int vector_start, 221 unsigned int vector_end); 222 223 struct PCIDevice { 224 DeviceState qdev; 225 226 /* PCI config space */ 227 uint8_t *config; 228 229 /* Used to enable config checks on load. Note that writable bits are 230 * never checked even if set in cmask. */ 231 uint8_t *cmask; 232 233 /* Used to implement R/W bytes */ 234 uint8_t *wmask; 235 236 /* Used to implement RW1C(Write 1 to Clear) bytes */ 237 uint8_t *w1cmask; 238 239 /* Used to allocate config space for capabilities. */ 240 uint8_t *used; 241 242 /* the following fields are read only */ 243 PCIBus *bus; 244 int32_t devfn; 245 char name[64]; 246 PCIIORegion io_regions[PCI_NUM_REGIONS]; 247 AddressSpace bus_master_as; 248 MemoryRegion bus_master_enable_region; 249 250 /* do not access the following fields */ 251 PCIConfigReadFunc *config_read; 252 PCIConfigWriteFunc *config_write; 253 254 /* Legacy PCI VGA regions */ 255 MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS]; 256 bool has_vga; 257 258 /* Current IRQ levels. Used internally by the generic PCI code. */ 259 uint8_t irq_state; 260 261 /* Capability bits */ 262 uint32_t cap_present; 263 264 /* Offset of MSI-X capability in config space */ 265 uint8_t msix_cap; 266 267 /* MSI-X entries */ 268 int msix_entries_nr; 269 270 /* Space to store MSIX table & pending bit array */ 271 uint8_t *msix_table; 272 uint8_t *msix_pba; 273 /* MemoryRegion container for msix exclusive BAR setup */ 274 MemoryRegion msix_exclusive_bar; 275 /* Memory Regions for MSIX table and pending bit entries. */ 276 MemoryRegion msix_table_mmio; 277 MemoryRegion msix_pba_mmio; 278 /* Reference-count for entries actually in use by driver. */ 279 unsigned *msix_entry_used; 280 /* MSIX function mask set or MSIX disabled */ 281 bool msix_function_masked; 282 /* Version id needed for VMState */ 283 int32_t version_id; 284 285 /* Offset of MSI capability in config space */ 286 uint8_t msi_cap; 287 288 /* PCI Express */ 289 PCIExpressDevice exp; 290 291 /* SHPC */ 292 SHPCDevice *shpc; 293 294 /* Location of option rom */ 295 char *romfile; 296 bool has_rom; 297 MemoryRegion rom; 298 uint32_t rom_bar; 299 300 /* INTx routing notifier */ 301 PCIINTxRoutingNotifier intx_routing_notifier; 302 303 /* MSI-X notifiers */ 304 MSIVectorUseNotifier msix_vector_use_notifier; 305 MSIVectorReleaseNotifier msix_vector_release_notifier; 306 MSIVectorPollNotifier msix_vector_poll_notifier; 307 }; 308 309 void pci_register_bar(PCIDevice *pci_dev, int region_num, 310 uint8_t attr, MemoryRegion *memory); 311 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, 312 MemoryRegion *io_lo, MemoryRegion *io_hi); 313 void pci_unregister_vga(PCIDevice *pci_dev); 314 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num); 315 316 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, 317 uint8_t offset, uint8_t size); 318 int pci_add_capability2(PCIDevice *pdev, uint8_t cap_id, 319 uint8_t offset, uint8_t size, 320 Error **errp); 321 322 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size); 323 324 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id); 325 326 327 uint32_t pci_default_read_config(PCIDevice *d, 328 uint32_t address, int len); 329 void pci_default_write_config(PCIDevice *d, 330 uint32_t address, uint32_t val, int len); 331 void pci_device_save(PCIDevice *s, QEMUFile *f); 332 int pci_device_load(PCIDevice *s, QEMUFile *f); 333 MemoryRegion *pci_address_space(PCIDevice *dev); 334 MemoryRegion *pci_address_space_io(PCIDevice *dev); 335 336 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level); 337 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); 338 typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin); 339 340 #define TYPE_PCI_BUS "PCI" 341 #define PCI_BUS(obj) OBJECT_CHECK(PCIBus, (obj), TYPE_PCI_BUS) 342 #define TYPE_PCIE_BUS "PCIE" 343 344 bool pci_bus_is_express(PCIBus *bus); 345 bool pci_bus_is_root(PCIBus *bus); 346 void pci_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent, 347 const char *name, 348 MemoryRegion *address_space_mem, 349 MemoryRegion *address_space_io, 350 uint8_t devfn_min, const char *typename); 351 PCIBus *pci_bus_new(DeviceState *parent, const char *name, 352 MemoryRegion *address_space_mem, 353 MemoryRegion *address_space_io, 354 uint8_t devfn_min, const char *typename); 355 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 356 void *irq_opaque, int nirq); 357 int pci_bus_get_irq_level(PCIBus *bus, int irq_num); 358 /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */ 359 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin); 360 PCIBus *pci_register_bus(DeviceState *parent, const char *name, 361 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 362 void *irq_opaque, 363 MemoryRegion *address_space_mem, 364 MemoryRegion *address_space_io, 365 uint8_t devfn_min, int nirq, const char *typename); 366 void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn); 367 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin); 368 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new); 369 void pci_bus_fire_intx_routing_notifier(PCIBus *bus); 370 void pci_device_set_intx_routing_notifier(PCIDevice *dev, 371 PCIINTxRoutingNotifier notifier); 372 void pci_device_reset(PCIDevice *dev); 373 374 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus, 375 const char *default_model, 376 const char *default_devaddr); 377 378 PCIDevice *pci_vga_init(PCIBus *bus); 379 380 int pci_bus_num(PCIBus *s); 381 void pci_for_each_device(PCIBus *bus, int bus_num, 382 void (*fn)(PCIBus *bus, PCIDevice *d, void *opaque), 383 void *opaque); 384 void pci_for_each_bus_depth_first(PCIBus *bus, 385 void *(*begin)(PCIBus *bus, void *parent_state), 386 void (*end)(PCIBus *bus, void *state), 387 void *parent_state); 388 389 /* Use this wrapper when specific scan order is not required. */ 390 static inline 391 void pci_for_each_bus(PCIBus *bus, 392 void (*fn)(PCIBus *bus, void *opaque), 393 void *opaque) 394 { 395 pci_for_each_bus_depth_first(bus, NULL, fn, opaque); 396 } 397 398 PCIBus *pci_find_primary_bus(void); 399 PCIBus *pci_device_root_bus(const PCIDevice *d); 400 const char *pci_root_bus_path(PCIDevice *dev); 401 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn); 402 int pci_qdev_find_device(const char *id, PCIDevice **pdev); 403 void pci_bus_get_w64_range(PCIBus *bus, Range *range); 404 405 void pci_device_deassert_intx(PCIDevice *dev); 406 407 typedef AddressSpace *(*PCIIOMMUFunc)(PCIBus *, void *, int); 408 409 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev); 410 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque); 411 412 static inline void 413 pci_set_byte(uint8_t *config, uint8_t val) 414 { 415 *config = val; 416 } 417 418 static inline uint8_t 419 pci_get_byte(const uint8_t *config) 420 { 421 return *config; 422 } 423 424 static inline void 425 pci_set_word(uint8_t *config, uint16_t val) 426 { 427 stw_le_p(config, val); 428 } 429 430 static inline uint16_t 431 pci_get_word(const uint8_t *config) 432 { 433 return lduw_le_p(config); 434 } 435 436 static inline void 437 pci_set_long(uint8_t *config, uint32_t val) 438 { 439 stl_le_p(config, val); 440 } 441 442 static inline uint32_t 443 pci_get_long(const uint8_t *config) 444 { 445 return ldl_le_p(config); 446 } 447 448 static inline void 449 pci_set_quad(uint8_t *config, uint64_t val) 450 { 451 cpu_to_le64w((uint64_t *)config, val); 452 } 453 454 static inline uint64_t 455 pci_get_quad(const uint8_t *config) 456 { 457 return le64_to_cpup((const uint64_t *)config); 458 } 459 460 static inline void 461 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val) 462 { 463 pci_set_word(&pci_config[PCI_VENDOR_ID], val); 464 } 465 466 static inline void 467 pci_config_set_device_id(uint8_t *pci_config, uint16_t val) 468 { 469 pci_set_word(&pci_config[PCI_DEVICE_ID], val); 470 } 471 472 static inline void 473 pci_config_set_revision(uint8_t *pci_config, uint8_t val) 474 { 475 pci_set_byte(&pci_config[PCI_REVISION_ID], val); 476 } 477 478 static inline void 479 pci_config_set_class(uint8_t *pci_config, uint16_t val) 480 { 481 pci_set_word(&pci_config[PCI_CLASS_DEVICE], val); 482 } 483 484 static inline void 485 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val) 486 { 487 pci_set_byte(&pci_config[PCI_CLASS_PROG], val); 488 } 489 490 static inline void 491 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val) 492 { 493 pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val); 494 } 495 496 /* 497 * helper functions to do bit mask operation on configuration space. 498 * Just to set bit, use test-and-set and discard returned value. 499 * Just to clear bit, use test-and-clear and discard returned value. 500 * NOTE: They aren't atomic. 501 */ 502 static inline uint8_t 503 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask) 504 { 505 uint8_t val = pci_get_byte(config); 506 pci_set_byte(config, val & ~mask); 507 return val & mask; 508 } 509 510 static inline uint8_t 511 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask) 512 { 513 uint8_t val = pci_get_byte(config); 514 pci_set_byte(config, val | mask); 515 return val & mask; 516 } 517 518 static inline uint16_t 519 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask) 520 { 521 uint16_t val = pci_get_word(config); 522 pci_set_word(config, val & ~mask); 523 return val & mask; 524 } 525 526 static inline uint16_t 527 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask) 528 { 529 uint16_t val = pci_get_word(config); 530 pci_set_word(config, val | mask); 531 return val & mask; 532 } 533 534 static inline uint32_t 535 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask) 536 { 537 uint32_t val = pci_get_long(config); 538 pci_set_long(config, val & ~mask); 539 return val & mask; 540 } 541 542 static inline uint32_t 543 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask) 544 { 545 uint32_t val = pci_get_long(config); 546 pci_set_long(config, val | mask); 547 return val & mask; 548 } 549 550 static inline uint64_t 551 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask) 552 { 553 uint64_t val = pci_get_quad(config); 554 pci_set_quad(config, val & ~mask); 555 return val & mask; 556 } 557 558 static inline uint64_t 559 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask) 560 { 561 uint64_t val = pci_get_quad(config); 562 pci_set_quad(config, val | mask); 563 return val & mask; 564 } 565 566 /* Access a register specified by a mask */ 567 static inline void 568 pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg) 569 { 570 uint8_t val = pci_get_byte(config); 571 uint8_t rval = reg << ctz32(mask); 572 pci_set_byte(config, (~mask & val) | (mask & rval)); 573 } 574 575 static inline uint8_t 576 pci_get_byte_by_mask(uint8_t *config, uint8_t mask) 577 { 578 uint8_t val = pci_get_byte(config); 579 return (val & mask) >> ctz32(mask); 580 } 581 582 static inline void 583 pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg) 584 { 585 uint16_t val = pci_get_word(config); 586 uint16_t rval = reg << ctz32(mask); 587 pci_set_word(config, (~mask & val) | (mask & rval)); 588 } 589 590 static inline uint16_t 591 pci_get_word_by_mask(uint8_t *config, uint16_t mask) 592 { 593 uint16_t val = pci_get_word(config); 594 return (val & mask) >> ctz32(mask); 595 } 596 597 static inline void 598 pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg) 599 { 600 uint32_t val = pci_get_long(config); 601 uint32_t rval = reg << ctz32(mask); 602 pci_set_long(config, (~mask & val) | (mask & rval)); 603 } 604 605 static inline uint32_t 606 pci_get_long_by_mask(uint8_t *config, uint32_t mask) 607 { 608 uint32_t val = pci_get_long(config); 609 return (val & mask) >> ctz32(mask); 610 } 611 612 static inline void 613 pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg) 614 { 615 uint64_t val = pci_get_quad(config); 616 uint64_t rval = reg << ctz32(mask); 617 pci_set_quad(config, (~mask & val) | (mask & rval)); 618 } 619 620 static inline uint64_t 621 pci_get_quad_by_mask(uint8_t *config, uint64_t mask) 622 { 623 uint64_t val = pci_get_quad(config); 624 return (val & mask) >> ctz32(mask); 625 } 626 627 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction, 628 const char *name); 629 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, 630 bool multifunction, 631 const char *name); 632 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name); 633 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name); 634 635 qemu_irq pci_allocate_irq(PCIDevice *pci_dev); 636 void pci_set_irq(PCIDevice *pci_dev, int level); 637 638 static inline void pci_irq_assert(PCIDevice *pci_dev) 639 { 640 pci_set_irq(pci_dev, 1); 641 } 642 643 static inline void pci_irq_deassert(PCIDevice *pci_dev) 644 { 645 pci_set_irq(pci_dev, 0); 646 } 647 648 /* 649 * FIXME: PCI does not work this way. 650 * All the callers to this method should be fixed. 651 */ 652 static inline void pci_irq_pulse(PCIDevice *pci_dev) 653 { 654 pci_irq_assert(pci_dev); 655 pci_irq_deassert(pci_dev); 656 } 657 658 static inline int pci_is_express(const PCIDevice *d) 659 { 660 return d->cap_present & QEMU_PCI_CAP_EXPRESS; 661 } 662 663 static inline uint32_t pci_config_size(const PCIDevice *d) 664 { 665 return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE; 666 } 667 668 /* DMA access functions */ 669 static inline AddressSpace *pci_get_address_space(PCIDevice *dev) 670 { 671 return &dev->bus_master_as; 672 } 673 674 static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr, 675 void *buf, dma_addr_t len, DMADirection dir) 676 { 677 dma_memory_rw(pci_get_address_space(dev), addr, buf, len, dir); 678 return 0; 679 } 680 681 static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr, 682 void *buf, dma_addr_t len) 683 { 684 return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE); 685 } 686 687 static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr, 688 const void *buf, dma_addr_t len) 689 { 690 return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE); 691 } 692 693 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \ 694 static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev, \ 695 dma_addr_t addr) \ 696 { \ 697 return ld##_l##_dma(pci_get_address_space(dev), addr); \ 698 } \ 699 static inline void st##_s##_pci_dma(PCIDevice *dev, \ 700 dma_addr_t addr, uint##_bits##_t val) \ 701 { \ 702 st##_s##_dma(pci_get_address_space(dev), addr, val); \ 703 } 704 705 PCI_DMA_DEFINE_LDST(ub, b, 8); 706 PCI_DMA_DEFINE_LDST(uw_le, w_le, 16) 707 PCI_DMA_DEFINE_LDST(l_le, l_le, 32); 708 PCI_DMA_DEFINE_LDST(q_le, q_le, 64); 709 PCI_DMA_DEFINE_LDST(uw_be, w_be, 16) 710 PCI_DMA_DEFINE_LDST(l_be, l_be, 32); 711 PCI_DMA_DEFINE_LDST(q_be, q_be, 64); 712 713 #undef PCI_DMA_DEFINE_LDST 714 715 static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr, 716 dma_addr_t *plen, DMADirection dir) 717 { 718 void *buf; 719 720 buf = dma_memory_map(pci_get_address_space(dev), addr, plen, dir); 721 return buf; 722 } 723 724 static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len, 725 DMADirection dir, dma_addr_t access_len) 726 { 727 dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len); 728 } 729 730 static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev, 731 int alloc_hint) 732 { 733 qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev)); 734 } 735 736 extern const VMStateDescription vmstate_pci_device; 737 738 #define VMSTATE_PCI_DEVICE(_field, _state) { \ 739 .name = (stringify(_field)), \ 740 .size = sizeof(PCIDevice), \ 741 .vmsd = &vmstate_pci_device, \ 742 .flags = VMS_STRUCT, \ 743 .offset = vmstate_offset_value(_state, _field, PCIDevice), \ 744 } 745 746 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \ 747 .name = (stringify(_field)), \ 748 .size = sizeof(PCIDevice), \ 749 .vmsd = &vmstate_pci_device, \ 750 .flags = VMS_STRUCT|VMS_POINTER, \ 751 .offset = vmstate_offset_pointer(_state, _field, PCIDevice), \ 752 } 753 754 #endif 755