1 #ifndef QEMU_PCI_H 2 #define QEMU_PCI_H 3 4 #include "hw/qdev.h" 5 #include "exec/memory.h" 6 #include "sysemu/dma.h" 7 8 /* PCI includes legacy ISA access. */ 9 #include "hw/isa/isa.h" 10 11 #include "hw/pci/pcie.h" 12 13 /* PCI bus */ 14 15 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 16 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 17 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 18 #define PCI_FUNC(devfn) ((devfn) & 0x07) 19 #define PCI_BUILD_BDF(bus, devfn) ((bus << 8) | (devfn)) 20 #define PCI_BUS_MAX 256 21 #define PCI_DEVFN_MAX 256 22 #define PCI_SLOT_MAX 32 23 #define PCI_FUNC_MAX 8 24 25 /* Class, Vendor and Device IDs from Linux's pci_ids.h */ 26 #include "hw/pci/pci_ids.h" 27 28 /* QEMU-specific Vendor and Device ID definitions */ 29 30 /* IBM (0x1014) */ 31 #define PCI_DEVICE_ID_IBM_440GX 0x027f 32 #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff 33 34 /* Hitachi (0x1054) */ 35 #define PCI_VENDOR_ID_HITACHI 0x1054 36 #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e 37 38 /* Apple (0x106b) */ 39 #define PCI_DEVICE_ID_APPLE_343S1201 0x0010 40 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e 41 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f 42 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022 43 #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f 44 45 /* Realtek (0x10ec) */ 46 #define PCI_DEVICE_ID_REALTEK_8029 0x8029 47 48 /* Xilinx (0x10ee) */ 49 #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300 50 51 /* Marvell (0x11ab) */ 52 #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620 53 54 /* QEMU/Bochs VGA (0x1234) */ 55 #define PCI_VENDOR_ID_QEMU 0x1234 56 #define PCI_DEVICE_ID_QEMU_VGA 0x1111 57 58 /* VMWare (0x15ad) */ 59 #define PCI_VENDOR_ID_VMWARE 0x15ad 60 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 61 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710 62 #define PCI_DEVICE_ID_VMWARE_NET 0x0720 63 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730 64 #define PCI_DEVICE_ID_VMWARE_PVSCSI 0x07C0 65 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729 66 #define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0 67 68 /* Intel (0x8086) */ 69 #define PCI_DEVICE_ID_INTEL_82551IT 0x1209 70 #define PCI_DEVICE_ID_INTEL_82557 0x1229 71 #define PCI_DEVICE_ID_INTEL_82801IR 0x2922 72 73 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */ 74 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 75 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 76 #define PCI_SUBDEVICE_ID_QEMU 0x1100 77 78 #define PCI_DEVICE_ID_VIRTIO_NET 0x1000 79 #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001 80 #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002 81 #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003 82 #define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004 83 #define PCI_DEVICE_ID_VIRTIO_RNG 0x1005 84 #define PCI_DEVICE_ID_VIRTIO_9P 0x1009 85 #define PCI_DEVICE_ID_VIRTIO_VSOCK 0x1012 86 87 #define PCI_VENDOR_ID_REDHAT 0x1b36 88 #define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001 89 #define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002 90 #define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003 91 #define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004 92 #define PCI_DEVICE_ID_REDHAT_TEST 0x0005 93 #define PCI_DEVICE_ID_REDHAT_ROCKER 0x0006 94 #define PCI_DEVICE_ID_REDHAT_SDHCI 0x0007 95 #define PCI_DEVICE_ID_REDHAT_PCIE_HOST 0x0008 96 #define PCI_DEVICE_ID_REDHAT_PXB 0x0009 97 #define PCI_DEVICE_ID_REDHAT_BRIDGE_SEAT 0x000a 98 #define PCI_DEVICE_ID_REDHAT_PXB_PCIE 0x000b 99 #define PCI_DEVICE_ID_REDHAT_QXL 0x0100 100 101 #define FMT_PCIBUS PRIx64 102 103 typedef uint64_t pcibus_t; 104 105 struct PCIHostDeviceAddress { 106 unsigned int domain; 107 unsigned int bus; 108 unsigned int slot; 109 unsigned int function; 110 }; 111 112 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, 113 uint32_t address, uint32_t data, int len); 114 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev, 115 uint32_t address, int len); 116 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, 117 pcibus_t addr, pcibus_t size, int type); 118 typedef void PCIUnregisterFunc(PCIDevice *pci_dev); 119 120 typedef struct PCIIORegion { 121 pcibus_t addr; /* current PCI mapping address. -1 means not mapped */ 122 #define PCI_BAR_UNMAPPED (~(pcibus_t)0) 123 pcibus_t size; 124 uint8_t type; 125 MemoryRegion *memory; 126 MemoryRegion *address_space; 127 } PCIIORegion; 128 129 #define PCI_ROM_SLOT 6 130 #define PCI_NUM_REGIONS 7 131 132 enum { 133 QEMU_PCI_VGA_MEM, 134 QEMU_PCI_VGA_IO_LO, 135 QEMU_PCI_VGA_IO_HI, 136 QEMU_PCI_VGA_NUM_REGIONS, 137 }; 138 139 #define QEMU_PCI_VGA_MEM_BASE 0xa0000 140 #define QEMU_PCI_VGA_MEM_SIZE 0x20000 141 #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0 142 #define QEMU_PCI_VGA_IO_LO_SIZE 0xc 143 #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0 144 #define QEMU_PCI_VGA_IO_HI_SIZE 0x20 145 146 #include "hw/pci/pci_regs.h" 147 148 /* PCI HEADER_TYPE */ 149 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80 150 151 /* Size of the standard PCI config header */ 152 #define PCI_CONFIG_HEADER_SIZE 0x40 153 /* Size of the standard PCI config space */ 154 #define PCI_CONFIG_SPACE_SIZE 0x100 155 /* Size of the standard PCIe config space: 4KB */ 156 #define PCIE_CONFIG_SPACE_SIZE 0x1000 157 158 #define PCI_NUM_PINS 4 /* A-D */ 159 160 /* Bits in cap_present field. */ 161 enum { 162 QEMU_PCI_CAP_MSI = 0x1, 163 QEMU_PCI_CAP_MSIX = 0x2, 164 QEMU_PCI_CAP_EXPRESS = 0x4, 165 166 /* multifunction capable device */ 167 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3 168 QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR), 169 170 /* command register SERR bit enabled */ 171 #define QEMU_PCI_CAP_SERR_BITNR 4 172 QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR), 173 /* Standard hot plug controller. */ 174 #define QEMU_PCI_SHPC_BITNR 5 175 QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR), 176 #define QEMU_PCI_SLOTID_BITNR 6 177 QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR), 178 /* PCI Express capability - Power Controller Present */ 179 #define QEMU_PCIE_SLTCAP_PCP_BITNR 7 180 QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR), 181 /* Link active status in endpoint capability is always set */ 182 #define QEMU_PCIE_LNKSTA_DLLLA_BITNR 8 183 QEMU_PCIE_LNKSTA_DLLLA = (1 << QEMU_PCIE_LNKSTA_DLLLA_BITNR), 184 }; 185 186 #define TYPE_PCI_DEVICE "pci-device" 187 #define PCI_DEVICE(obj) \ 188 OBJECT_CHECK(PCIDevice, (obj), TYPE_PCI_DEVICE) 189 #define PCI_DEVICE_CLASS(klass) \ 190 OBJECT_CLASS_CHECK(PCIDeviceClass, (klass), TYPE_PCI_DEVICE) 191 #define PCI_DEVICE_GET_CLASS(obj) \ 192 OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE) 193 194 typedef struct PCIINTxRoute { 195 enum { 196 PCI_INTX_ENABLED, 197 PCI_INTX_INVERTED, 198 PCI_INTX_DISABLED, 199 } mode; 200 int irq; 201 } PCIINTxRoute; 202 203 typedef struct PCIDeviceClass { 204 DeviceClass parent_class; 205 206 void (*realize)(PCIDevice *dev, Error **errp); 207 int (*init)(PCIDevice *dev);/* TODO convert to realize() and remove */ 208 PCIUnregisterFunc *exit; 209 PCIConfigReadFunc *config_read; 210 PCIConfigWriteFunc *config_write; 211 212 uint16_t vendor_id; 213 uint16_t device_id; 214 uint8_t revision; 215 uint16_t class_id; 216 uint16_t subsystem_vendor_id; /* only for header type = 0 */ 217 uint16_t subsystem_id; /* only for header type = 0 */ 218 219 /* 220 * pci-to-pci bridge or normal device. 221 * This doesn't mean pci host switch. 222 * When card bus bridge is supported, this would be enhanced. 223 */ 224 int is_bridge; 225 226 /* pcie stuff */ 227 int is_express; /* is this device pci express? */ 228 229 /* rom bar */ 230 const char *romfile; 231 } PCIDeviceClass; 232 233 typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev); 234 typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector, 235 MSIMessage msg); 236 typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector); 237 typedef void (*MSIVectorPollNotifier)(PCIDevice *dev, 238 unsigned int vector_start, 239 unsigned int vector_end); 240 241 enum PCIReqIDType { 242 PCI_REQ_ID_INVALID = 0, 243 PCI_REQ_ID_BDF, 244 PCI_REQ_ID_SECONDARY_BUS, 245 PCI_REQ_ID_MAX, 246 }; 247 typedef enum PCIReqIDType PCIReqIDType; 248 249 struct PCIReqIDCache { 250 PCIDevice *dev; 251 PCIReqIDType type; 252 }; 253 typedef struct PCIReqIDCache PCIReqIDCache; 254 255 struct PCIDevice { 256 DeviceState qdev; 257 258 /* PCI config space */ 259 uint8_t *config; 260 261 /* Used to enable config checks on load. Note that writable bits are 262 * never checked even if set in cmask. */ 263 uint8_t *cmask; 264 265 /* Used to implement R/W bytes */ 266 uint8_t *wmask; 267 268 /* Used to implement RW1C(Write 1 to Clear) bytes */ 269 uint8_t *w1cmask; 270 271 /* Used to allocate config space for capabilities. */ 272 uint8_t *used; 273 274 /* the following fields are read only */ 275 PCIBus *bus; 276 int32_t devfn; 277 /* Cached device to fetch requester ID from, to avoid the PCI 278 * tree walking every time we invoke PCI request (e.g., 279 * MSI). For conventional PCI root complex, this field is 280 * meaningless. */ 281 PCIReqIDCache requester_id_cache; 282 char name[64]; 283 PCIIORegion io_regions[PCI_NUM_REGIONS]; 284 AddressSpace bus_master_as; 285 MemoryRegion bus_master_enable_region; 286 287 /* do not access the following fields */ 288 PCIConfigReadFunc *config_read; 289 PCIConfigWriteFunc *config_write; 290 291 /* Legacy PCI VGA regions */ 292 MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS]; 293 bool has_vga; 294 295 /* Current IRQ levels. Used internally by the generic PCI code. */ 296 uint8_t irq_state; 297 298 /* Capability bits */ 299 uint32_t cap_present; 300 301 /* Offset of MSI-X capability in config space */ 302 uint8_t msix_cap; 303 304 /* MSI-X entries */ 305 int msix_entries_nr; 306 307 /* Space to store MSIX table & pending bit array */ 308 uint8_t *msix_table; 309 uint8_t *msix_pba; 310 /* MemoryRegion container for msix exclusive BAR setup */ 311 MemoryRegion msix_exclusive_bar; 312 /* Memory Regions for MSIX table and pending bit entries. */ 313 MemoryRegion msix_table_mmio; 314 MemoryRegion msix_pba_mmio; 315 /* Reference-count for entries actually in use by driver. */ 316 unsigned *msix_entry_used; 317 /* MSIX function mask set or MSIX disabled */ 318 bool msix_function_masked; 319 /* Version id needed for VMState */ 320 int32_t version_id; 321 322 /* Offset of MSI capability in config space */ 323 uint8_t msi_cap; 324 325 /* PCI Express */ 326 PCIExpressDevice exp; 327 328 /* SHPC */ 329 SHPCDevice *shpc; 330 331 /* Location of option rom */ 332 char *romfile; 333 bool has_rom; 334 MemoryRegion rom; 335 uint32_t rom_bar; 336 337 /* INTx routing notifier */ 338 PCIINTxRoutingNotifier intx_routing_notifier; 339 340 /* MSI-X notifiers */ 341 MSIVectorUseNotifier msix_vector_use_notifier; 342 MSIVectorReleaseNotifier msix_vector_release_notifier; 343 MSIVectorPollNotifier msix_vector_poll_notifier; 344 }; 345 346 void pci_register_bar(PCIDevice *pci_dev, int region_num, 347 uint8_t attr, MemoryRegion *memory); 348 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, 349 MemoryRegion *io_lo, MemoryRegion *io_hi); 350 void pci_unregister_vga(PCIDevice *pci_dev); 351 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num); 352 353 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, 354 uint8_t offset, uint8_t size); 355 int pci_add_capability2(PCIDevice *pdev, uint8_t cap_id, 356 uint8_t offset, uint8_t size, 357 Error **errp); 358 359 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size); 360 361 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id); 362 363 364 uint32_t pci_default_read_config(PCIDevice *d, 365 uint32_t address, int len); 366 void pci_default_write_config(PCIDevice *d, 367 uint32_t address, uint32_t val, int len); 368 void pci_device_save(PCIDevice *s, QEMUFile *f); 369 int pci_device_load(PCIDevice *s, QEMUFile *f); 370 MemoryRegion *pci_address_space(PCIDevice *dev); 371 MemoryRegion *pci_address_space_io(PCIDevice *dev); 372 373 /* 374 * Should not normally be used by devices. For use by sPAPR target 375 * where QEMU emulates firmware. 376 */ 377 int pci_bar(PCIDevice *d, int reg); 378 379 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level); 380 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); 381 typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin); 382 383 #define TYPE_PCI_BUS "PCI" 384 #define PCI_BUS(obj) OBJECT_CHECK(PCIBus, (obj), TYPE_PCI_BUS) 385 #define PCI_BUS_CLASS(klass) OBJECT_CLASS_CHECK(PCIBusClass, (klass), TYPE_PCI_BUS) 386 #define PCI_BUS_GET_CLASS(obj) OBJECT_GET_CLASS(PCIBusClass, (obj), TYPE_PCI_BUS) 387 #define TYPE_PCIE_BUS "PCIE" 388 389 bool pci_bus_is_express(PCIBus *bus); 390 bool pci_bus_is_root(PCIBus *bus); 391 void pci_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent, 392 const char *name, 393 MemoryRegion *address_space_mem, 394 MemoryRegion *address_space_io, 395 uint8_t devfn_min, const char *typename); 396 PCIBus *pci_bus_new(DeviceState *parent, const char *name, 397 MemoryRegion *address_space_mem, 398 MemoryRegion *address_space_io, 399 uint8_t devfn_min, const char *typename); 400 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 401 void *irq_opaque, int nirq); 402 int pci_bus_get_irq_level(PCIBus *bus, int irq_num); 403 /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */ 404 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin); 405 PCIBus *pci_register_bus(DeviceState *parent, const char *name, 406 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 407 void *irq_opaque, 408 MemoryRegion *address_space_mem, 409 MemoryRegion *address_space_io, 410 uint8_t devfn_min, int nirq, const char *typename); 411 void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn); 412 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin); 413 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new); 414 void pci_bus_fire_intx_routing_notifier(PCIBus *bus); 415 void pci_device_set_intx_routing_notifier(PCIDevice *dev, 416 PCIINTxRoutingNotifier notifier); 417 void pci_device_reset(PCIDevice *dev); 418 419 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus, 420 const char *default_model, 421 const char *default_devaddr); 422 423 PCIDevice *pci_vga_init(PCIBus *bus); 424 425 int pci_bus_num(PCIBus *s); 426 int pci_bus_numa_node(PCIBus *bus); 427 void pci_for_each_device(PCIBus *bus, int bus_num, 428 void (*fn)(PCIBus *bus, PCIDevice *d, void *opaque), 429 void *opaque); 430 void pci_for_each_bus_depth_first(PCIBus *bus, 431 void *(*begin)(PCIBus *bus, void *parent_state), 432 void (*end)(PCIBus *bus, void *state), 433 void *parent_state); 434 PCIDevice *pci_get_function_0(PCIDevice *pci_dev); 435 436 /* Use this wrapper when specific scan order is not required. */ 437 static inline 438 void pci_for_each_bus(PCIBus *bus, 439 void (*fn)(PCIBus *bus, void *opaque), 440 void *opaque) 441 { 442 pci_for_each_bus_depth_first(bus, NULL, fn, opaque); 443 } 444 445 PCIBus *pci_find_primary_bus(void); 446 PCIBus *pci_device_root_bus(const PCIDevice *d); 447 const char *pci_root_bus_path(PCIDevice *dev); 448 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn); 449 int pci_qdev_find_device(const char *id, PCIDevice **pdev); 450 void pci_bus_get_w64_range(PCIBus *bus, Range *range); 451 452 void pci_device_deassert_intx(PCIDevice *dev); 453 454 typedef AddressSpace *(*PCIIOMMUFunc)(PCIBus *, void *, int); 455 456 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev); 457 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque); 458 459 static inline void 460 pci_set_byte(uint8_t *config, uint8_t val) 461 { 462 *config = val; 463 } 464 465 static inline uint8_t 466 pci_get_byte(const uint8_t *config) 467 { 468 return *config; 469 } 470 471 static inline void 472 pci_set_word(uint8_t *config, uint16_t val) 473 { 474 stw_le_p(config, val); 475 } 476 477 static inline uint16_t 478 pci_get_word(const uint8_t *config) 479 { 480 return lduw_le_p(config); 481 } 482 483 static inline void 484 pci_set_long(uint8_t *config, uint32_t val) 485 { 486 stl_le_p(config, val); 487 } 488 489 static inline uint32_t 490 pci_get_long(const uint8_t *config) 491 { 492 return ldl_le_p(config); 493 } 494 495 /* 496 * PCI capabilities and/or their fields 497 * are generally DWORD aligned only so 498 * mechanism used by pci_set/get_quad() 499 * must be tolerant to unaligned pointers 500 * 501 */ 502 static inline void 503 pci_set_quad(uint8_t *config, uint64_t val) 504 { 505 stq_le_p(config, val); 506 } 507 508 static inline uint64_t 509 pci_get_quad(const uint8_t *config) 510 { 511 return ldq_le_p(config); 512 } 513 514 static inline void 515 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val) 516 { 517 pci_set_word(&pci_config[PCI_VENDOR_ID], val); 518 } 519 520 static inline void 521 pci_config_set_device_id(uint8_t *pci_config, uint16_t val) 522 { 523 pci_set_word(&pci_config[PCI_DEVICE_ID], val); 524 } 525 526 static inline void 527 pci_config_set_revision(uint8_t *pci_config, uint8_t val) 528 { 529 pci_set_byte(&pci_config[PCI_REVISION_ID], val); 530 } 531 532 static inline void 533 pci_config_set_class(uint8_t *pci_config, uint16_t val) 534 { 535 pci_set_word(&pci_config[PCI_CLASS_DEVICE], val); 536 } 537 538 static inline void 539 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val) 540 { 541 pci_set_byte(&pci_config[PCI_CLASS_PROG], val); 542 } 543 544 static inline void 545 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val) 546 { 547 pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val); 548 } 549 550 /* 551 * helper functions to do bit mask operation on configuration space. 552 * Just to set bit, use test-and-set and discard returned value. 553 * Just to clear bit, use test-and-clear and discard returned value. 554 * NOTE: They aren't atomic. 555 */ 556 static inline uint8_t 557 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask) 558 { 559 uint8_t val = pci_get_byte(config); 560 pci_set_byte(config, val & ~mask); 561 return val & mask; 562 } 563 564 static inline uint8_t 565 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask) 566 { 567 uint8_t val = pci_get_byte(config); 568 pci_set_byte(config, val | mask); 569 return val & mask; 570 } 571 572 static inline uint16_t 573 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask) 574 { 575 uint16_t val = pci_get_word(config); 576 pci_set_word(config, val & ~mask); 577 return val & mask; 578 } 579 580 static inline uint16_t 581 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask) 582 { 583 uint16_t val = pci_get_word(config); 584 pci_set_word(config, val | mask); 585 return val & mask; 586 } 587 588 static inline uint32_t 589 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask) 590 { 591 uint32_t val = pci_get_long(config); 592 pci_set_long(config, val & ~mask); 593 return val & mask; 594 } 595 596 static inline uint32_t 597 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask) 598 { 599 uint32_t val = pci_get_long(config); 600 pci_set_long(config, val | mask); 601 return val & mask; 602 } 603 604 static inline uint64_t 605 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask) 606 { 607 uint64_t val = pci_get_quad(config); 608 pci_set_quad(config, val & ~mask); 609 return val & mask; 610 } 611 612 static inline uint64_t 613 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask) 614 { 615 uint64_t val = pci_get_quad(config); 616 pci_set_quad(config, val | mask); 617 return val & mask; 618 } 619 620 /* Access a register specified by a mask */ 621 static inline void 622 pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg) 623 { 624 uint8_t val = pci_get_byte(config); 625 uint8_t rval = reg << ctz32(mask); 626 pci_set_byte(config, (~mask & val) | (mask & rval)); 627 } 628 629 static inline uint8_t 630 pci_get_byte_by_mask(uint8_t *config, uint8_t mask) 631 { 632 uint8_t val = pci_get_byte(config); 633 return (val & mask) >> ctz32(mask); 634 } 635 636 static inline void 637 pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg) 638 { 639 uint16_t val = pci_get_word(config); 640 uint16_t rval = reg << ctz32(mask); 641 pci_set_word(config, (~mask & val) | (mask & rval)); 642 } 643 644 static inline uint16_t 645 pci_get_word_by_mask(uint8_t *config, uint16_t mask) 646 { 647 uint16_t val = pci_get_word(config); 648 return (val & mask) >> ctz32(mask); 649 } 650 651 static inline void 652 pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg) 653 { 654 uint32_t val = pci_get_long(config); 655 uint32_t rval = reg << ctz32(mask); 656 pci_set_long(config, (~mask & val) | (mask & rval)); 657 } 658 659 static inline uint32_t 660 pci_get_long_by_mask(uint8_t *config, uint32_t mask) 661 { 662 uint32_t val = pci_get_long(config); 663 return (val & mask) >> ctz32(mask); 664 } 665 666 static inline void 667 pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg) 668 { 669 uint64_t val = pci_get_quad(config); 670 uint64_t rval = reg << ctz32(mask); 671 pci_set_quad(config, (~mask & val) | (mask & rval)); 672 } 673 674 static inline uint64_t 675 pci_get_quad_by_mask(uint8_t *config, uint64_t mask) 676 { 677 uint64_t val = pci_get_quad(config); 678 return (val & mask) >> ctz32(mask); 679 } 680 681 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction, 682 const char *name); 683 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, 684 bool multifunction, 685 const char *name); 686 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name); 687 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name); 688 689 qemu_irq pci_allocate_irq(PCIDevice *pci_dev); 690 void pci_set_irq(PCIDevice *pci_dev, int level); 691 692 static inline void pci_irq_assert(PCIDevice *pci_dev) 693 { 694 pci_set_irq(pci_dev, 1); 695 } 696 697 static inline void pci_irq_deassert(PCIDevice *pci_dev) 698 { 699 pci_set_irq(pci_dev, 0); 700 } 701 702 /* 703 * FIXME: PCI does not work this way. 704 * All the callers to this method should be fixed. 705 */ 706 static inline void pci_irq_pulse(PCIDevice *pci_dev) 707 { 708 pci_irq_assert(pci_dev); 709 pci_irq_deassert(pci_dev); 710 } 711 712 static inline int pci_is_express(const PCIDevice *d) 713 { 714 return d->cap_present & QEMU_PCI_CAP_EXPRESS; 715 } 716 717 static inline uint32_t pci_config_size(const PCIDevice *d) 718 { 719 return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE; 720 } 721 722 static inline uint16_t pci_get_bdf(PCIDevice *dev) 723 { 724 return PCI_BUILD_BDF(pci_bus_num(dev->bus), dev->devfn); 725 } 726 727 uint16_t pci_requester_id(PCIDevice *dev); 728 729 /* DMA access functions */ 730 static inline AddressSpace *pci_get_address_space(PCIDevice *dev) 731 { 732 return &dev->bus_master_as; 733 } 734 735 static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr, 736 void *buf, dma_addr_t len, DMADirection dir) 737 { 738 dma_memory_rw(pci_get_address_space(dev), addr, buf, len, dir); 739 return 0; 740 } 741 742 static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr, 743 void *buf, dma_addr_t len) 744 { 745 return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE); 746 } 747 748 static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr, 749 const void *buf, dma_addr_t len) 750 { 751 return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE); 752 } 753 754 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \ 755 static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev, \ 756 dma_addr_t addr) \ 757 { \ 758 return ld##_l##_dma(pci_get_address_space(dev), addr); \ 759 } \ 760 static inline void st##_s##_pci_dma(PCIDevice *dev, \ 761 dma_addr_t addr, uint##_bits##_t val) \ 762 { \ 763 st##_s##_dma(pci_get_address_space(dev), addr, val); \ 764 } 765 766 PCI_DMA_DEFINE_LDST(ub, b, 8); 767 PCI_DMA_DEFINE_LDST(uw_le, w_le, 16) 768 PCI_DMA_DEFINE_LDST(l_le, l_le, 32); 769 PCI_DMA_DEFINE_LDST(q_le, q_le, 64); 770 PCI_DMA_DEFINE_LDST(uw_be, w_be, 16) 771 PCI_DMA_DEFINE_LDST(l_be, l_be, 32); 772 PCI_DMA_DEFINE_LDST(q_be, q_be, 64); 773 774 #undef PCI_DMA_DEFINE_LDST 775 776 static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr, 777 dma_addr_t *plen, DMADirection dir) 778 { 779 void *buf; 780 781 buf = dma_memory_map(pci_get_address_space(dev), addr, plen, dir); 782 return buf; 783 } 784 785 static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len, 786 DMADirection dir, dma_addr_t access_len) 787 { 788 dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len); 789 } 790 791 static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev, 792 int alloc_hint) 793 { 794 qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev)); 795 } 796 797 extern const VMStateDescription vmstate_pci_device; 798 799 #define VMSTATE_PCI_DEVICE(_field, _state) { \ 800 .name = (stringify(_field)), \ 801 .size = sizeof(PCIDevice), \ 802 .vmsd = &vmstate_pci_device, \ 803 .flags = VMS_STRUCT, \ 804 .offset = vmstate_offset_value(_state, _field, PCIDevice), \ 805 } 806 807 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \ 808 .name = (stringify(_field)), \ 809 .size = sizeof(PCIDevice), \ 810 .vmsd = &vmstate_pci_device, \ 811 .flags = VMS_STRUCT|VMS_POINTER, \ 812 .offset = vmstate_offset_pointer(_state, _field, PCIDevice), \ 813 } 814 815 MSIMessage pci_get_msi_message(PCIDevice *dev, int vector); 816 817 #endif 818