1 #ifndef QEMU_PCI_H 2 #define QEMU_PCI_H 3 4 #include "exec/memory.h" 5 #include "sysemu/dma.h" 6 #include "sysemu/host_iommu_device.h" 7 8 /* PCI includes legacy ISA access. */ 9 #include "hw/isa/isa.h" 10 11 extern bool pci_available; 12 13 /* PCI bus */ 14 15 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 16 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 17 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 18 #define PCI_FUNC(devfn) ((devfn) & 0x07) 19 #define PCI_BUILD_BDF(bus, devfn) (((bus) << 8) | (devfn)) 20 #define PCI_BDF_TO_DEVFN(x) ((x) & 0xff) 21 #define PCI_BUS_MAX 256 22 #define PCI_DEVFN_MAX 256 23 #define PCI_SLOT_MAX 32 24 #define PCI_FUNC_MAX 8 25 26 /* Class, Vendor and Device IDs from Linux's pci_ids.h */ 27 #include "hw/pci/pci_ids.h" 28 29 /* QEMU-specific Vendor and Device ID definitions */ 30 31 /* IBM (0x1014) */ 32 #define PCI_DEVICE_ID_IBM_440GX 0x027f 33 #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff 34 35 /* Hitachi (0x1054) */ 36 #define PCI_VENDOR_ID_HITACHI 0x1054 37 #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e 38 39 /* Apple (0x106b) */ 40 #define PCI_DEVICE_ID_APPLE_343S1201 0x0010 41 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e 42 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f 43 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022 44 #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f 45 46 /* Realtek (0x10ec) */ 47 #define PCI_DEVICE_ID_REALTEK_8029 0x8029 48 49 /* Xilinx (0x10ee) */ 50 #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300 51 52 /* Marvell (0x11ab) */ 53 #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620 54 55 /* QEMU/Bochs VGA (0x1234) */ 56 #define PCI_VENDOR_ID_QEMU 0x1234 57 #define PCI_DEVICE_ID_QEMU_VGA 0x1111 58 #define PCI_DEVICE_ID_QEMU_IPMI 0x1112 59 60 /* VMWare (0x15ad) */ 61 #define PCI_VENDOR_ID_VMWARE 0x15ad 62 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 63 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710 64 #define PCI_DEVICE_ID_VMWARE_NET 0x0720 65 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730 66 #define PCI_DEVICE_ID_VMWARE_PVSCSI 0x07C0 67 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729 68 #define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0 69 70 /* Intel (0x8086) */ 71 #define PCI_DEVICE_ID_INTEL_82551IT 0x1209 72 #define PCI_DEVICE_ID_INTEL_82557 0x1229 73 #define PCI_DEVICE_ID_INTEL_82801IR 0x2922 74 75 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */ 76 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 77 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 78 #define PCI_SUBDEVICE_ID_QEMU 0x1100 79 80 /* legacy virtio-pci devices */ 81 #define PCI_DEVICE_ID_VIRTIO_NET 0x1000 82 #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001 83 #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002 84 #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003 85 #define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004 86 #define PCI_DEVICE_ID_VIRTIO_RNG 0x1005 87 #define PCI_DEVICE_ID_VIRTIO_9P 0x1009 88 #define PCI_DEVICE_ID_VIRTIO_VSOCK 0x1012 89 90 /* 91 * modern virtio-pci devices get their id assigned automatically, 92 * there is no need to add #defines here. It gets calculated as 93 * 94 * PCI_DEVICE_ID = PCI_DEVICE_ID_VIRTIO_10_BASE + 95 * virtio_bus_get_vdev_id(bus) 96 */ 97 #define PCI_DEVICE_ID_VIRTIO_10_BASE 0x1040 98 99 #define PCI_VENDOR_ID_REDHAT 0x1b36 100 #define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001 101 #define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002 102 #define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003 103 #define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004 104 #define PCI_DEVICE_ID_REDHAT_TEST 0x0005 105 #define PCI_DEVICE_ID_REDHAT_ROCKER 0x0006 106 #define PCI_DEVICE_ID_REDHAT_SDHCI 0x0007 107 #define PCI_DEVICE_ID_REDHAT_PCIE_HOST 0x0008 108 #define PCI_DEVICE_ID_REDHAT_PXB 0x0009 109 #define PCI_DEVICE_ID_REDHAT_BRIDGE_SEAT 0x000a 110 #define PCI_DEVICE_ID_REDHAT_PXB_PCIE 0x000b 111 #define PCI_DEVICE_ID_REDHAT_PCIE_RP 0x000c 112 #define PCI_DEVICE_ID_REDHAT_XHCI 0x000d 113 #define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000e 114 #define PCI_DEVICE_ID_REDHAT_MDPY 0x000f 115 #define PCI_DEVICE_ID_REDHAT_NVME 0x0010 116 #define PCI_DEVICE_ID_REDHAT_PVPANIC 0x0011 117 #define PCI_DEVICE_ID_REDHAT_ACPI_ERST 0x0012 118 #define PCI_DEVICE_ID_REDHAT_UFS 0x0013 119 #define PCI_DEVICE_ID_REDHAT_RISCV_IOMMU 0x0014 120 #define PCI_DEVICE_ID_REDHAT_QXL 0x0100 121 122 #define FMT_PCIBUS PRIx64 123 124 typedef uint64_t pcibus_t; 125 126 struct PCIHostDeviceAddress { 127 unsigned int domain; 128 unsigned int bus; 129 unsigned int slot; 130 unsigned int function; 131 }; 132 133 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, 134 uint32_t address, uint32_t data, int len); 135 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev, 136 uint32_t address, int len); 137 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, 138 pcibus_t addr, pcibus_t size, int type); 139 typedef void PCIUnregisterFunc(PCIDevice *pci_dev); 140 141 typedef void MSITriggerFunc(PCIDevice *dev, MSIMessage msg); 142 typedef MSIMessage MSIPrepareMessageFunc(PCIDevice *dev, unsigned vector); 143 typedef MSIMessage MSIxPrepareMessageFunc(PCIDevice *dev, unsigned vector); 144 145 typedef struct PCIIORegion { 146 pcibus_t addr; /* current PCI mapping address. -1 means not mapped */ 147 #define PCI_BAR_UNMAPPED (~(pcibus_t)0) 148 pcibus_t size; 149 uint8_t type; 150 MemoryRegion *memory; 151 MemoryRegion *address_space; 152 } PCIIORegion; 153 154 #define PCI_ROM_SLOT 6 155 #define PCI_NUM_REGIONS 7 156 157 enum { 158 QEMU_PCI_VGA_MEM, 159 QEMU_PCI_VGA_IO_LO, 160 QEMU_PCI_VGA_IO_HI, 161 QEMU_PCI_VGA_NUM_REGIONS, 162 }; 163 164 #define QEMU_PCI_VGA_MEM_BASE 0xa0000 165 #define QEMU_PCI_VGA_MEM_SIZE 0x20000 166 #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0 167 #define QEMU_PCI_VGA_IO_LO_SIZE 0xc 168 #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0 169 #define QEMU_PCI_VGA_IO_HI_SIZE 0x20 170 171 #include "hw/pci/pci_regs.h" 172 173 /* PCI HEADER_TYPE */ 174 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80 175 176 /* Size of the standard PCI config header */ 177 #define PCI_CONFIG_HEADER_SIZE 0x40 178 /* Size of the standard PCI config space */ 179 #define PCI_CONFIG_SPACE_SIZE 0x100 180 /* Size of the standard PCIe config space: 4KB */ 181 #define PCIE_CONFIG_SPACE_SIZE 0x1000 182 183 #define PCI_NUM_PINS 4 /* A-D */ 184 185 /* Bits in cap_present field. */ 186 enum { 187 QEMU_PCI_CAP_MSI = 0x1, 188 QEMU_PCI_CAP_MSIX = 0x2, 189 QEMU_PCI_CAP_EXPRESS = 0x4, 190 191 /* multifunction capable device */ 192 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3 193 QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR), 194 195 /* command register SERR bit enabled - unused since QEMU v5.0 */ 196 #define QEMU_PCI_CAP_SERR_BITNR 4 197 QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR), 198 /* Standard hot plug controller. */ 199 #define QEMU_PCI_SHPC_BITNR 5 200 QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR), 201 #define QEMU_PCI_SLOTID_BITNR 6 202 QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR), 203 /* PCI Express capability - Power Controller Present */ 204 #define QEMU_PCIE_SLTCAP_PCP_BITNR 7 205 QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR), 206 /* Link active status in endpoint capability is always set */ 207 #define QEMU_PCIE_LNKSTA_DLLLA_BITNR 8 208 QEMU_PCIE_LNKSTA_DLLLA = (1 << QEMU_PCIE_LNKSTA_DLLLA_BITNR), 209 #define QEMU_PCIE_EXTCAP_INIT_BITNR 9 210 QEMU_PCIE_EXTCAP_INIT = (1 << QEMU_PCIE_EXTCAP_INIT_BITNR), 211 #define QEMU_PCIE_CXL_BITNR 10 212 QEMU_PCIE_CAP_CXL = (1 << QEMU_PCIE_CXL_BITNR), 213 #define QEMU_PCIE_ERR_UNC_MASK_BITNR 11 214 QEMU_PCIE_ERR_UNC_MASK = (1 << QEMU_PCIE_ERR_UNC_MASK_BITNR), 215 #define QEMU_PCIE_ARI_NEXTFN_1_BITNR 12 216 QEMU_PCIE_ARI_NEXTFN_1 = (1 << QEMU_PCIE_ARI_NEXTFN_1_BITNR), 217 #define QEMU_PCIE_EXT_TAG_BITNR 13 218 QEMU_PCIE_EXT_TAG = (1 << QEMU_PCIE_EXT_TAG_BITNR), 219 }; 220 221 typedef struct PCIINTxRoute { 222 enum { 223 PCI_INTX_ENABLED, 224 PCI_INTX_INVERTED, 225 PCI_INTX_DISABLED, 226 } mode; 227 int irq; 228 } PCIINTxRoute; 229 230 typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev); 231 typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector, 232 MSIMessage msg); 233 typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector); 234 typedef void (*MSIVectorPollNotifier)(PCIDevice *dev, 235 unsigned int vector_start, 236 unsigned int vector_end); 237 238 void pci_register_bar(PCIDevice *pci_dev, int region_num, 239 uint8_t attr, MemoryRegion *memory); 240 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, 241 MemoryRegion *io_lo, MemoryRegion *io_hi); 242 void pci_unregister_vga(PCIDevice *pci_dev); 243 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num); 244 245 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, 246 uint8_t offset, uint8_t size, 247 Error **errp); 248 249 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size); 250 251 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id); 252 253 254 uint32_t pci_default_read_config(PCIDevice *d, 255 uint32_t address, int len); 256 void pci_default_write_config(PCIDevice *d, 257 uint32_t address, uint32_t val, int len); 258 void pci_device_save(PCIDevice *s, QEMUFile *f); 259 int pci_device_load(PCIDevice *s, QEMUFile *f); 260 MemoryRegion *pci_address_space(PCIDevice *dev); 261 MemoryRegion *pci_address_space_io(PCIDevice *dev); 262 263 /* 264 * Should not normally be used by devices. For use by sPAPR target 265 * where QEMU emulates firmware. 266 */ 267 int pci_bar(PCIDevice *d, int reg); 268 269 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level); 270 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); 271 typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin); 272 273 #define TYPE_PCI_BUS "PCI" 274 OBJECT_DECLARE_TYPE(PCIBus, PCIBusClass, PCI_BUS) 275 #define TYPE_PCIE_BUS "PCIE" 276 #define TYPE_CXL_BUS "CXL" 277 278 typedef void (*pci_bus_dev_fn)(PCIBus *b, PCIDevice *d, void *opaque); 279 typedef void (*pci_bus_fn)(PCIBus *b, void *opaque); 280 typedef void *(*pci_bus_ret_fn)(PCIBus *b, void *opaque); 281 282 bool pci_bus_is_express(const PCIBus *bus); 283 284 void pci_root_bus_init(PCIBus *bus, size_t bus_size, DeviceState *parent, 285 const char *name, 286 MemoryRegion *mem, MemoryRegion *io, 287 uint8_t devfn_min, const char *typename); 288 PCIBus *pci_root_bus_new(DeviceState *parent, const char *name, 289 MemoryRegion *mem, MemoryRegion *io, 290 uint8_t devfn_min, const char *typename); 291 void pci_root_bus_cleanup(PCIBus *bus); 292 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, 293 void *irq_opaque, int nirq); 294 void pci_bus_map_irqs(PCIBus *bus, pci_map_irq_fn map_irq); 295 void pci_bus_irqs_cleanup(PCIBus *bus); 296 int pci_bus_get_irq_level(PCIBus *bus, int irq_num); 297 uint32_t pci_bus_get_slot_reserved_mask(PCIBus *bus); 298 void pci_bus_set_slot_reserved_mask(PCIBus *bus, uint32_t mask); 299 void pci_bus_clear_slot_reserved_mask(PCIBus *bus, uint32_t mask); 300 /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */ 301 static inline int pci_swizzle(int slot, int pin) 302 { 303 return (slot + pin) % PCI_NUM_PINS; 304 } 305 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin); 306 PCIBus *pci_register_root_bus(DeviceState *parent, const char *name, 307 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 308 void *irq_opaque, 309 MemoryRegion *mem, MemoryRegion *io, 310 uint8_t devfn_min, int nirq, 311 const char *typename); 312 void pci_unregister_root_bus(PCIBus *bus); 313 void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn); 314 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin); 315 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new); 316 void pci_bus_fire_intx_routing_notifier(PCIBus *bus); 317 void pci_device_set_intx_routing_notifier(PCIDevice *dev, 318 PCIINTxRoutingNotifier notifier); 319 void pci_device_reset(PCIDevice *dev); 320 321 void pci_init_nic_devices(PCIBus *bus, const char *default_model); 322 bool pci_init_nic_in_slot(PCIBus *rootbus, const char *default_model, 323 const char *alias, const char *devaddr); 324 PCIDevice *pci_vga_init(PCIBus *bus); 325 326 static inline PCIBus *pci_get_bus(const PCIDevice *dev) 327 { 328 return PCI_BUS(qdev_get_parent_bus(DEVICE(dev))); 329 } 330 int pci_bus_num(PCIBus *s); 331 void pci_bus_range(PCIBus *bus, int *min_bus, int *max_bus); 332 static inline int pci_dev_bus_num(const PCIDevice *dev) 333 { 334 return pci_bus_num(pci_get_bus(dev)); 335 } 336 337 int pci_bus_numa_node(PCIBus *bus); 338 void pci_for_each_device(PCIBus *bus, int bus_num, 339 pci_bus_dev_fn fn, 340 void *opaque); 341 void pci_for_each_device_reverse(PCIBus *bus, int bus_num, 342 pci_bus_dev_fn fn, 343 void *opaque); 344 void pci_for_each_device_under_bus(PCIBus *bus, 345 pci_bus_dev_fn fn, void *opaque); 346 void pci_for_each_device_under_bus_reverse(PCIBus *bus, 347 pci_bus_dev_fn fn, 348 void *opaque); 349 void pci_for_each_bus_depth_first(PCIBus *bus, pci_bus_ret_fn begin, 350 pci_bus_fn end, void *parent_state); 351 PCIDevice *pci_get_function_0(PCIDevice *pci_dev); 352 353 /* Use this wrapper when specific scan order is not required. */ 354 static inline 355 void pci_for_each_bus(PCIBus *bus, pci_bus_fn fn, void *opaque) 356 { 357 pci_for_each_bus_depth_first(bus, NULL, fn, opaque); 358 } 359 360 PCIBus *pci_device_root_bus(const PCIDevice *d); 361 const char *pci_root_bus_path(PCIDevice *dev); 362 bool pci_bus_bypass_iommu(PCIBus *bus); 363 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn); 364 int pci_qdev_find_device(const char *id, PCIDevice **pdev); 365 void pci_bus_get_w64_range(PCIBus *bus, Range *range); 366 367 void pci_device_deassert_intx(PCIDevice *dev); 368 369 370 /** 371 * struct PCIIOMMUOps: callbacks structure for specific IOMMU handlers 372 * of a PCIBus 373 * 374 * Allows to modify the behavior of some IOMMU operations of the PCI 375 * framework for a set of devices on a PCI bus. 376 */ 377 typedef struct PCIIOMMUOps { 378 /** 379 * @get_address_space: get the address space for a set of devices 380 * on a PCI bus. 381 * 382 * Mandatory callback which returns a pointer to an #AddressSpace 383 * 384 * @bus: the #PCIBus being accessed. 385 * 386 * @opaque: the data passed to pci_setup_iommu(). 387 * 388 * @devfn: device and function number 389 */ 390 AddressSpace * (*get_address_space)(PCIBus *bus, void *opaque, int devfn); 391 /** 392 * @set_iommu_device: attach a HostIOMMUDevice to a vIOMMU 393 * 394 * Optional callback, if not implemented in vIOMMU, then vIOMMU can't 395 * retrieve host information from the associated HostIOMMUDevice. 396 * 397 * @bus: the #PCIBus of the PCI device. 398 * 399 * @opaque: the data passed to pci_setup_iommu(). 400 * 401 * @devfn: device and function number of the PCI device. 402 * 403 * @dev: the #HostIOMMUDevice to attach. 404 * 405 * @errp: pass an Error out only when return false 406 * 407 * Returns: true if HostIOMMUDevice is attached or else false with errp set. 408 */ 409 bool (*set_iommu_device)(PCIBus *bus, void *opaque, int devfn, 410 HostIOMMUDevice *dev, Error **errp); 411 /** 412 * @unset_iommu_device: detach a HostIOMMUDevice from a vIOMMU 413 * 414 * Optional callback. 415 * 416 * @bus: the #PCIBus of the PCI device. 417 * 418 * @opaque: the data passed to pci_setup_iommu(). 419 * 420 * @devfn: device and function number of the PCI device. 421 */ 422 void (*unset_iommu_device)(PCIBus *bus, void *opaque, int devfn); 423 } PCIIOMMUOps; 424 425 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev); 426 bool pci_device_set_iommu_device(PCIDevice *dev, HostIOMMUDevice *hiod, 427 Error **errp); 428 void pci_device_unset_iommu_device(PCIDevice *dev); 429 430 /** 431 * pci_setup_iommu: Initialize specific IOMMU handlers for a PCIBus 432 * 433 * Let PCI host bridges define specific operations. 434 * 435 * @bus: the #PCIBus being updated. 436 * @ops: the #PCIIOMMUOps 437 * @opaque: passed to callbacks of the @ops structure. 438 */ 439 void pci_setup_iommu(PCIBus *bus, const PCIIOMMUOps *ops, void *opaque); 440 441 pcibus_t pci_bar_address(PCIDevice *d, 442 int reg, uint8_t type, pcibus_t size); 443 444 static inline void 445 pci_set_byte(uint8_t *config, uint8_t val) 446 { 447 *config = val; 448 } 449 450 static inline uint8_t 451 pci_get_byte(const uint8_t *config) 452 { 453 return *config; 454 } 455 456 static inline void 457 pci_set_word(uint8_t *config, uint16_t val) 458 { 459 stw_le_p(config, val); 460 } 461 462 static inline uint16_t 463 pci_get_word(const uint8_t *config) 464 { 465 return lduw_le_p(config); 466 } 467 468 static inline void 469 pci_set_long(uint8_t *config, uint32_t val) 470 { 471 stl_le_p(config, val); 472 } 473 474 static inline uint32_t 475 pci_get_long(const uint8_t *config) 476 { 477 return ldl_le_p(config); 478 } 479 480 /* 481 * PCI capabilities and/or their fields 482 * are generally DWORD aligned only so 483 * mechanism used by pci_set/get_quad() 484 * must be tolerant to unaligned pointers 485 * 486 */ 487 static inline void 488 pci_set_quad(uint8_t *config, uint64_t val) 489 { 490 stq_le_p(config, val); 491 } 492 493 static inline uint64_t 494 pci_get_quad(const uint8_t *config) 495 { 496 return ldq_le_p(config); 497 } 498 499 static inline void 500 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val) 501 { 502 pci_set_word(&pci_config[PCI_VENDOR_ID], val); 503 } 504 505 static inline void 506 pci_config_set_device_id(uint8_t *pci_config, uint16_t val) 507 { 508 pci_set_word(&pci_config[PCI_DEVICE_ID], val); 509 } 510 511 static inline void 512 pci_config_set_revision(uint8_t *pci_config, uint8_t val) 513 { 514 pci_set_byte(&pci_config[PCI_REVISION_ID], val); 515 } 516 517 static inline void 518 pci_config_set_class(uint8_t *pci_config, uint16_t val) 519 { 520 pci_set_word(&pci_config[PCI_CLASS_DEVICE], val); 521 } 522 523 static inline void 524 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val) 525 { 526 pci_set_byte(&pci_config[PCI_CLASS_PROG], val); 527 } 528 529 static inline void 530 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val) 531 { 532 pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val); 533 } 534 535 /* 536 * helper functions to do bit mask operation on configuration space. 537 * Just to set bit, use test-and-set and discard returned value. 538 * Just to clear bit, use test-and-clear and discard returned value. 539 * NOTE: They aren't atomic. 540 */ 541 static inline uint8_t 542 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask) 543 { 544 uint8_t val = pci_get_byte(config); 545 pci_set_byte(config, val & ~mask); 546 return val & mask; 547 } 548 549 static inline uint8_t 550 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask) 551 { 552 uint8_t val = pci_get_byte(config); 553 pci_set_byte(config, val | mask); 554 return val & mask; 555 } 556 557 static inline uint16_t 558 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask) 559 { 560 uint16_t val = pci_get_word(config); 561 pci_set_word(config, val & ~mask); 562 return val & mask; 563 } 564 565 static inline uint16_t 566 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask) 567 { 568 uint16_t val = pci_get_word(config); 569 pci_set_word(config, val | mask); 570 return val & mask; 571 } 572 573 static inline uint32_t 574 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask) 575 { 576 uint32_t val = pci_get_long(config); 577 pci_set_long(config, val & ~mask); 578 return val & mask; 579 } 580 581 static inline uint32_t 582 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask) 583 { 584 uint32_t val = pci_get_long(config); 585 pci_set_long(config, val | mask); 586 return val & mask; 587 } 588 589 static inline uint64_t 590 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask) 591 { 592 uint64_t val = pci_get_quad(config); 593 pci_set_quad(config, val & ~mask); 594 return val & mask; 595 } 596 597 static inline uint64_t 598 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask) 599 { 600 uint64_t val = pci_get_quad(config); 601 pci_set_quad(config, val | mask); 602 return val & mask; 603 } 604 605 /* Access a register specified by a mask */ 606 static inline void 607 pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg) 608 { 609 uint8_t val = pci_get_byte(config); 610 uint8_t rval; 611 612 assert(mask); 613 rval = reg << ctz32(mask); 614 pci_set_byte(config, (~mask & val) | (mask & rval)); 615 } 616 617 static inline void 618 pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg) 619 { 620 uint16_t val = pci_get_word(config); 621 uint16_t rval; 622 623 assert(mask); 624 rval = reg << ctz32(mask); 625 pci_set_word(config, (~mask & val) | (mask & rval)); 626 } 627 628 static inline void 629 pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg) 630 { 631 uint32_t val = pci_get_long(config); 632 uint32_t rval; 633 634 assert(mask); 635 rval = reg << ctz32(mask); 636 pci_set_long(config, (~mask & val) | (mask & rval)); 637 } 638 639 static inline void 640 pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg) 641 { 642 uint64_t val = pci_get_quad(config); 643 uint64_t rval; 644 645 assert(mask); 646 rval = reg << ctz32(mask); 647 pci_set_quad(config, (~mask & val) | (mask & rval)); 648 } 649 650 PCIDevice *pci_new_multifunction(int devfn, const char *name); 651 PCIDevice *pci_new(int devfn, const char *name); 652 bool pci_realize_and_unref(PCIDevice *dev, PCIBus *bus, Error **errp); 653 654 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, 655 const char *name); 656 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name); 657 658 void lsi53c8xx_handle_legacy_cmdline(DeviceState *lsi_dev); 659 660 qemu_irq pci_allocate_irq(PCIDevice *pci_dev); 661 void pci_set_irq(PCIDevice *pci_dev, int level); 662 663 static inline void pci_irq_assert(PCIDevice *pci_dev) 664 { 665 pci_set_irq(pci_dev, 1); 666 } 667 668 static inline void pci_irq_deassert(PCIDevice *pci_dev) 669 { 670 pci_set_irq(pci_dev, 0); 671 } 672 673 /* 674 * FIXME: PCI does not work this way. 675 * All the callers to this method should be fixed. 676 */ 677 static inline void pci_irq_pulse(PCIDevice *pci_dev) 678 { 679 pci_irq_assert(pci_dev); 680 pci_irq_deassert(pci_dev); 681 } 682 683 MSIMessage pci_get_msi_message(PCIDevice *dev, int vector); 684 void pci_set_power(PCIDevice *pci_dev, bool state); 685 686 #endif 687