1 #ifndef QEMU_PCI_H 2 #define QEMU_PCI_H 3 4 #include "exec/memory.h" 5 #include "sysemu/dma.h" 6 7 /* PCI includes legacy ISA access. */ 8 #include "hw/isa/isa.h" 9 10 #include "hw/pci/pcie.h" 11 #include "qom/object.h" 12 13 extern bool pci_available; 14 15 /* PCI bus */ 16 17 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 18 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 19 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 20 #define PCI_FUNC(devfn) ((devfn) & 0x07) 21 #define PCI_BUILD_BDF(bus, devfn) ((bus << 8) | (devfn)) 22 #define PCI_BUS_MAX 256 23 #define PCI_DEVFN_MAX 256 24 #define PCI_SLOT_MAX 32 25 #define PCI_FUNC_MAX 8 26 27 /* Class, Vendor and Device IDs from Linux's pci_ids.h */ 28 #include "hw/pci/pci_ids.h" 29 30 /* QEMU-specific Vendor and Device ID definitions */ 31 32 /* IBM (0x1014) */ 33 #define PCI_DEVICE_ID_IBM_440GX 0x027f 34 #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff 35 36 /* Hitachi (0x1054) */ 37 #define PCI_VENDOR_ID_HITACHI 0x1054 38 #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e 39 40 /* Apple (0x106b) */ 41 #define PCI_DEVICE_ID_APPLE_343S1201 0x0010 42 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e 43 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f 44 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022 45 #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f 46 47 /* Realtek (0x10ec) */ 48 #define PCI_DEVICE_ID_REALTEK_8029 0x8029 49 50 /* Xilinx (0x10ee) */ 51 #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300 52 53 /* Marvell (0x11ab) */ 54 #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620 55 56 /* QEMU/Bochs VGA (0x1234) */ 57 #define PCI_VENDOR_ID_QEMU 0x1234 58 #define PCI_DEVICE_ID_QEMU_VGA 0x1111 59 #define PCI_DEVICE_ID_QEMU_IPMI 0x1112 60 61 /* VMWare (0x15ad) */ 62 #define PCI_VENDOR_ID_VMWARE 0x15ad 63 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 64 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710 65 #define PCI_DEVICE_ID_VMWARE_NET 0x0720 66 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730 67 #define PCI_DEVICE_ID_VMWARE_PVSCSI 0x07C0 68 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729 69 #define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0 70 71 /* Intel (0x8086) */ 72 #define PCI_DEVICE_ID_INTEL_82551IT 0x1209 73 #define PCI_DEVICE_ID_INTEL_82557 0x1229 74 #define PCI_DEVICE_ID_INTEL_82801IR 0x2922 75 76 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */ 77 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 78 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 79 #define PCI_SUBDEVICE_ID_QEMU 0x1100 80 81 #define PCI_DEVICE_ID_VIRTIO_NET 0x1000 82 #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001 83 #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002 84 #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003 85 #define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004 86 #define PCI_DEVICE_ID_VIRTIO_RNG 0x1005 87 #define PCI_DEVICE_ID_VIRTIO_9P 0x1009 88 #define PCI_DEVICE_ID_VIRTIO_VSOCK 0x1012 89 #define PCI_DEVICE_ID_VIRTIO_PMEM 0x1013 90 #define PCI_DEVICE_ID_VIRTIO_IOMMU 0x1014 91 #define PCI_DEVICE_ID_VIRTIO_MEM 0x1015 92 93 #define PCI_VENDOR_ID_REDHAT 0x1b36 94 #define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001 95 #define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002 96 #define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003 97 #define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004 98 #define PCI_DEVICE_ID_REDHAT_TEST 0x0005 99 #define PCI_DEVICE_ID_REDHAT_ROCKER 0x0006 100 #define PCI_DEVICE_ID_REDHAT_SDHCI 0x0007 101 #define PCI_DEVICE_ID_REDHAT_PCIE_HOST 0x0008 102 #define PCI_DEVICE_ID_REDHAT_PXB 0x0009 103 #define PCI_DEVICE_ID_REDHAT_BRIDGE_SEAT 0x000a 104 #define PCI_DEVICE_ID_REDHAT_PXB_PCIE 0x000b 105 #define PCI_DEVICE_ID_REDHAT_PCIE_RP 0x000c 106 #define PCI_DEVICE_ID_REDHAT_XHCI 0x000d 107 #define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000e 108 #define PCI_DEVICE_ID_REDHAT_MDPY 0x000f 109 #define PCI_DEVICE_ID_REDHAT_NVME 0x0010 110 #define PCI_DEVICE_ID_REDHAT_PVPANIC 0x0011 111 #define PCI_DEVICE_ID_REDHAT_ACPI_ERST 0x0012 112 #define PCI_DEVICE_ID_REDHAT_QXL 0x0100 113 114 #define FMT_PCIBUS PRIx64 115 116 typedef uint64_t pcibus_t; 117 118 struct PCIHostDeviceAddress { 119 unsigned int domain; 120 unsigned int bus; 121 unsigned int slot; 122 unsigned int function; 123 }; 124 125 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, 126 uint32_t address, uint32_t data, int len); 127 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev, 128 uint32_t address, int len); 129 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, 130 pcibus_t addr, pcibus_t size, int type); 131 typedef void PCIUnregisterFunc(PCIDevice *pci_dev); 132 133 typedef struct PCIIORegion { 134 pcibus_t addr; /* current PCI mapping address. -1 means not mapped */ 135 #define PCI_BAR_UNMAPPED (~(pcibus_t)0) 136 pcibus_t size; 137 uint8_t type; 138 MemoryRegion *memory; 139 MemoryRegion *address_space; 140 } PCIIORegion; 141 142 #define PCI_ROM_SLOT 6 143 #define PCI_NUM_REGIONS 7 144 145 enum { 146 QEMU_PCI_VGA_MEM, 147 QEMU_PCI_VGA_IO_LO, 148 QEMU_PCI_VGA_IO_HI, 149 QEMU_PCI_VGA_NUM_REGIONS, 150 }; 151 152 #define QEMU_PCI_VGA_MEM_BASE 0xa0000 153 #define QEMU_PCI_VGA_MEM_SIZE 0x20000 154 #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0 155 #define QEMU_PCI_VGA_IO_LO_SIZE 0xc 156 #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0 157 #define QEMU_PCI_VGA_IO_HI_SIZE 0x20 158 159 #include "hw/pci/pci_regs.h" 160 161 /* PCI HEADER_TYPE */ 162 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80 163 164 /* Size of the standard PCI config header */ 165 #define PCI_CONFIG_HEADER_SIZE 0x40 166 /* Size of the standard PCI config space */ 167 #define PCI_CONFIG_SPACE_SIZE 0x100 168 /* Size of the standard PCIe config space: 4KB */ 169 #define PCIE_CONFIG_SPACE_SIZE 0x1000 170 171 #define PCI_NUM_PINS 4 /* A-D */ 172 173 /* Bits in cap_present field. */ 174 enum { 175 QEMU_PCI_CAP_MSI = 0x1, 176 QEMU_PCI_CAP_MSIX = 0x2, 177 QEMU_PCI_CAP_EXPRESS = 0x4, 178 179 /* multifunction capable device */ 180 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3 181 QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR), 182 183 /* command register SERR bit enabled - unused since QEMU v5.0 */ 184 #define QEMU_PCI_CAP_SERR_BITNR 4 185 QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR), 186 /* Standard hot plug controller. */ 187 #define QEMU_PCI_SHPC_BITNR 5 188 QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR), 189 #define QEMU_PCI_SLOTID_BITNR 6 190 QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR), 191 /* PCI Express capability - Power Controller Present */ 192 #define QEMU_PCIE_SLTCAP_PCP_BITNR 7 193 QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR), 194 /* Link active status in endpoint capability is always set */ 195 #define QEMU_PCIE_LNKSTA_DLLLA_BITNR 8 196 QEMU_PCIE_LNKSTA_DLLLA = (1 << QEMU_PCIE_LNKSTA_DLLLA_BITNR), 197 #define QEMU_PCIE_EXTCAP_INIT_BITNR 9 198 QEMU_PCIE_EXTCAP_INIT = (1 << QEMU_PCIE_EXTCAP_INIT_BITNR), 199 }; 200 201 #define TYPE_PCI_DEVICE "pci-device" 202 typedef struct PCIDeviceClass PCIDeviceClass; 203 DECLARE_OBJ_CHECKERS(PCIDevice, PCIDeviceClass, 204 PCI_DEVICE, TYPE_PCI_DEVICE) 205 206 /* Implemented by devices that can be plugged on PCI Express buses */ 207 #define INTERFACE_PCIE_DEVICE "pci-express-device" 208 209 /* Implemented by devices that can be plugged on Conventional PCI buses */ 210 #define INTERFACE_CONVENTIONAL_PCI_DEVICE "conventional-pci-device" 211 212 typedef struct PCIINTxRoute { 213 enum { 214 PCI_INTX_ENABLED, 215 PCI_INTX_INVERTED, 216 PCI_INTX_DISABLED, 217 } mode; 218 int irq; 219 } PCIINTxRoute; 220 221 struct PCIDeviceClass { 222 DeviceClass parent_class; 223 224 void (*realize)(PCIDevice *dev, Error **errp); 225 PCIUnregisterFunc *exit; 226 PCIConfigReadFunc *config_read; 227 PCIConfigWriteFunc *config_write; 228 229 uint16_t vendor_id; 230 uint16_t device_id; 231 uint8_t revision; 232 uint16_t class_id; 233 uint16_t subsystem_vendor_id; /* only for header type = 0 */ 234 uint16_t subsystem_id; /* only for header type = 0 */ 235 236 /* 237 * pci-to-pci bridge or normal device. 238 * This doesn't mean pci host switch. 239 * When card bus bridge is supported, this would be enhanced. 240 */ 241 bool is_bridge; 242 243 /* rom bar */ 244 const char *romfile; 245 }; 246 247 typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev); 248 typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector, 249 MSIMessage msg); 250 typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector); 251 typedef void (*MSIVectorPollNotifier)(PCIDevice *dev, 252 unsigned int vector_start, 253 unsigned int vector_end); 254 255 enum PCIReqIDType { 256 PCI_REQ_ID_INVALID = 0, 257 PCI_REQ_ID_BDF, 258 PCI_REQ_ID_SECONDARY_BUS, 259 PCI_REQ_ID_MAX, 260 }; 261 typedef enum PCIReqIDType PCIReqIDType; 262 263 struct PCIReqIDCache { 264 PCIDevice *dev; 265 PCIReqIDType type; 266 }; 267 typedef struct PCIReqIDCache PCIReqIDCache; 268 269 struct PCIDevice { 270 DeviceState qdev; 271 bool partially_hotplugged; 272 bool has_power; 273 274 /* PCI config space */ 275 uint8_t *config; 276 277 /* Used to enable config checks on load. Note that writable bits are 278 * never checked even if set in cmask. */ 279 uint8_t *cmask; 280 281 /* Used to implement R/W bytes */ 282 uint8_t *wmask; 283 284 /* Used to implement RW1C(Write 1 to Clear) bytes */ 285 uint8_t *w1cmask; 286 287 /* Used to allocate config space for capabilities. */ 288 uint8_t *used; 289 290 /* the following fields are read only */ 291 int32_t devfn; 292 /* Cached device to fetch requester ID from, to avoid the PCI 293 * tree walking every time we invoke PCI request (e.g., 294 * MSI). For conventional PCI root complex, this field is 295 * meaningless. */ 296 PCIReqIDCache requester_id_cache; 297 char name[64]; 298 PCIIORegion io_regions[PCI_NUM_REGIONS]; 299 AddressSpace bus_master_as; 300 MemoryRegion bus_master_container_region; 301 MemoryRegion bus_master_enable_region; 302 303 /* do not access the following fields */ 304 PCIConfigReadFunc *config_read; 305 PCIConfigWriteFunc *config_write; 306 307 /* Legacy PCI VGA regions */ 308 MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS]; 309 bool has_vga; 310 311 /* Current IRQ levels. Used internally by the generic PCI code. */ 312 uint8_t irq_state; 313 314 /* Capability bits */ 315 uint32_t cap_present; 316 317 /* Offset of MSI-X capability in config space */ 318 uint8_t msix_cap; 319 320 /* MSI-X entries */ 321 int msix_entries_nr; 322 323 /* Space to store MSIX table & pending bit array */ 324 uint8_t *msix_table; 325 uint8_t *msix_pba; 326 /* MemoryRegion container for msix exclusive BAR setup */ 327 MemoryRegion msix_exclusive_bar; 328 /* Memory Regions for MSIX table and pending bit entries. */ 329 MemoryRegion msix_table_mmio; 330 MemoryRegion msix_pba_mmio; 331 /* Reference-count for entries actually in use by driver. */ 332 unsigned *msix_entry_used; 333 /* MSIX function mask set or MSIX disabled */ 334 bool msix_function_masked; 335 /* Version id needed for VMState */ 336 int32_t version_id; 337 338 /* Offset of MSI capability in config space */ 339 uint8_t msi_cap; 340 341 /* PCI Express */ 342 PCIExpressDevice exp; 343 344 /* SHPC */ 345 SHPCDevice *shpc; 346 347 /* Location of option rom */ 348 char *romfile; 349 uint32_t romsize; 350 bool has_rom; 351 MemoryRegion rom; 352 uint32_t rom_bar; 353 354 /* INTx routing notifier */ 355 PCIINTxRoutingNotifier intx_routing_notifier; 356 357 /* MSI-X notifiers */ 358 MSIVectorUseNotifier msix_vector_use_notifier; 359 MSIVectorReleaseNotifier msix_vector_release_notifier; 360 MSIVectorPollNotifier msix_vector_poll_notifier; 361 362 /* ID of standby device in net_failover pair */ 363 char *failover_pair_id; 364 uint32_t acpi_index; 365 }; 366 367 void pci_register_bar(PCIDevice *pci_dev, int region_num, 368 uint8_t attr, MemoryRegion *memory); 369 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, 370 MemoryRegion *io_lo, MemoryRegion *io_hi); 371 void pci_unregister_vga(PCIDevice *pci_dev); 372 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num); 373 374 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, 375 uint8_t offset, uint8_t size, 376 Error **errp); 377 378 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size); 379 380 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id); 381 382 383 uint32_t pci_default_read_config(PCIDevice *d, 384 uint32_t address, int len); 385 void pci_default_write_config(PCIDevice *d, 386 uint32_t address, uint32_t val, int len); 387 void pci_device_save(PCIDevice *s, QEMUFile *f); 388 int pci_device_load(PCIDevice *s, QEMUFile *f); 389 MemoryRegion *pci_address_space(PCIDevice *dev); 390 MemoryRegion *pci_address_space_io(PCIDevice *dev); 391 392 /* 393 * Should not normally be used by devices. For use by sPAPR target 394 * where QEMU emulates firmware. 395 */ 396 int pci_bar(PCIDevice *d, int reg); 397 398 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level); 399 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); 400 typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin); 401 402 #define TYPE_PCI_BUS "PCI" 403 OBJECT_DECLARE_TYPE(PCIBus, PCIBusClass, PCI_BUS) 404 #define TYPE_PCIE_BUS "PCIE" 405 406 typedef void (*pci_bus_dev_fn)(PCIBus *b, PCIDevice *d, void *opaque); 407 typedef void (*pci_bus_fn)(PCIBus *b, void *opaque); 408 typedef void *(*pci_bus_ret_fn)(PCIBus *b, void *opaque); 409 410 bool pci_bus_is_express(PCIBus *bus); 411 412 void pci_root_bus_init(PCIBus *bus, size_t bus_size, DeviceState *parent, 413 const char *name, 414 MemoryRegion *address_space_mem, 415 MemoryRegion *address_space_io, 416 uint8_t devfn_min, const char *typename); 417 PCIBus *pci_root_bus_new(DeviceState *parent, const char *name, 418 MemoryRegion *address_space_mem, 419 MemoryRegion *address_space_io, 420 uint8_t devfn_min, const char *typename); 421 void pci_root_bus_cleanup(PCIBus *bus); 422 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 423 void *irq_opaque, int nirq); 424 void pci_bus_irqs_cleanup(PCIBus *bus); 425 int pci_bus_get_irq_level(PCIBus *bus, int irq_num); 426 /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */ 427 static inline int pci_swizzle(int slot, int pin) 428 { 429 return (slot + pin) % PCI_NUM_PINS; 430 } 431 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin); 432 PCIBus *pci_register_root_bus(DeviceState *parent, const char *name, 433 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 434 void *irq_opaque, 435 MemoryRegion *address_space_mem, 436 MemoryRegion *address_space_io, 437 uint8_t devfn_min, int nirq, 438 const char *typename); 439 void pci_unregister_root_bus(PCIBus *bus); 440 void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn); 441 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin); 442 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new); 443 void pci_bus_fire_intx_routing_notifier(PCIBus *bus); 444 void pci_device_set_intx_routing_notifier(PCIDevice *dev, 445 PCIINTxRoutingNotifier notifier); 446 void pci_device_reset(PCIDevice *dev); 447 448 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus, 449 const char *default_model, 450 const char *default_devaddr); 451 452 PCIDevice *pci_vga_init(PCIBus *bus); 453 454 static inline PCIBus *pci_get_bus(const PCIDevice *dev) 455 { 456 return PCI_BUS(qdev_get_parent_bus(DEVICE(dev))); 457 } 458 int pci_bus_num(PCIBus *s); 459 void pci_bus_range(PCIBus *bus, int *min_bus, int *max_bus); 460 static inline int pci_dev_bus_num(const PCIDevice *dev) 461 { 462 return pci_bus_num(pci_get_bus(dev)); 463 } 464 465 int pci_bus_numa_node(PCIBus *bus); 466 void pci_for_each_device(PCIBus *bus, int bus_num, 467 pci_bus_dev_fn fn, 468 void *opaque); 469 void pci_for_each_device_reverse(PCIBus *bus, int bus_num, 470 pci_bus_dev_fn fn, 471 void *opaque); 472 void pci_for_each_device_under_bus(PCIBus *bus, 473 pci_bus_dev_fn fn, void *opaque); 474 void pci_for_each_device_under_bus_reverse(PCIBus *bus, 475 pci_bus_dev_fn fn, 476 void *opaque); 477 void pci_for_each_bus_depth_first(PCIBus *bus, pci_bus_ret_fn begin, 478 pci_bus_fn end, void *parent_state); 479 PCIDevice *pci_get_function_0(PCIDevice *pci_dev); 480 481 /* Use this wrapper when specific scan order is not required. */ 482 static inline 483 void pci_for_each_bus(PCIBus *bus, pci_bus_fn fn, void *opaque) 484 { 485 pci_for_each_bus_depth_first(bus, NULL, fn, opaque); 486 } 487 488 PCIBus *pci_device_root_bus(const PCIDevice *d); 489 const char *pci_root_bus_path(PCIDevice *dev); 490 bool pci_bus_bypass_iommu(PCIBus *bus); 491 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn); 492 int pci_qdev_find_device(const char *id, PCIDevice **pdev); 493 void pci_bus_get_w64_range(PCIBus *bus, Range *range); 494 495 void pci_device_deassert_intx(PCIDevice *dev); 496 497 typedef AddressSpace *(*PCIIOMMUFunc)(PCIBus *, void *, int); 498 499 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev); 500 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque); 501 502 static inline void 503 pci_set_byte(uint8_t *config, uint8_t val) 504 { 505 *config = val; 506 } 507 508 static inline uint8_t 509 pci_get_byte(const uint8_t *config) 510 { 511 return *config; 512 } 513 514 static inline void 515 pci_set_word(uint8_t *config, uint16_t val) 516 { 517 stw_le_p(config, val); 518 } 519 520 static inline uint16_t 521 pci_get_word(const uint8_t *config) 522 { 523 return lduw_le_p(config); 524 } 525 526 static inline void 527 pci_set_long(uint8_t *config, uint32_t val) 528 { 529 stl_le_p(config, val); 530 } 531 532 static inline uint32_t 533 pci_get_long(const uint8_t *config) 534 { 535 return ldl_le_p(config); 536 } 537 538 /* 539 * PCI capabilities and/or their fields 540 * are generally DWORD aligned only so 541 * mechanism used by pci_set/get_quad() 542 * must be tolerant to unaligned pointers 543 * 544 */ 545 static inline void 546 pci_set_quad(uint8_t *config, uint64_t val) 547 { 548 stq_le_p(config, val); 549 } 550 551 static inline uint64_t 552 pci_get_quad(const uint8_t *config) 553 { 554 return ldq_le_p(config); 555 } 556 557 static inline void 558 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val) 559 { 560 pci_set_word(&pci_config[PCI_VENDOR_ID], val); 561 } 562 563 static inline void 564 pci_config_set_device_id(uint8_t *pci_config, uint16_t val) 565 { 566 pci_set_word(&pci_config[PCI_DEVICE_ID], val); 567 } 568 569 static inline void 570 pci_config_set_revision(uint8_t *pci_config, uint8_t val) 571 { 572 pci_set_byte(&pci_config[PCI_REVISION_ID], val); 573 } 574 575 static inline void 576 pci_config_set_class(uint8_t *pci_config, uint16_t val) 577 { 578 pci_set_word(&pci_config[PCI_CLASS_DEVICE], val); 579 } 580 581 static inline void 582 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val) 583 { 584 pci_set_byte(&pci_config[PCI_CLASS_PROG], val); 585 } 586 587 static inline void 588 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val) 589 { 590 pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val); 591 } 592 593 /* 594 * helper functions to do bit mask operation on configuration space. 595 * Just to set bit, use test-and-set and discard returned value. 596 * Just to clear bit, use test-and-clear and discard returned value. 597 * NOTE: They aren't atomic. 598 */ 599 static inline uint8_t 600 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask) 601 { 602 uint8_t val = pci_get_byte(config); 603 pci_set_byte(config, val & ~mask); 604 return val & mask; 605 } 606 607 static inline uint8_t 608 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask) 609 { 610 uint8_t val = pci_get_byte(config); 611 pci_set_byte(config, val | mask); 612 return val & mask; 613 } 614 615 static inline uint16_t 616 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask) 617 { 618 uint16_t val = pci_get_word(config); 619 pci_set_word(config, val & ~mask); 620 return val & mask; 621 } 622 623 static inline uint16_t 624 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask) 625 { 626 uint16_t val = pci_get_word(config); 627 pci_set_word(config, val | mask); 628 return val & mask; 629 } 630 631 static inline uint32_t 632 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask) 633 { 634 uint32_t val = pci_get_long(config); 635 pci_set_long(config, val & ~mask); 636 return val & mask; 637 } 638 639 static inline uint32_t 640 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask) 641 { 642 uint32_t val = pci_get_long(config); 643 pci_set_long(config, val | mask); 644 return val & mask; 645 } 646 647 static inline uint64_t 648 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask) 649 { 650 uint64_t val = pci_get_quad(config); 651 pci_set_quad(config, val & ~mask); 652 return val & mask; 653 } 654 655 static inline uint64_t 656 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask) 657 { 658 uint64_t val = pci_get_quad(config); 659 pci_set_quad(config, val | mask); 660 return val & mask; 661 } 662 663 /* Access a register specified by a mask */ 664 static inline void 665 pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg) 666 { 667 uint8_t val = pci_get_byte(config); 668 uint8_t rval = reg << ctz32(mask); 669 pci_set_byte(config, (~mask & val) | (mask & rval)); 670 } 671 672 static inline uint8_t 673 pci_get_byte_by_mask(uint8_t *config, uint8_t mask) 674 { 675 uint8_t val = pci_get_byte(config); 676 return (val & mask) >> ctz32(mask); 677 } 678 679 static inline void 680 pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg) 681 { 682 uint16_t val = pci_get_word(config); 683 uint16_t rval = reg << ctz32(mask); 684 pci_set_word(config, (~mask & val) | (mask & rval)); 685 } 686 687 static inline uint16_t 688 pci_get_word_by_mask(uint8_t *config, uint16_t mask) 689 { 690 uint16_t val = pci_get_word(config); 691 return (val & mask) >> ctz32(mask); 692 } 693 694 static inline void 695 pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg) 696 { 697 uint32_t val = pci_get_long(config); 698 uint32_t rval = reg << ctz32(mask); 699 pci_set_long(config, (~mask & val) | (mask & rval)); 700 } 701 702 static inline uint32_t 703 pci_get_long_by_mask(uint8_t *config, uint32_t mask) 704 { 705 uint32_t val = pci_get_long(config); 706 return (val & mask) >> ctz32(mask); 707 } 708 709 static inline void 710 pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg) 711 { 712 uint64_t val = pci_get_quad(config); 713 uint64_t rval = reg << ctz32(mask); 714 pci_set_quad(config, (~mask & val) | (mask & rval)); 715 } 716 717 static inline uint64_t 718 pci_get_quad_by_mask(uint8_t *config, uint64_t mask) 719 { 720 uint64_t val = pci_get_quad(config); 721 return (val & mask) >> ctz32(mask); 722 } 723 724 PCIDevice *pci_new_multifunction(int devfn, bool multifunction, 725 const char *name); 726 PCIDevice *pci_new(int devfn, const char *name); 727 bool pci_realize_and_unref(PCIDevice *dev, PCIBus *bus, Error **errp); 728 729 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, 730 bool multifunction, 731 const char *name); 732 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name); 733 734 void lsi53c8xx_handle_legacy_cmdline(DeviceState *lsi_dev); 735 736 qemu_irq pci_allocate_irq(PCIDevice *pci_dev); 737 void pci_set_irq(PCIDevice *pci_dev, int level); 738 739 static inline int pci_intx(PCIDevice *pci_dev) 740 { 741 return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1; 742 } 743 744 static inline void pci_irq_assert(PCIDevice *pci_dev) 745 { 746 pci_set_irq(pci_dev, 1); 747 } 748 749 static inline void pci_irq_deassert(PCIDevice *pci_dev) 750 { 751 pci_set_irq(pci_dev, 0); 752 } 753 754 /* 755 * FIXME: PCI does not work this way. 756 * All the callers to this method should be fixed. 757 */ 758 static inline void pci_irq_pulse(PCIDevice *pci_dev) 759 { 760 pci_irq_assert(pci_dev); 761 pci_irq_deassert(pci_dev); 762 } 763 764 static inline int pci_is_express(const PCIDevice *d) 765 { 766 return d->cap_present & QEMU_PCI_CAP_EXPRESS; 767 } 768 769 static inline int pci_is_express_downstream_port(const PCIDevice *d) 770 { 771 uint8_t type; 772 773 if (!pci_is_express(d) || !d->exp.exp_cap) { 774 return 0; 775 } 776 777 type = pcie_cap_get_type(d); 778 779 return type == PCI_EXP_TYPE_DOWNSTREAM || type == PCI_EXP_TYPE_ROOT_PORT; 780 } 781 782 static inline uint32_t pci_config_size(const PCIDevice *d) 783 { 784 return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE; 785 } 786 787 static inline uint16_t pci_get_bdf(PCIDevice *dev) 788 { 789 return PCI_BUILD_BDF(pci_bus_num(pci_get_bus(dev)), dev->devfn); 790 } 791 792 uint16_t pci_requester_id(PCIDevice *dev); 793 794 /* DMA access functions */ 795 static inline AddressSpace *pci_get_address_space(PCIDevice *dev) 796 { 797 return &dev->bus_master_as; 798 } 799 800 /** 801 * pci_dma_rw: Read from or write to an address space from PCI device. 802 * 803 * Return a MemTxResult indicating whether the operation succeeded 804 * or failed (eg unassigned memory, device rejected the transaction, 805 * IOMMU fault). 806 * 807 * @dev: #PCIDevice doing the memory access 808 * @addr: address within the #PCIDevice address space 809 * @buf: buffer with the data transferred 810 * @len: the number of bytes to read or write 811 * @dir: indicates the transfer direction 812 */ 813 static inline MemTxResult pci_dma_rw(PCIDevice *dev, dma_addr_t addr, 814 void *buf, dma_addr_t len, 815 DMADirection dir, MemTxAttrs attrs) 816 { 817 return dma_memory_rw(pci_get_address_space(dev), addr, buf, len, 818 dir, attrs); 819 } 820 821 /** 822 * pci_dma_read: Read from an address space from PCI device. 823 * 824 * Return a MemTxResult indicating whether the operation succeeded 825 * or failed (eg unassigned memory, device rejected the transaction, 826 * IOMMU fault). Called within RCU critical section. 827 * 828 * @dev: #PCIDevice doing the memory access 829 * @addr: address within the #PCIDevice address space 830 * @buf: buffer with the data transferred 831 * @len: length of the data transferred 832 */ 833 static inline MemTxResult pci_dma_read(PCIDevice *dev, dma_addr_t addr, 834 void *buf, dma_addr_t len) 835 { 836 return pci_dma_rw(dev, addr, buf, len, 837 DMA_DIRECTION_TO_DEVICE, MEMTXATTRS_UNSPECIFIED); 838 } 839 840 /** 841 * pci_dma_write: Write to address space from PCI device. 842 * 843 * Return a MemTxResult indicating whether the operation succeeded 844 * or failed (eg unassigned memory, device rejected the transaction, 845 * IOMMU fault). 846 * 847 * @dev: #PCIDevice doing the memory access 848 * @addr: address within the #PCIDevice address space 849 * @buf: buffer with the data transferred 850 * @len: the number of bytes to write 851 */ 852 static inline MemTxResult pci_dma_write(PCIDevice *dev, dma_addr_t addr, 853 const void *buf, dma_addr_t len) 854 { 855 return pci_dma_rw(dev, addr, (void *) buf, len, 856 DMA_DIRECTION_FROM_DEVICE, MEMTXATTRS_UNSPECIFIED); 857 } 858 859 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \ 860 static inline MemTxResult ld##_l##_pci_dma(PCIDevice *dev, \ 861 dma_addr_t addr, \ 862 uint##_bits##_t *val, \ 863 MemTxAttrs attrs) \ 864 { \ 865 return ld##_l##_dma(pci_get_address_space(dev), addr, val, attrs); \ 866 } \ 867 static inline MemTxResult st##_s##_pci_dma(PCIDevice *dev, \ 868 dma_addr_t addr, \ 869 uint##_bits##_t val, \ 870 MemTxAttrs attrs) \ 871 { \ 872 return st##_s##_dma(pci_get_address_space(dev), addr, val, attrs); \ 873 } 874 875 PCI_DMA_DEFINE_LDST(ub, b, 8); 876 PCI_DMA_DEFINE_LDST(uw_le, w_le, 16) 877 PCI_DMA_DEFINE_LDST(l_le, l_le, 32); 878 PCI_DMA_DEFINE_LDST(q_le, q_le, 64); 879 PCI_DMA_DEFINE_LDST(uw_be, w_be, 16) 880 PCI_DMA_DEFINE_LDST(l_be, l_be, 32); 881 PCI_DMA_DEFINE_LDST(q_be, q_be, 64); 882 883 #undef PCI_DMA_DEFINE_LDST 884 885 /** 886 * pci_dma_map: Map device PCI address space range into host virtual address 887 * @dev: #PCIDevice to be accessed 888 * @addr: address within that device's address space 889 * @plen: pointer to length of buffer; updated on return to indicate 890 * if only a subset of the requested range has been mapped 891 * @dir: indicates the transfer direction 892 * 893 * Return: A host pointer, or %NULL if the resources needed to 894 * perform the mapping are exhausted (in that case *@plen 895 * is set to zero). 896 */ 897 static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr, 898 dma_addr_t *plen, DMADirection dir) 899 { 900 void *buf; 901 902 buf = dma_memory_map(pci_get_address_space(dev), addr, plen, dir, 903 MEMTXATTRS_UNSPECIFIED); 904 return buf; 905 } 906 907 static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len, 908 DMADirection dir, dma_addr_t access_len) 909 { 910 dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len); 911 } 912 913 static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev, 914 int alloc_hint) 915 { 916 qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev)); 917 } 918 919 extern const VMStateDescription vmstate_pci_device; 920 921 #define VMSTATE_PCI_DEVICE(_field, _state) { \ 922 .name = (stringify(_field)), \ 923 .size = sizeof(PCIDevice), \ 924 .vmsd = &vmstate_pci_device, \ 925 .flags = VMS_STRUCT, \ 926 .offset = vmstate_offset_value(_state, _field, PCIDevice), \ 927 } 928 929 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \ 930 .name = (stringify(_field)), \ 931 .size = sizeof(PCIDevice), \ 932 .vmsd = &vmstate_pci_device, \ 933 .flags = VMS_STRUCT|VMS_POINTER, \ 934 .offset = vmstate_offset_pointer(_state, _field, PCIDevice), \ 935 } 936 937 MSIMessage pci_get_msi_message(PCIDevice *dev, int vector); 938 void pci_set_power(PCIDevice *pci_dev, bool state); 939 940 #endif 941