1 #ifndef QEMU_PCI_H 2 #define QEMU_PCI_H 3 4 #include "exec/memory.h" 5 #include "sysemu/dma.h" 6 #include "sysemu/host_iommu_device.h" 7 8 /* PCI includes legacy ISA access. */ 9 #include "hw/isa/isa.h" 10 11 extern bool pci_available; 12 13 /* PCI bus */ 14 15 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 16 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 17 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 18 #define PCI_FUNC(devfn) ((devfn) & 0x07) 19 #define PCI_BUILD_BDF(bus, devfn) ((bus << 8) | (devfn)) 20 #define PCI_BDF_TO_DEVFN(x) ((x) & 0xff) 21 #define PCI_BUS_MAX 256 22 #define PCI_DEVFN_MAX 256 23 #define PCI_SLOT_MAX 32 24 #define PCI_FUNC_MAX 8 25 26 /* Class, Vendor and Device IDs from Linux's pci_ids.h */ 27 #include "hw/pci/pci_ids.h" 28 29 /* QEMU-specific Vendor and Device ID definitions */ 30 31 /* IBM (0x1014) */ 32 #define PCI_DEVICE_ID_IBM_440GX 0x027f 33 #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff 34 35 /* Hitachi (0x1054) */ 36 #define PCI_VENDOR_ID_HITACHI 0x1054 37 #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e 38 39 /* Apple (0x106b) */ 40 #define PCI_DEVICE_ID_APPLE_343S1201 0x0010 41 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e 42 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f 43 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022 44 #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f 45 46 /* Realtek (0x10ec) */ 47 #define PCI_DEVICE_ID_REALTEK_8029 0x8029 48 49 /* Xilinx (0x10ee) */ 50 #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300 51 52 /* Marvell (0x11ab) */ 53 #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620 54 55 /* QEMU/Bochs VGA (0x1234) */ 56 #define PCI_VENDOR_ID_QEMU 0x1234 57 #define PCI_DEVICE_ID_QEMU_VGA 0x1111 58 #define PCI_DEVICE_ID_QEMU_IPMI 0x1112 59 60 /* VMWare (0x15ad) */ 61 #define PCI_VENDOR_ID_VMWARE 0x15ad 62 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 63 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710 64 #define PCI_DEVICE_ID_VMWARE_NET 0x0720 65 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730 66 #define PCI_DEVICE_ID_VMWARE_PVSCSI 0x07C0 67 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729 68 #define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0 69 70 /* Intel (0x8086) */ 71 #define PCI_DEVICE_ID_INTEL_82551IT 0x1209 72 #define PCI_DEVICE_ID_INTEL_82557 0x1229 73 #define PCI_DEVICE_ID_INTEL_82801IR 0x2922 74 75 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */ 76 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 77 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 78 #define PCI_SUBDEVICE_ID_QEMU 0x1100 79 80 /* legacy virtio-pci devices */ 81 #define PCI_DEVICE_ID_VIRTIO_NET 0x1000 82 #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001 83 #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002 84 #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003 85 #define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004 86 #define PCI_DEVICE_ID_VIRTIO_RNG 0x1005 87 #define PCI_DEVICE_ID_VIRTIO_9P 0x1009 88 #define PCI_DEVICE_ID_VIRTIO_VSOCK 0x1012 89 90 /* 91 * modern virtio-pci devices get their id assigned automatically, 92 * there is no need to add #defines here. It gets calculated as 93 * 94 * PCI_DEVICE_ID = PCI_DEVICE_ID_VIRTIO_10_BASE + 95 * virtio_bus_get_vdev_id(bus) 96 */ 97 #define PCI_DEVICE_ID_VIRTIO_10_BASE 0x1040 98 99 #define PCI_VENDOR_ID_REDHAT 0x1b36 100 #define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001 101 #define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002 102 #define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003 103 #define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004 104 #define PCI_DEVICE_ID_REDHAT_TEST 0x0005 105 #define PCI_DEVICE_ID_REDHAT_ROCKER 0x0006 106 #define PCI_DEVICE_ID_REDHAT_SDHCI 0x0007 107 #define PCI_DEVICE_ID_REDHAT_PCIE_HOST 0x0008 108 #define PCI_DEVICE_ID_REDHAT_PXB 0x0009 109 #define PCI_DEVICE_ID_REDHAT_BRIDGE_SEAT 0x000a 110 #define PCI_DEVICE_ID_REDHAT_PXB_PCIE 0x000b 111 #define PCI_DEVICE_ID_REDHAT_PCIE_RP 0x000c 112 #define PCI_DEVICE_ID_REDHAT_XHCI 0x000d 113 #define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000e 114 #define PCI_DEVICE_ID_REDHAT_MDPY 0x000f 115 #define PCI_DEVICE_ID_REDHAT_NVME 0x0010 116 #define PCI_DEVICE_ID_REDHAT_PVPANIC 0x0011 117 #define PCI_DEVICE_ID_REDHAT_ACPI_ERST 0x0012 118 #define PCI_DEVICE_ID_REDHAT_UFS 0x0013 119 #define PCI_DEVICE_ID_REDHAT_RISCV_IOMMU 0x0014 120 #define PCI_DEVICE_ID_REDHAT_QXL 0x0100 121 122 #define FMT_PCIBUS PRIx64 123 124 typedef uint64_t pcibus_t; 125 126 struct PCIHostDeviceAddress { 127 unsigned int domain; 128 unsigned int bus; 129 unsigned int slot; 130 unsigned int function; 131 }; 132 133 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, 134 uint32_t address, uint32_t data, int len); 135 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev, 136 uint32_t address, int len); 137 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, 138 pcibus_t addr, pcibus_t size, int type); 139 typedef void PCIUnregisterFunc(PCIDevice *pci_dev); 140 141 typedef void MSITriggerFunc(PCIDevice *dev, MSIMessage msg); 142 typedef MSIMessage MSIPrepareMessageFunc(PCIDevice *dev, unsigned vector); 143 typedef MSIMessage MSIxPrepareMessageFunc(PCIDevice *dev, unsigned vector); 144 145 typedef struct PCIIORegion { 146 pcibus_t addr; /* current PCI mapping address. -1 means not mapped */ 147 #define PCI_BAR_UNMAPPED (~(pcibus_t)0) 148 pcibus_t size; 149 uint8_t type; 150 MemoryRegion *memory; 151 MemoryRegion *address_space; 152 } PCIIORegion; 153 154 #define PCI_ROM_SLOT 6 155 #define PCI_NUM_REGIONS 7 156 157 enum { 158 QEMU_PCI_VGA_MEM, 159 QEMU_PCI_VGA_IO_LO, 160 QEMU_PCI_VGA_IO_HI, 161 QEMU_PCI_VGA_NUM_REGIONS, 162 }; 163 164 #define QEMU_PCI_VGA_MEM_BASE 0xa0000 165 #define QEMU_PCI_VGA_MEM_SIZE 0x20000 166 #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0 167 #define QEMU_PCI_VGA_IO_LO_SIZE 0xc 168 #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0 169 #define QEMU_PCI_VGA_IO_HI_SIZE 0x20 170 171 #include "hw/pci/pci_regs.h" 172 173 /* PCI HEADER_TYPE */ 174 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80 175 176 /* Size of the standard PCI config header */ 177 #define PCI_CONFIG_HEADER_SIZE 0x40 178 /* Size of the standard PCI config space */ 179 #define PCI_CONFIG_SPACE_SIZE 0x100 180 /* Size of the standard PCIe config space: 4KB */ 181 #define PCIE_CONFIG_SPACE_SIZE 0x1000 182 183 #define PCI_NUM_PINS 4 /* A-D */ 184 185 /* Bits in cap_present field. */ 186 enum { 187 QEMU_PCI_CAP_MSI = 0x1, 188 QEMU_PCI_CAP_MSIX = 0x2, 189 QEMU_PCI_CAP_EXPRESS = 0x4, 190 191 /* multifunction capable device */ 192 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3 193 QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR), 194 195 /* command register SERR bit enabled - unused since QEMU v5.0 */ 196 #define QEMU_PCI_CAP_SERR_BITNR 4 197 QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR), 198 /* Standard hot plug controller. */ 199 #define QEMU_PCI_SHPC_BITNR 5 200 QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR), 201 #define QEMU_PCI_SLOTID_BITNR 6 202 QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR), 203 /* PCI Express capability - Power Controller Present */ 204 #define QEMU_PCIE_SLTCAP_PCP_BITNR 7 205 QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR), 206 /* Link active status in endpoint capability is always set */ 207 #define QEMU_PCIE_LNKSTA_DLLLA_BITNR 8 208 QEMU_PCIE_LNKSTA_DLLLA = (1 << QEMU_PCIE_LNKSTA_DLLLA_BITNR), 209 #define QEMU_PCIE_EXTCAP_INIT_BITNR 9 210 QEMU_PCIE_EXTCAP_INIT = (1 << QEMU_PCIE_EXTCAP_INIT_BITNR), 211 #define QEMU_PCIE_CXL_BITNR 10 212 QEMU_PCIE_CAP_CXL = (1 << QEMU_PCIE_CXL_BITNR), 213 #define QEMU_PCIE_ERR_UNC_MASK_BITNR 11 214 QEMU_PCIE_ERR_UNC_MASK = (1 << QEMU_PCIE_ERR_UNC_MASK_BITNR), 215 #define QEMU_PCIE_ARI_NEXTFN_1_BITNR 12 216 QEMU_PCIE_ARI_NEXTFN_1 = (1 << QEMU_PCIE_ARI_NEXTFN_1_BITNR), 217 }; 218 219 typedef struct PCIINTxRoute { 220 enum { 221 PCI_INTX_ENABLED, 222 PCI_INTX_INVERTED, 223 PCI_INTX_DISABLED, 224 } mode; 225 int irq; 226 } PCIINTxRoute; 227 228 typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev); 229 typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector, 230 MSIMessage msg); 231 typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector); 232 typedef void (*MSIVectorPollNotifier)(PCIDevice *dev, 233 unsigned int vector_start, 234 unsigned int vector_end); 235 236 void pci_register_bar(PCIDevice *pci_dev, int region_num, 237 uint8_t attr, MemoryRegion *memory); 238 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, 239 MemoryRegion *io_lo, MemoryRegion *io_hi); 240 void pci_unregister_vga(PCIDevice *pci_dev); 241 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num); 242 243 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, 244 uint8_t offset, uint8_t size, 245 Error **errp); 246 247 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size); 248 249 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id); 250 251 252 uint32_t pci_default_read_config(PCIDevice *d, 253 uint32_t address, int len); 254 void pci_default_write_config(PCIDevice *d, 255 uint32_t address, uint32_t val, int len); 256 void pci_device_save(PCIDevice *s, QEMUFile *f); 257 int pci_device_load(PCIDevice *s, QEMUFile *f); 258 MemoryRegion *pci_address_space(PCIDevice *dev); 259 MemoryRegion *pci_address_space_io(PCIDevice *dev); 260 261 /* 262 * Should not normally be used by devices. For use by sPAPR target 263 * where QEMU emulates firmware. 264 */ 265 int pci_bar(PCIDevice *d, int reg); 266 267 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level); 268 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); 269 typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin); 270 271 #define TYPE_PCI_BUS "PCI" 272 OBJECT_DECLARE_TYPE(PCIBus, PCIBusClass, PCI_BUS) 273 #define TYPE_PCIE_BUS "PCIE" 274 #define TYPE_CXL_BUS "CXL" 275 276 typedef void (*pci_bus_dev_fn)(PCIBus *b, PCIDevice *d, void *opaque); 277 typedef void (*pci_bus_fn)(PCIBus *b, void *opaque); 278 typedef void *(*pci_bus_ret_fn)(PCIBus *b, void *opaque); 279 280 bool pci_bus_is_express(const PCIBus *bus); 281 282 void pci_root_bus_init(PCIBus *bus, size_t bus_size, DeviceState *parent, 283 const char *name, 284 MemoryRegion *mem, MemoryRegion *io, 285 uint8_t devfn_min, const char *typename); 286 PCIBus *pci_root_bus_new(DeviceState *parent, const char *name, 287 MemoryRegion *mem, MemoryRegion *io, 288 uint8_t devfn_min, const char *typename); 289 void pci_root_bus_cleanup(PCIBus *bus); 290 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, 291 void *irq_opaque, int nirq); 292 void pci_bus_map_irqs(PCIBus *bus, pci_map_irq_fn map_irq); 293 void pci_bus_irqs_cleanup(PCIBus *bus); 294 int pci_bus_get_irq_level(PCIBus *bus, int irq_num); 295 uint32_t pci_bus_get_slot_reserved_mask(PCIBus *bus); 296 void pci_bus_set_slot_reserved_mask(PCIBus *bus, uint32_t mask); 297 void pci_bus_clear_slot_reserved_mask(PCIBus *bus, uint32_t mask); 298 /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */ 299 static inline int pci_swizzle(int slot, int pin) 300 { 301 return (slot + pin) % PCI_NUM_PINS; 302 } 303 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin); 304 PCIBus *pci_register_root_bus(DeviceState *parent, const char *name, 305 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 306 void *irq_opaque, 307 MemoryRegion *mem, MemoryRegion *io, 308 uint8_t devfn_min, int nirq, 309 const char *typename); 310 void pci_unregister_root_bus(PCIBus *bus); 311 void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn); 312 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin); 313 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new); 314 void pci_bus_fire_intx_routing_notifier(PCIBus *bus); 315 void pci_device_set_intx_routing_notifier(PCIDevice *dev, 316 PCIINTxRoutingNotifier notifier); 317 void pci_device_reset(PCIDevice *dev); 318 319 void pci_init_nic_devices(PCIBus *bus, const char *default_model); 320 bool pci_init_nic_in_slot(PCIBus *rootbus, const char *default_model, 321 const char *alias, const char *devaddr); 322 PCIDevice *pci_vga_init(PCIBus *bus); 323 324 static inline PCIBus *pci_get_bus(const PCIDevice *dev) 325 { 326 return PCI_BUS(qdev_get_parent_bus(DEVICE(dev))); 327 } 328 int pci_bus_num(PCIBus *s); 329 void pci_bus_range(PCIBus *bus, int *min_bus, int *max_bus); 330 static inline int pci_dev_bus_num(const PCIDevice *dev) 331 { 332 return pci_bus_num(pci_get_bus(dev)); 333 } 334 335 int pci_bus_numa_node(PCIBus *bus); 336 void pci_for_each_device(PCIBus *bus, int bus_num, 337 pci_bus_dev_fn fn, 338 void *opaque); 339 void pci_for_each_device_reverse(PCIBus *bus, int bus_num, 340 pci_bus_dev_fn fn, 341 void *opaque); 342 void pci_for_each_device_under_bus(PCIBus *bus, 343 pci_bus_dev_fn fn, void *opaque); 344 void pci_for_each_device_under_bus_reverse(PCIBus *bus, 345 pci_bus_dev_fn fn, 346 void *opaque); 347 void pci_for_each_bus_depth_first(PCIBus *bus, pci_bus_ret_fn begin, 348 pci_bus_fn end, void *parent_state); 349 PCIDevice *pci_get_function_0(PCIDevice *pci_dev); 350 351 /* Use this wrapper when specific scan order is not required. */ 352 static inline 353 void pci_for_each_bus(PCIBus *bus, pci_bus_fn fn, void *opaque) 354 { 355 pci_for_each_bus_depth_first(bus, NULL, fn, opaque); 356 } 357 358 PCIBus *pci_device_root_bus(const PCIDevice *d); 359 const char *pci_root_bus_path(PCIDevice *dev); 360 bool pci_bus_bypass_iommu(PCIBus *bus); 361 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn); 362 int pci_qdev_find_device(const char *id, PCIDevice **pdev); 363 void pci_bus_get_w64_range(PCIBus *bus, Range *range); 364 365 void pci_device_deassert_intx(PCIDevice *dev); 366 367 368 /** 369 * struct PCIIOMMUOps: callbacks structure for specific IOMMU handlers 370 * of a PCIBus 371 * 372 * Allows to modify the behavior of some IOMMU operations of the PCI 373 * framework for a set of devices on a PCI bus. 374 */ 375 typedef struct PCIIOMMUOps { 376 /** 377 * @get_address_space: get the address space for a set of devices 378 * on a PCI bus. 379 * 380 * Mandatory callback which returns a pointer to an #AddressSpace 381 * 382 * @bus: the #PCIBus being accessed. 383 * 384 * @opaque: the data passed to pci_setup_iommu(). 385 * 386 * @devfn: device and function number 387 */ 388 AddressSpace * (*get_address_space)(PCIBus *bus, void *opaque, int devfn); 389 /** 390 * @set_iommu_device: attach a HostIOMMUDevice to a vIOMMU 391 * 392 * Optional callback, if not implemented in vIOMMU, then vIOMMU can't 393 * retrieve host information from the associated HostIOMMUDevice. 394 * 395 * @bus: the #PCIBus of the PCI device. 396 * 397 * @opaque: the data passed to pci_setup_iommu(). 398 * 399 * @devfn: device and function number of the PCI device. 400 * 401 * @dev: the #HostIOMMUDevice to attach. 402 * 403 * @errp: pass an Error out only when return false 404 * 405 * Returns: true if HostIOMMUDevice is attached or else false with errp set. 406 */ 407 bool (*set_iommu_device)(PCIBus *bus, void *opaque, int devfn, 408 HostIOMMUDevice *dev, Error **errp); 409 /** 410 * @unset_iommu_device: detach a HostIOMMUDevice from a vIOMMU 411 * 412 * Optional callback. 413 * 414 * @bus: the #PCIBus of the PCI device. 415 * 416 * @opaque: the data passed to pci_setup_iommu(). 417 * 418 * @devfn: device and function number of the PCI device. 419 */ 420 void (*unset_iommu_device)(PCIBus *bus, void *opaque, int devfn); 421 } PCIIOMMUOps; 422 423 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev); 424 bool pci_device_set_iommu_device(PCIDevice *dev, HostIOMMUDevice *hiod, 425 Error **errp); 426 void pci_device_unset_iommu_device(PCIDevice *dev); 427 428 /** 429 * pci_setup_iommu: Initialize specific IOMMU handlers for a PCIBus 430 * 431 * Let PCI host bridges define specific operations. 432 * 433 * @bus: the #PCIBus being updated. 434 * @ops: the #PCIIOMMUOps 435 * @opaque: passed to callbacks of the @ops structure. 436 */ 437 void pci_setup_iommu(PCIBus *bus, const PCIIOMMUOps *ops, void *opaque); 438 439 pcibus_t pci_bar_address(PCIDevice *d, 440 int reg, uint8_t type, pcibus_t size); 441 442 static inline void 443 pci_set_byte(uint8_t *config, uint8_t val) 444 { 445 *config = val; 446 } 447 448 static inline uint8_t 449 pci_get_byte(const uint8_t *config) 450 { 451 return *config; 452 } 453 454 static inline void 455 pci_set_word(uint8_t *config, uint16_t val) 456 { 457 stw_le_p(config, val); 458 } 459 460 static inline uint16_t 461 pci_get_word(const uint8_t *config) 462 { 463 return lduw_le_p(config); 464 } 465 466 static inline void 467 pci_set_long(uint8_t *config, uint32_t val) 468 { 469 stl_le_p(config, val); 470 } 471 472 static inline uint32_t 473 pci_get_long(const uint8_t *config) 474 { 475 return ldl_le_p(config); 476 } 477 478 /* 479 * PCI capabilities and/or their fields 480 * are generally DWORD aligned only so 481 * mechanism used by pci_set/get_quad() 482 * must be tolerant to unaligned pointers 483 * 484 */ 485 static inline void 486 pci_set_quad(uint8_t *config, uint64_t val) 487 { 488 stq_le_p(config, val); 489 } 490 491 static inline uint64_t 492 pci_get_quad(const uint8_t *config) 493 { 494 return ldq_le_p(config); 495 } 496 497 static inline void 498 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val) 499 { 500 pci_set_word(&pci_config[PCI_VENDOR_ID], val); 501 } 502 503 static inline void 504 pci_config_set_device_id(uint8_t *pci_config, uint16_t val) 505 { 506 pci_set_word(&pci_config[PCI_DEVICE_ID], val); 507 } 508 509 static inline void 510 pci_config_set_revision(uint8_t *pci_config, uint8_t val) 511 { 512 pci_set_byte(&pci_config[PCI_REVISION_ID], val); 513 } 514 515 static inline void 516 pci_config_set_class(uint8_t *pci_config, uint16_t val) 517 { 518 pci_set_word(&pci_config[PCI_CLASS_DEVICE], val); 519 } 520 521 static inline void 522 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val) 523 { 524 pci_set_byte(&pci_config[PCI_CLASS_PROG], val); 525 } 526 527 static inline void 528 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val) 529 { 530 pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val); 531 } 532 533 /* 534 * helper functions to do bit mask operation on configuration space. 535 * Just to set bit, use test-and-set and discard returned value. 536 * Just to clear bit, use test-and-clear and discard returned value. 537 * NOTE: They aren't atomic. 538 */ 539 static inline uint8_t 540 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask) 541 { 542 uint8_t val = pci_get_byte(config); 543 pci_set_byte(config, val & ~mask); 544 return val & mask; 545 } 546 547 static inline uint8_t 548 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask) 549 { 550 uint8_t val = pci_get_byte(config); 551 pci_set_byte(config, val | mask); 552 return val & mask; 553 } 554 555 static inline uint16_t 556 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask) 557 { 558 uint16_t val = pci_get_word(config); 559 pci_set_word(config, val & ~mask); 560 return val & mask; 561 } 562 563 static inline uint16_t 564 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask) 565 { 566 uint16_t val = pci_get_word(config); 567 pci_set_word(config, val | mask); 568 return val & mask; 569 } 570 571 static inline uint32_t 572 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask) 573 { 574 uint32_t val = pci_get_long(config); 575 pci_set_long(config, val & ~mask); 576 return val & mask; 577 } 578 579 static inline uint32_t 580 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask) 581 { 582 uint32_t val = pci_get_long(config); 583 pci_set_long(config, val | mask); 584 return val & mask; 585 } 586 587 static inline uint64_t 588 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask) 589 { 590 uint64_t val = pci_get_quad(config); 591 pci_set_quad(config, val & ~mask); 592 return val & mask; 593 } 594 595 static inline uint64_t 596 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask) 597 { 598 uint64_t val = pci_get_quad(config); 599 pci_set_quad(config, val | mask); 600 return val & mask; 601 } 602 603 /* Access a register specified by a mask */ 604 static inline void 605 pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg) 606 { 607 uint8_t val = pci_get_byte(config); 608 uint8_t rval; 609 610 assert(mask); 611 rval = reg << ctz32(mask); 612 pci_set_byte(config, (~mask & val) | (mask & rval)); 613 } 614 615 static inline void 616 pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg) 617 { 618 uint16_t val = pci_get_word(config); 619 uint16_t rval; 620 621 assert(mask); 622 rval = reg << ctz32(mask); 623 pci_set_word(config, (~mask & val) | (mask & rval)); 624 } 625 626 static inline void 627 pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg) 628 { 629 uint32_t val = pci_get_long(config); 630 uint32_t rval; 631 632 assert(mask); 633 rval = reg << ctz32(mask); 634 pci_set_long(config, (~mask & val) | (mask & rval)); 635 } 636 637 static inline void 638 pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg) 639 { 640 uint64_t val = pci_get_quad(config); 641 uint64_t rval; 642 643 assert(mask); 644 rval = reg << ctz32(mask); 645 pci_set_quad(config, (~mask & val) | (mask & rval)); 646 } 647 648 PCIDevice *pci_new_multifunction(int devfn, const char *name); 649 PCIDevice *pci_new(int devfn, const char *name); 650 bool pci_realize_and_unref(PCIDevice *dev, PCIBus *bus, Error **errp); 651 652 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, 653 const char *name); 654 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name); 655 656 void lsi53c8xx_handle_legacy_cmdline(DeviceState *lsi_dev); 657 658 qemu_irq pci_allocate_irq(PCIDevice *pci_dev); 659 void pci_set_irq(PCIDevice *pci_dev, int level); 660 661 static inline void pci_irq_assert(PCIDevice *pci_dev) 662 { 663 pci_set_irq(pci_dev, 1); 664 } 665 666 static inline void pci_irq_deassert(PCIDevice *pci_dev) 667 { 668 pci_set_irq(pci_dev, 0); 669 } 670 671 /* 672 * FIXME: PCI does not work this way. 673 * All the callers to this method should be fixed. 674 */ 675 static inline void pci_irq_pulse(PCIDevice *pci_dev) 676 { 677 pci_irq_assert(pci_dev); 678 pci_irq_deassert(pci_dev); 679 } 680 681 MSIMessage pci_get_msi_message(PCIDevice *dev, int vector); 682 void pci_set_power(PCIDevice *pci_dev, bool state); 683 684 #endif 685