1 #ifndef QEMU_PCI_H 2 #define QEMU_PCI_H 3 4 #include "exec/memory.h" 5 #include "sysemu/dma.h" 6 7 /* PCI includes legacy ISA access. */ 8 #include "hw/isa/isa.h" 9 10 extern bool pci_available; 11 12 /* PCI bus */ 13 14 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 15 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 16 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 17 #define PCI_FUNC(devfn) ((devfn) & 0x07) 18 #define PCI_BUILD_BDF(bus, devfn) ((bus << 8) | (devfn)) 19 #define PCI_BDF_TO_DEVFN(x) ((x) & 0xff) 20 #define PCI_BUS_MAX 256 21 #define PCI_DEVFN_MAX 256 22 #define PCI_SLOT_MAX 32 23 #define PCI_FUNC_MAX 8 24 25 /* Class, Vendor and Device IDs from Linux's pci_ids.h */ 26 #include "hw/pci/pci_ids.h" 27 28 /* QEMU-specific Vendor and Device ID definitions */ 29 30 /* IBM (0x1014) */ 31 #define PCI_DEVICE_ID_IBM_440GX 0x027f 32 #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff 33 34 /* Hitachi (0x1054) */ 35 #define PCI_VENDOR_ID_HITACHI 0x1054 36 #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e 37 38 /* Apple (0x106b) */ 39 #define PCI_DEVICE_ID_APPLE_343S1201 0x0010 40 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e 41 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f 42 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022 43 #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f 44 45 /* Realtek (0x10ec) */ 46 #define PCI_DEVICE_ID_REALTEK_8029 0x8029 47 48 /* Xilinx (0x10ee) */ 49 #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300 50 51 /* Marvell (0x11ab) */ 52 #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620 53 54 /* QEMU/Bochs VGA (0x1234) */ 55 #define PCI_VENDOR_ID_QEMU 0x1234 56 #define PCI_DEVICE_ID_QEMU_VGA 0x1111 57 #define PCI_DEVICE_ID_QEMU_IPMI 0x1112 58 59 /* VMWare (0x15ad) */ 60 #define PCI_VENDOR_ID_VMWARE 0x15ad 61 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 62 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710 63 #define PCI_DEVICE_ID_VMWARE_NET 0x0720 64 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730 65 #define PCI_DEVICE_ID_VMWARE_PVSCSI 0x07C0 66 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729 67 #define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0 68 69 /* Intel (0x8086) */ 70 #define PCI_DEVICE_ID_INTEL_82551IT 0x1209 71 #define PCI_DEVICE_ID_INTEL_82557 0x1229 72 #define PCI_DEVICE_ID_INTEL_82801IR 0x2922 73 74 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */ 75 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 76 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 77 #define PCI_SUBDEVICE_ID_QEMU 0x1100 78 79 #define PCI_DEVICE_ID_VIRTIO_NET 0x1000 80 #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001 81 #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002 82 #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003 83 #define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004 84 #define PCI_DEVICE_ID_VIRTIO_RNG 0x1005 85 #define PCI_DEVICE_ID_VIRTIO_9P 0x1009 86 #define PCI_DEVICE_ID_VIRTIO_VSOCK 0x1012 87 88 #define PCI_VENDOR_ID_REDHAT 0x1b36 89 #define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001 90 #define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002 91 #define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003 92 #define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004 93 #define PCI_DEVICE_ID_REDHAT_TEST 0x0005 94 #define PCI_DEVICE_ID_REDHAT_ROCKER 0x0006 95 #define PCI_DEVICE_ID_REDHAT_SDHCI 0x0007 96 #define PCI_DEVICE_ID_REDHAT_PCIE_HOST 0x0008 97 #define PCI_DEVICE_ID_REDHAT_PXB 0x0009 98 #define PCI_DEVICE_ID_REDHAT_BRIDGE_SEAT 0x000a 99 #define PCI_DEVICE_ID_REDHAT_PXB_PCIE 0x000b 100 #define PCI_DEVICE_ID_REDHAT_PCIE_RP 0x000c 101 #define PCI_DEVICE_ID_REDHAT_XHCI 0x000d 102 #define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000e 103 #define PCI_DEVICE_ID_REDHAT_MDPY 0x000f 104 #define PCI_DEVICE_ID_REDHAT_NVME 0x0010 105 #define PCI_DEVICE_ID_REDHAT_PVPANIC 0x0011 106 #define PCI_DEVICE_ID_REDHAT_ACPI_ERST 0x0012 107 #define PCI_DEVICE_ID_REDHAT_QXL 0x0100 108 109 #define FMT_PCIBUS PRIx64 110 111 typedef uint64_t pcibus_t; 112 113 struct PCIHostDeviceAddress { 114 unsigned int domain; 115 unsigned int bus; 116 unsigned int slot; 117 unsigned int function; 118 }; 119 120 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, 121 uint32_t address, uint32_t data, int len); 122 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev, 123 uint32_t address, int len); 124 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, 125 pcibus_t addr, pcibus_t size, int type); 126 typedef void PCIUnregisterFunc(PCIDevice *pci_dev); 127 128 typedef void MSITriggerFunc(PCIDevice *dev, MSIMessage msg); 129 typedef MSIMessage MSIPrepareMessageFunc(PCIDevice *dev, unsigned vector); 130 typedef MSIMessage MSIxPrepareMessageFunc(PCIDevice *dev, unsigned vector); 131 132 typedef struct PCIIORegion { 133 pcibus_t addr; /* current PCI mapping address. -1 means not mapped */ 134 #define PCI_BAR_UNMAPPED (~(pcibus_t)0) 135 pcibus_t size; 136 uint8_t type; 137 MemoryRegion *memory; 138 MemoryRegion *address_space; 139 } PCIIORegion; 140 141 #define PCI_ROM_SLOT 6 142 #define PCI_NUM_REGIONS 7 143 144 enum { 145 QEMU_PCI_VGA_MEM, 146 QEMU_PCI_VGA_IO_LO, 147 QEMU_PCI_VGA_IO_HI, 148 QEMU_PCI_VGA_NUM_REGIONS, 149 }; 150 151 #define QEMU_PCI_VGA_MEM_BASE 0xa0000 152 #define QEMU_PCI_VGA_MEM_SIZE 0x20000 153 #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0 154 #define QEMU_PCI_VGA_IO_LO_SIZE 0xc 155 #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0 156 #define QEMU_PCI_VGA_IO_HI_SIZE 0x20 157 158 #include "hw/pci/pci_regs.h" 159 #include "hw/pci/pcie.h" 160 161 /* PCI HEADER_TYPE */ 162 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80 163 164 /* Size of the standard PCI config header */ 165 #define PCI_CONFIG_HEADER_SIZE 0x40 166 /* Size of the standard PCI config space */ 167 #define PCI_CONFIG_SPACE_SIZE 0x100 168 /* Size of the standard PCIe config space: 4KB */ 169 #define PCIE_CONFIG_SPACE_SIZE 0x1000 170 171 #define PCI_NUM_PINS 4 /* A-D */ 172 173 /* Bits in cap_present field. */ 174 enum { 175 QEMU_PCI_CAP_MSI = 0x1, 176 QEMU_PCI_CAP_MSIX = 0x2, 177 QEMU_PCI_CAP_EXPRESS = 0x4, 178 179 /* multifunction capable device */ 180 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3 181 QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR), 182 183 /* command register SERR bit enabled - unused since QEMU v5.0 */ 184 #define QEMU_PCI_CAP_SERR_BITNR 4 185 QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR), 186 /* Standard hot plug controller. */ 187 #define QEMU_PCI_SHPC_BITNR 5 188 QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR), 189 #define QEMU_PCI_SLOTID_BITNR 6 190 QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR), 191 /* PCI Express capability - Power Controller Present */ 192 #define QEMU_PCIE_SLTCAP_PCP_BITNR 7 193 QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR), 194 /* Link active status in endpoint capability is always set */ 195 #define QEMU_PCIE_LNKSTA_DLLLA_BITNR 8 196 QEMU_PCIE_LNKSTA_DLLLA = (1 << QEMU_PCIE_LNKSTA_DLLLA_BITNR), 197 #define QEMU_PCIE_EXTCAP_INIT_BITNR 9 198 QEMU_PCIE_EXTCAP_INIT = (1 << QEMU_PCIE_EXTCAP_INIT_BITNR), 199 #define QEMU_PCIE_CXL_BITNR 10 200 QEMU_PCIE_CAP_CXL = (1 << QEMU_PCIE_CXL_BITNR), 201 }; 202 203 #define TYPE_PCI_DEVICE "pci-device" 204 typedef struct PCIDeviceClass PCIDeviceClass; 205 DECLARE_OBJ_CHECKERS(PCIDevice, PCIDeviceClass, 206 PCI_DEVICE, TYPE_PCI_DEVICE) 207 208 /* 209 * Implemented by devices that can be plugged on CXL buses. In the spec, this is 210 * actually a "CXL Component, but we name it device to match the PCI naming. 211 */ 212 #define INTERFACE_CXL_DEVICE "cxl-device" 213 214 /* Implemented by devices that can be plugged on PCI Express buses */ 215 #define INTERFACE_PCIE_DEVICE "pci-express-device" 216 217 /* Implemented by devices that can be plugged on Conventional PCI buses */ 218 #define INTERFACE_CONVENTIONAL_PCI_DEVICE "conventional-pci-device" 219 220 typedef struct PCIINTxRoute { 221 enum { 222 PCI_INTX_ENABLED, 223 PCI_INTX_INVERTED, 224 PCI_INTX_DISABLED, 225 } mode; 226 int irq; 227 } PCIINTxRoute; 228 229 struct PCIDeviceClass { 230 DeviceClass parent_class; 231 232 void (*realize)(PCIDevice *dev, Error **errp); 233 PCIUnregisterFunc *exit; 234 PCIConfigReadFunc *config_read; 235 PCIConfigWriteFunc *config_write; 236 237 uint16_t vendor_id; 238 uint16_t device_id; 239 uint8_t revision; 240 uint16_t class_id; 241 uint16_t subsystem_vendor_id; /* only for header type = 0 */ 242 uint16_t subsystem_id; /* only for header type = 0 */ 243 244 /* 245 * pci-to-pci bridge or normal device. 246 * This doesn't mean pci host switch. 247 * When card bus bridge is supported, this would be enhanced. 248 */ 249 bool is_bridge; 250 251 /* rom bar */ 252 const char *romfile; 253 }; 254 255 typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev); 256 typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector, 257 MSIMessage msg); 258 typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector); 259 typedef void (*MSIVectorPollNotifier)(PCIDevice *dev, 260 unsigned int vector_start, 261 unsigned int vector_end); 262 263 enum PCIReqIDType { 264 PCI_REQ_ID_INVALID = 0, 265 PCI_REQ_ID_BDF, 266 PCI_REQ_ID_SECONDARY_BUS, 267 PCI_REQ_ID_MAX, 268 }; 269 typedef enum PCIReqIDType PCIReqIDType; 270 271 struct PCIReqIDCache { 272 PCIDevice *dev; 273 PCIReqIDType type; 274 }; 275 typedef struct PCIReqIDCache PCIReqIDCache; 276 277 struct PCIDevice { 278 DeviceState qdev; 279 bool partially_hotplugged; 280 bool has_power; 281 282 /* PCI config space */ 283 uint8_t *config; 284 285 /* Used to enable config checks on load. Note that writable bits are 286 * never checked even if set in cmask. */ 287 uint8_t *cmask; 288 289 /* Used to implement R/W bytes */ 290 uint8_t *wmask; 291 292 /* Used to implement RW1C(Write 1 to Clear) bytes */ 293 uint8_t *w1cmask; 294 295 /* Used to allocate config space for capabilities. */ 296 uint8_t *used; 297 298 /* the following fields are read only */ 299 int32_t devfn; 300 /* Cached device to fetch requester ID from, to avoid the PCI 301 * tree walking every time we invoke PCI request (e.g., 302 * MSI). For conventional PCI root complex, this field is 303 * meaningless. */ 304 PCIReqIDCache requester_id_cache; 305 char name[64]; 306 PCIIORegion io_regions[PCI_NUM_REGIONS]; 307 AddressSpace bus_master_as; 308 MemoryRegion bus_master_container_region; 309 MemoryRegion bus_master_enable_region; 310 311 /* do not access the following fields */ 312 PCIConfigReadFunc *config_read; 313 PCIConfigWriteFunc *config_write; 314 315 /* Legacy PCI VGA regions */ 316 MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS]; 317 bool has_vga; 318 319 /* Current IRQ levels. Used internally by the generic PCI code. */ 320 uint8_t irq_state; 321 322 /* Capability bits */ 323 uint32_t cap_present; 324 325 /* Offset of MSI-X capability in config space */ 326 uint8_t msix_cap; 327 328 /* MSI-X entries */ 329 int msix_entries_nr; 330 331 /* Space to store MSIX table & pending bit array */ 332 uint8_t *msix_table; 333 uint8_t *msix_pba; 334 335 /* May be used by INTx or MSI during interrupt notification */ 336 void *irq_opaque; 337 338 MSITriggerFunc *msi_trigger; 339 MSIPrepareMessageFunc *msi_prepare_message; 340 MSIxPrepareMessageFunc *msix_prepare_message; 341 342 /* MemoryRegion container for msix exclusive BAR setup */ 343 MemoryRegion msix_exclusive_bar; 344 /* Memory Regions for MSIX table and pending bit entries. */ 345 MemoryRegion msix_table_mmio; 346 MemoryRegion msix_pba_mmio; 347 /* Reference-count for entries actually in use by driver. */ 348 unsigned *msix_entry_used; 349 /* MSIX function mask set or MSIX disabled */ 350 bool msix_function_masked; 351 /* Version id needed for VMState */ 352 int32_t version_id; 353 354 /* Offset of MSI capability in config space */ 355 uint8_t msi_cap; 356 357 /* PCI Express */ 358 PCIExpressDevice exp; 359 360 /* SHPC */ 361 SHPCDevice *shpc; 362 363 /* Location of option rom */ 364 char *romfile; 365 uint32_t romsize; 366 bool has_rom; 367 MemoryRegion rom; 368 uint32_t rom_bar; 369 370 /* INTx routing notifier */ 371 PCIINTxRoutingNotifier intx_routing_notifier; 372 373 /* MSI-X notifiers */ 374 MSIVectorUseNotifier msix_vector_use_notifier; 375 MSIVectorReleaseNotifier msix_vector_release_notifier; 376 MSIVectorPollNotifier msix_vector_poll_notifier; 377 378 /* ID of standby device in net_failover pair */ 379 char *failover_pair_id; 380 uint32_t acpi_index; 381 }; 382 383 void pci_register_bar(PCIDevice *pci_dev, int region_num, 384 uint8_t attr, MemoryRegion *memory); 385 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, 386 MemoryRegion *io_lo, MemoryRegion *io_hi); 387 void pci_unregister_vga(PCIDevice *pci_dev); 388 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num); 389 390 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, 391 uint8_t offset, uint8_t size, 392 Error **errp); 393 394 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size); 395 396 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id); 397 398 399 uint32_t pci_default_read_config(PCIDevice *d, 400 uint32_t address, int len); 401 void pci_default_write_config(PCIDevice *d, 402 uint32_t address, uint32_t val, int len); 403 void pci_device_save(PCIDevice *s, QEMUFile *f); 404 int pci_device_load(PCIDevice *s, QEMUFile *f); 405 MemoryRegion *pci_address_space(PCIDevice *dev); 406 MemoryRegion *pci_address_space_io(PCIDevice *dev); 407 408 /* 409 * Should not normally be used by devices. For use by sPAPR target 410 * where QEMU emulates firmware. 411 */ 412 int pci_bar(PCIDevice *d, int reg); 413 414 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level); 415 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); 416 typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin); 417 418 #define TYPE_PCI_BUS "PCI" 419 OBJECT_DECLARE_TYPE(PCIBus, PCIBusClass, PCI_BUS) 420 #define TYPE_PCIE_BUS "PCIE" 421 #define TYPE_CXL_BUS "CXL" 422 423 typedef void (*pci_bus_dev_fn)(PCIBus *b, PCIDevice *d, void *opaque); 424 typedef void (*pci_bus_fn)(PCIBus *b, void *opaque); 425 typedef void *(*pci_bus_ret_fn)(PCIBus *b, void *opaque); 426 427 bool pci_bus_is_express(PCIBus *bus); 428 429 void pci_root_bus_init(PCIBus *bus, size_t bus_size, DeviceState *parent, 430 const char *name, 431 MemoryRegion *address_space_mem, 432 MemoryRegion *address_space_io, 433 uint8_t devfn_min, const char *typename); 434 PCIBus *pci_root_bus_new(DeviceState *parent, const char *name, 435 MemoryRegion *address_space_mem, 436 MemoryRegion *address_space_io, 437 uint8_t devfn_min, const char *typename); 438 void pci_root_bus_cleanup(PCIBus *bus); 439 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 440 void *irq_opaque, int nirq); 441 void pci_bus_irqs_cleanup(PCIBus *bus); 442 int pci_bus_get_irq_level(PCIBus *bus, int irq_num); 443 /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */ 444 static inline int pci_swizzle(int slot, int pin) 445 { 446 return (slot + pin) % PCI_NUM_PINS; 447 } 448 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin); 449 PCIBus *pci_register_root_bus(DeviceState *parent, const char *name, 450 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 451 void *irq_opaque, 452 MemoryRegion *address_space_mem, 453 MemoryRegion *address_space_io, 454 uint8_t devfn_min, int nirq, 455 const char *typename); 456 void pci_unregister_root_bus(PCIBus *bus); 457 void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn); 458 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin); 459 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new); 460 void pci_bus_fire_intx_routing_notifier(PCIBus *bus); 461 void pci_device_set_intx_routing_notifier(PCIDevice *dev, 462 PCIINTxRoutingNotifier notifier); 463 void pci_device_reset(PCIDevice *dev); 464 465 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus, 466 const char *default_model, 467 const char *default_devaddr); 468 469 PCIDevice *pci_vga_init(PCIBus *bus); 470 471 static inline PCIBus *pci_get_bus(const PCIDevice *dev) 472 { 473 return PCI_BUS(qdev_get_parent_bus(DEVICE(dev))); 474 } 475 int pci_bus_num(PCIBus *s); 476 void pci_bus_range(PCIBus *bus, int *min_bus, int *max_bus); 477 static inline int pci_dev_bus_num(const PCIDevice *dev) 478 { 479 return pci_bus_num(pci_get_bus(dev)); 480 } 481 482 int pci_bus_numa_node(PCIBus *bus); 483 void pci_for_each_device(PCIBus *bus, int bus_num, 484 pci_bus_dev_fn fn, 485 void *opaque); 486 void pci_for_each_device_reverse(PCIBus *bus, int bus_num, 487 pci_bus_dev_fn fn, 488 void *opaque); 489 void pci_for_each_device_under_bus(PCIBus *bus, 490 pci_bus_dev_fn fn, void *opaque); 491 void pci_for_each_device_under_bus_reverse(PCIBus *bus, 492 pci_bus_dev_fn fn, 493 void *opaque); 494 void pci_for_each_bus_depth_first(PCIBus *bus, pci_bus_ret_fn begin, 495 pci_bus_fn end, void *parent_state); 496 PCIDevice *pci_get_function_0(PCIDevice *pci_dev); 497 498 /* Use this wrapper when specific scan order is not required. */ 499 static inline 500 void pci_for_each_bus(PCIBus *bus, pci_bus_fn fn, void *opaque) 501 { 502 pci_for_each_bus_depth_first(bus, NULL, fn, opaque); 503 } 504 505 PCIBus *pci_device_root_bus(const PCIDevice *d); 506 const char *pci_root_bus_path(PCIDevice *dev); 507 bool pci_bus_bypass_iommu(PCIBus *bus); 508 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn); 509 int pci_qdev_find_device(const char *id, PCIDevice **pdev); 510 void pci_bus_get_w64_range(PCIBus *bus, Range *range); 511 512 void pci_device_deassert_intx(PCIDevice *dev); 513 514 typedef AddressSpace *(*PCIIOMMUFunc)(PCIBus *, void *, int); 515 516 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev); 517 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque); 518 519 pcibus_t pci_bar_address(PCIDevice *d, 520 int reg, uint8_t type, pcibus_t size); 521 522 static inline void 523 pci_set_byte(uint8_t *config, uint8_t val) 524 { 525 *config = val; 526 } 527 528 static inline uint8_t 529 pci_get_byte(const uint8_t *config) 530 { 531 return *config; 532 } 533 534 static inline void 535 pci_set_word(uint8_t *config, uint16_t val) 536 { 537 stw_le_p(config, val); 538 } 539 540 static inline uint16_t 541 pci_get_word(const uint8_t *config) 542 { 543 return lduw_le_p(config); 544 } 545 546 static inline void 547 pci_set_long(uint8_t *config, uint32_t val) 548 { 549 stl_le_p(config, val); 550 } 551 552 static inline uint32_t 553 pci_get_long(const uint8_t *config) 554 { 555 return ldl_le_p(config); 556 } 557 558 /* 559 * PCI capabilities and/or their fields 560 * are generally DWORD aligned only so 561 * mechanism used by pci_set/get_quad() 562 * must be tolerant to unaligned pointers 563 * 564 */ 565 static inline void 566 pci_set_quad(uint8_t *config, uint64_t val) 567 { 568 stq_le_p(config, val); 569 } 570 571 static inline uint64_t 572 pci_get_quad(const uint8_t *config) 573 { 574 return ldq_le_p(config); 575 } 576 577 static inline void 578 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val) 579 { 580 pci_set_word(&pci_config[PCI_VENDOR_ID], val); 581 } 582 583 static inline void 584 pci_config_set_device_id(uint8_t *pci_config, uint16_t val) 585 { 586 pci_set_word(&pci_config[PCI_DEVICE_ID], val); 587 } 588 589 static inline void 590 pci_config_set_revision(uint8_t *pci_config, uint8_t val) 591 { 592 pci_set_byte(&pci_config[PCI_REVISION_ID], val); 593 } 594 595 static inline void 596 pci_config_set_class(uint8_t *pci_config, uint16_t val) 597 { 598 pci_set_word(&pci_config[PCI_CLASS_DEVICE], val); 599 } 600 601 static inline void 602 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val) 603 { 604 pci_set_byte(&pci_config[PCI_CLASS_PROG], val); 605 } 606 607 static inline void 608 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val) 609 { 610 pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val); 611 } 612 613 /* 614 * helper functions to do bit mask operation on configuration space. 615 * Just to set bit, use test-and-set and discard returned value. 616 * Just to clear bit, use test-and-clear and discard returned value. 617 * NOTE: They aren't atomic. 618 */ 619 static inline uint8_t 620 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask) 621 { 622 uint8_t val = pci_get_byte(config); 623 pci_set_byte(config, val & ~mask); 624 return val & mask; 625 } 626 627 static inline uint8_t 628 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask) 629 { 630 uint8_t val = pci_get_byte(config); 631 pci_set_byte(config, val | mask); 632 return val & mask; 633 } 634 635 static inline uint16_t 636 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask) 637 { 638 uint16_t val = pci_get_word(config); 639 pci_set_word(config, val & ~mask); 640 return val & mask; 641 } 642 643 static inline uint16_t 644 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask) 645 { 646 uint16_t val = pci_get_word(config); 647 pci_set_word(config, val | mask); 648 return val & mask; 649 } 650 651 static inline uint32_t 652 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask) 653 { 654 uint32_t val = pci_get_long(config); 655 pci_set_long(config, val & ~mask); 656 return val & mask; 657 } 658 659 static inline uint32_t 660 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask) 661 { 662 uint32_t val = pci_get_long(config); 663 pci_set_long(config, val | mask); 664 return val & mask; 665 } 666 667 static inline uint64_t 668 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask) 669 { 670 uint64_t val = pci_get_quad(config); 671 pci_set_quad(config, val & ~mask); 672 return val & mask; 673 } 674 675 static inline uint64_t 676 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask) 677 { 678 uint64_t val = pci_get_quad(config); 679 pci_set_quad(config, val | mask); 680 return val & mask; 681 } 682 683 /* Access a register specified by a mask */ 684 static inline void 685 pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg) 686 { 687 uint8_t val = pci_get_byte(config); 688 uint8_t rval = reg << ctz32(mask); 689 pci_set_byte(config, (~mask & val) | (mask & rval)); 690 } 691 692 static inline uint8_t 693 pci_get_byte_by_mask(uint8_t *config, uint8_t mask) 694 { 695 uint8_t val = pci_get_byte(config); 696 return (val & mask) >> ctz32(mask); 697 } 698 699 static inline void 700 pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg) 701 { 702 uint16_t val = pci_get_word(config); 703 uint16_t rval = reg << ctz32(mask); 704 pci_set_word(config, (~mask & val) | (mask & rval)); 705 } 706 707 static inline uint16_t 708 pci_get_word_by_mask(uint8_t *config, uint16_t mask) 709 { 710 uint16_t val = pci_get_word(config); 711 return (val & mask) >> ctz32(mask); 712 } 713 714 static inline void 715 pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg) 716 { 717 uint32_t val = pci_get_long(config); 718 uint32_t rval = reg << ctz32(mask); 719 pci_set_long(config, (~mask & val) | (mask & rval)); 720 } 721 722 static inline uint32_t 723 pci_get_long_by_mask(uint8_t *config, uint32_t mask) 724 { 725 uint32_t val = pci_get_long(config); 726 return (val & mask) >> ctz32(mask); 727 } 728 729 static inline void 730 pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg) 731 { 732 uint64_t val = pci_get_quad(config); 733 uint64_t rval = reg << ctz32(mask); 734 pci_set_quad(config, (~mask & val) | (mask & rval)); 735 } 736 737 static inline uint64_t 738 pci_get_quad_by_mask(uint8_t *config, uint64_t mask) 739 { 740 uint64_t val = pci_get_quad(config); 741 return (val & mask) >> ctz32(mask); 742 } 743 744 PCIDevice *pci_new_multifunction(int devfn, bool multifunction, 745 const char *name); 746 PCIDevice *pci_new(int devfn, const char *name); 747 bool pci_realize_and_unref(PCIDevice *dev, PCIBus *bus, Error **errp); 748 749 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, 750 bool multifunction, 751 const char *name); 752 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name); 753 754 void lsi53c8xx_handle_legacy_cmdline(DeviceState *lsi_dev); 755 756 qemu_irq pci_allocate_irq(PCIDevice *pci_dev); 757 void pci_set_irq(PCIDevice *pci_dev, int level); 758 759 static inline int pci_intx(PCIDevice *pci_dev) 760 { 761 return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1; 762 } 763 764 static inline void pci_irq_assert(PCIDevice *pci_dev) 765 { 766 pci_set_irq(pci_dev, 1); 767 } 768 769 static inline void pci_irq_deassert(PCIDevice *pci_dev) 770 { 771 pci_set_irq(pci_dev, 0); 772 } 773 774 /* 775 * FIXME: PCI does not work this way. 776 * All the callers to this method should be fixed. 777 */ 778 static inline void pci_irq_pulse(PCIDevice *pci_dev) 779 { 780 pci_irq_assert(pci_dev); 781 pci_irq_deassert(pci_dev); 782 } 783 784 static inline int pci_is_cxl(const PCIDevice *d) 785 { 786 return d->cap_present & QEMU_PCIE_CAP_CXL; 787 } 788 789 static inline int pci_is_express(const PCIDevice *d) 790 { 791 return d->cap_present & QEMU_PCI_CAP_EXPRESS; 792 } 793 794 static inline int pci_is_express_downstream_port(const PCIDevice *d) 795 { 796 uint8_t type; 797 798 if (!pci_is_express(d) || !d->exp.exp_cap) { 799 return 0; 800 } 801 802 type = pcie_cap_get_type(d); 803 804 return type == PCI_EXP_TYPE_DOWNSTREAM || type == PCI_EXP_TYPE_ROOT_PORT; 805 } 806 807 static inline int pci_is_vf(const PCIDevice *d) 808 { 809 return d->exp.sriov_vf.pf != NULL; 810 } 811 812 static inline uint32_t pci_config_size(const PCIDevice *d) 813 { 814 return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE; 815 } 816 817 static inline uint16_t pci_get_bdf(PCIDevice *dev) 818 { 819 return PCI_BUILD_BDF(pci_bus_num(pci_get_bus(dev)), dev->devfn); 820 } 821 822 uint16_t pci_requester_id(PCIDevice *dev); 823 824 /* DMA access functions */ 825 static inline AddressSpace *pci_get_address_space(PCIDevice *dev) 826 { 827 return &dev->bus_master_as; 828 } 829 830 /** 831 * pci_dma_rw: Read from or write to an address space from PCI device. 832 * 833 * Return a MemTxResult indicating whether the operation succeeded 834 * or failed (eg unassigned memory, device rejected the transaction, 835 * IOMMU fault). 836 * 837 * @dev: #PCIDevice doing the memory access 838 * @addr: address within the #PCIDevice address space 839 * @buf: buffer with the data transferred 840 * @len: the number of bytes to read or write 841 * @dir: indicates the transfer direction 842 */ 843 static inline MemTxResult pci_dma_rw(PCIDevice *dev, dma_addr_t addr, 844 void *buf, dma_addr_t len, 845 DMADirection dir, MemTxAttrs attrs) 846 { 847 return dma_memory_rw(pci_get_address_space(dev), addr, buf, len, 848 dir, attrs); 849 } 850 851 /** 852 * pci_dma_read: Read from an address space from PCI device. 853 * 854 * Return a MemTxResult indicating whether the operation succeeded 855 * or failed (eg unassigned memory, device rejected the transaction, 856 * IOMMU fault). Called within RCU critical section. 857 * 858 * @dev: #PCIDevice doing the memory access 859 * @addr: address within the #PCIDevice address space 860 * @buf: buffer with the data transferred 861 * @len: length of the data transferred 862 */ 863 static inline MemTxResult pci_dma_read(PCIDevice *dev, dma_addr_t addr, 864 void *buf, dma_addr_t len) 865 { 866 return pci_dma_rw(dev, addr, buf, len, 867 DMA_DIRECTION_TO_DEVICE, MEMTXATTRS_UNSPECIFIED); 868 } 869 870 /** 871 * pci_dma_write: Write to address space from PCI device. 872 * 873 * Return a MemTxResult indicating whether the operation succeeded 874 * or failed (eg unassigned memory, device rejected the transaction, 875 * IOMMU fault). 876 * 877 * @dev: #PCIDevice doing the memory access 878 * @addr: address within the #PCIDevice address space 879 * @buf: buffer with the data transferred 880 * @len: the number of bytes to write 881 */ 882 static inline MemTxResult pci_dma_write(PCIDevice *dev, dma_addr_t addr, 883 const void *buf, dma_addr_t len) 884 { 885 return pci_dma_rw(dev, addr, (void *) buf, len, 886 DMA_DIRECTION_FROM_DEVICE, MEMTXATTRS_UNSPECIFIED); 887 } 888 889 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \ 890 static inline MemTxResult ld##_l##_pci_dma(PCIDevice *dev, \ 891 dma_addr_t addr, \ 892 uint##_bits##_t *val, \ 893 MemTxAttrs attrs) \ 894 { \ 895 return ld##_l##_dma(pci_get_address_space(dev), addr, val, attrs); \ 896 } \ 897 static inline MemTxResult st##_s##_pci_dma(PCIDevice *dev, \ 898 dma_addr_t addr, \ 899 uint##_bits##_t val, \ 900 MemTxAttrs attrs) \ 901 { \ 902 return st##_s##_dma(pci_get_address_space(dev), addr, val, attrs); \ 903 } 904 905 PCI_DMA_DEFINE_LDST(ub, b, 8); 906 PCI_DMA_DEFINE_LDST(uw_le, w_le, 16) 907 PCI_DMA_DEFINE_LDST(l_le, l_le, 32); 908 PCI_DMA_DEFINE_LDST(q_le, q_le, 64); 909 PCI_DMA_DEFINE_LDST(uw_be, w_be, 16) 910 PCI_DMA_DEFINE_LDST(l_be, l_be, 32); 911 PCI_DMA_DEFINE_LDST(q_be, q_be, 64); 912 913 #undef PCI_DMA_DEFINE_LDST 914 915 /** 916 * pci_dma_map: Map device PCI address space range into host virtual address 917 * @dev: #PCIDevice to be accessed 918 * @addr: address within that device's address space 919 * @plen: pointer to length of buffer; updated on return to indicate 920 * if only a subset of the requested range has been mapped 921 * @dir: indicates the transfer direction 922 * 923 * Return: A host pointer, or %NULL if the resources needed to 924 * perform the mapping are exhausted (in that case *@plen 925 * is set to zero). 926 */ 927 static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr, 928 dma_addr_t *plen, DMADirection dir) 929 { 930 void *buf; 931 932 buf = dma_memory_map(pci_get_address_space(dev), addr, plen, dir, 933 MEMTXATTRS_UNSPECIFIED); 934 return buf; 935 } 936 937 static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len, 938 DMADirection dir, dma_addr_t access_len) 939 { 940 dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len); 941 } 942 943 static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev, 944 int alloc_hint) 945 { 946 qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev)); 947 } 948 949 extern const VMStateDescription vmstate_pci_device; 950 951 #define VMSTATE_PCI_DEVICE(_field, _state) { \ 952 .name = (stringify(_field)), \ 953 .size = sizeof(PCIDevice), \ 954 .vmsd = &vmstate_pci_device, \ 955 .flags = VMS_STRUCT, \ 956 .offset = vmstate_offset_value(_state, _field, PCIDevice), \ 957 } 958 959 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \ 960 .name = (stringify(_field)), \ 961 .size = sizeof(PCIDevice), \ 962 .vmsd = &vmstate_pci_device, \ 963 .flags = VMS_STRUCT|VMS_POINTER, \ 964 .offset = vmstate_offset_pointer(_state, _field, PCIDevice), \ 965 } 966 967 MSIMessage pci_get_msi_message(PCIDevice *dev, int vector); 968 void pci_set_power(PCIDevice *pci_dev, bool state); 969 970 #endif 971