1 #ifndef QEMU_PCI_H 2 #define QEMU_PCI_H 3 4 #include "exec/memory.h" 5 #include "sysemu/dma.h" 6 7 /* PCI includes legacy ISA access. */ 8 #include "hw/isa/isa.h" 9 10 extern bool pci_available; 11 12 /* PCI bus */ 13 14 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 15 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 16 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 17 #define PCI_FUNC(devfn) ((devfn) & 0x07) 18 #define PCI_BUILD_BDF(bus, devfn) ((bus << 8) | (devfn)) 19 #define PCI_BDF_TO_DEVFN(x) ((x) & 0xff) 20 #define PCI_BUS_MAX 256 21 #define PCI_DEVFN_MAX 256 22 #define PCI_SLOT_MAX 32 23 #define PCI_FUNC_MAX 8 24 25 /* Class, Vendor and Device IDs from Linux's pci_ids.h */ 26 #include "hw/pci/pci_ids.h" 27 28 /* QEMU-specific Vendor and Device ID definitions */ 29 30 /* IBM (0x1014) */ 31 #define PCI_DEVICE_ID_IBM_440GX 0x027f 32 #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff 33 34 /* Hitachi (0x1054) */ 35 #define PCI_VENDOR_ID_HITACHI 0x1054 36 #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e 37 38 /* Apple (0x106b) */ 39 #define PCI_DEVICE_ID_APPLE_343S1201 0x0010 40 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e 41 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f 42 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022 43 #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f 44 45 /* Realtek (0x10ec) */ 46 #define PCI_DEVICE_ID_REALTEK_8029 0x8029 47 48 /* Xilinx (0x10ee) */ 49 #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300 50 51 /* Marvell (0x11ab) */ 52 #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620 53 54 /* QEMU/Bochs VGA (0x1234) */ 55 #define PCI_VENDOR_ID_QEMU 0x1234 56 #define PCI_DEVICE_ID_QEMU_VGA 0x1111 57 #define PCI_DEVICE_ID_QEMU_IPMI 0x1112 58 59 /* VMWare (0x15ad) */ 60 #define PCI_VENDOR_ID_VMWARE 0x15ad 61 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 62 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710 63 #define PCI_DEVICE_ID_VMWARE_NET 0x0720 64 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730 65 #define PCI_DEVICE_ID_VMWARE_PVSCSI 0x07C0 66 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729 67 #define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0 68 69 /* Intel (0x8086) */ 70 #define PCI_DEVICE_ID_INTEL_82551IT 0x1209 71 #define PCI_DEVICE_ID_INTEL_82557 0x1229 72 #define PCI_DEVICE_ID_INTEL_82801IR 0x2922 73 74 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */ 75 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 76 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 77 #define PCI_SUBDEVICE_ID_QEMU 0x1100 78 79 /* legacy virtio-pci devices */ 80 #define PCI_DEVICE_ID_VIRTIO_NET 0x1000 81 #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001 82 #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002 83 #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003 84 #define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004 85 #define PCI_DEVICE_ID_VIRTIO_RNG 0x1005 86 #define PCI_DEVICE_ID_VIRTIO_9P 0x1009 87 #define PCI_DEVICE_ID_VIRTIO_VSOCK 0x1012 88 89 /* 90 * modern virtio-pci devices get their id assigned automatically, 91 * there is no need to add #defines here. It gets calculated as 92 * 93 * PCI_DEVICE_ID = PCI_DEVICE_ID_VIRTIO_10_BASE + 94 * virtio_bus_get_vdev_id(bus) 95 */ 96 #define PCI_DEVICE_ID_VIRTIO_10_BASE 0x1040 97 98 #define PCI_VENDOR_ID_REDHAT 0x1b36 99 #define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001 100 #define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002 101 #define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003 102 #define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004 103 #define PCI_DEVICE_ID_REDHAT_TEST 0x0005 104 #define PCI_DEVICE_ID_REDHAT_ROCKER 0x0006 105 #define PCI_DEVICE_ID_REDHAT_SDHCI 0x0007 106 #define PCI_DEVICE_ID_REDHAT_PCIE_HOST 0x0008 107 #define PCI_DEVICE_ID_REDHAT_PXB 0x0009 108 #define PCI_DEVICE_ID_REDHAT_BRIDGE_SEAT 0x000a 109 #define PCI_DEVICE_ID_REDHAT_PXB_PCIE 0x000b 110 #define PCI_DEVICE_ID_REDHAT_PCIE_RP 0x000c 111 #define PCI_DEVICE_ID_REDHAT_XHCI 0x000d 112 #define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000e 113 #define PCI_DEVICE_ID_REDHAT_MDPY 0x000f 114 #define PCI_DEVICE_ID_REDHAT_NVME 0x0010 115 #define PCI_DEVICE_ID_REDHAT_PVPANIC 0x0011 116 #define PCI_DEVICE_ID_REDHAT_ACPI_ERST 0x0012 117 #define PCI_DEVICE_ID_REDHAT_QXL 0x0100 118 119 #define FMT_PCIBUS PRIx64 120 121 typedef uint64_t pcibus_t; 122 123 struct PCIHostDeviceAddress { 124 unsigned int domain; 125 unsigned int bus; 126 unsigned int slot; 127 unsigned int function; 128 }; 129 130 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, 131 uint32_t address, uint32_t data, int len); 132 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev, 133 uint32_t address, int len); 134 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, 135 pcibus_t addr, pcibus_t size, int type); 136 typedef void PCIUnregisterFunc(PCIDevice *pci_dev); 137 138 typedef void MSITriggerFunc(PCIDevice *dev, MSIMessage msg); 139 typedef MSIMessage MSIPrepareMessageFunc(PCIDevice *dev, unsigned vector); 140 typedef MSIMessage MSIxPrepareMessageFunc(PCIDevice *dev, unsigned vector); 141 142 typedef struct PCIIORegion { 143 pcibus_t addr; /* current PCI mapping address. -1 means not mapped */ 144 #define PCI_BAR_UNMAPPED (~(pcibus_t)0) 145 pcibus_t size; 146 uint8_t type; 147 MemoryRegion *memory; 148 MemoryRegion *address_space; 149 } PCIIORegion; 150 151 #define PCI_ROM_SLOT 6 152 #define PCI_NUM_REGIONS 7 153 154 enum { 155 QEMU_PCI_VGA_MEM, 156 QEMU_PCI_VGA_IO_LO, 157 QEMU_PCI_VGA_IO_HI, 158 QEMU_PCI_VGA_NUM_REGIONS, 159 }; 160 161 #define QEMU_PCI_VGA_MEM_BASE 0xa0000 162 #define QEMU_PCI_VGA_MEM_SIZE 0x20000 163 #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0 164 #define QEMU_PCI_VGA_IO_LO_SIZE 0xc 165 #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0 166 #define QEMU_PCI_VGA_IO_HI_SIZE 0x20 167 168 #include "hw/pci/pci_regs.h" 169 170 /* PCI HEADER_TYPE */ 171 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80 172 173 /* Size of the standard PCI config header */ 174 #define PCI_CONFIG_HEADER_SIZE 0x40 175 /* Size of the standard PCI config space */ 176 #define PCI_CONFIG_SPACE_SIZE 0x100 177 /* Size of the standard PCIe config space: 4KB */ 178 #define PCIE_CONFIG_SPACE_SIZE 0x1000 179 180 #define PCI_NUM_PINS 4 /* A-D */ 181 182 /* Bits in cap_present field. */ 183 enum { 184 QEMU_PCI_CAP_MSI = 0x1, 185 QEMU_PCI_CAP_MSIX = 0x2, 186 QEMU_PCI_CAP_EXPRESS = 0x4, 187 188 /* multifunction capable device */ 189 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3 190 QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR), 191 192 /* command register SERR bit enabled - unused since QEMU v5.0 */ 193 #define QEMU_PCI_CAP_SERR_BITNR 4 194 QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR), 195 /* Standard hot plug controller. */ 196 #define QEMU_PCI_SHPC_BITNR 5 197 QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR), 198 #define QEMU_PCI_SLOTID_BITNR 6 199 QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR), 200 /* PCI Express capability - Power Controller Present */ 201 #define QEMU_PCIE_SLTCAP_PCP_BITNR 7 202 QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR), 203 /* Link active status in endpoint capability is always set */ 204 #define QEMU_PCIE_LNKSTA_DLLLA_BITNR 8 205 QEMU_PCIE_LNKSTA_DLLLA = (1 << QEMU_PCIE_LNKSTA_DLLLA_BITNR), 206 #define QEMU_PCIE_EXTCAP_INIT_BITNR 9 207 QEMU_PCIE_EXTCAP_INIT = (1 << QEMU_PCIE_EXTCAP_INIT_BITNR), 208 #define QEMU_PCIE_CXL_BITNR 10 209 QEMU_PCIE_CAP_CXL = (1 << QEMU_PCIE_CXL_BITNR), 210 }; 211 212 typedef struct PCIINTxRoute { 213 enum { 214 PCI_INTX_ENABLED, 215 PCI_INTX_INVERTED, 216 PCI_INTX_DISABLED, 217 } mode; 218 int irq; 219 } PCIINTxRoute; 220 221 typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev); 222 typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector, 223 MSIMessage msg); 224 typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector); 225 typedef void (*MSIVectorPollNotifier)(PCIDevice *dev, 226 unsigned int vector_start, 227 unsigned int vector_end); 228 229 void pci_register_bar(PCIDevice *pci_dev, int region_num, 230 uint8_t attr, MemoryRegion *memory); 231 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, 232 MemoryRegion *io_lo, MemoryRegion *io_hi); 233 void pci_unregister_vga(PCIDevice *pci_dev); 234 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num); 235 236 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, 237 uint8_t offset, uint8_t size, 238 Error **errp); 239 240 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size); 241 242 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id); 243 244 245 uint32_t pci_default_read_config(PCIDevice *d, 246 uint32_t address, int len); 247 void pci_default_write_config(PCIDevice *d, 248 uint32_t address, uint32_t val, int len); 249 void pci_device_save(PCIDevice *s, QEMUFile *f); 250 int pci_device_load(PCIDevice *s, QEMUFile *f); 251 MemoryRegion *pci_address_space(PCIDevice *dev); 252 MemoryRegion *pci_address_space_io(PCIDevice *dev); 253 254 /* 255 * Should not normally be used by devices. For use by sPAPR target 256 * where QEMU emulates firmware. 257 */ 258 int pci_bar(PCIDevice *d, int reg); 259 260 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level); 261 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); 262 typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin); 263 264 #define TYPE_PCI_BUS "PCI" 265 OBJECT_DECLARE_TYPE(PCIBus, PCIBusClass, PCI_BUS) 266 #define TYPE_PCIE_BUS "PCIE" 267 #define TYPE_CXL_BUS "CXL" 268 269 typedef void (*pci_bus_dev_fn)(PCIBus *b, PCIDevice *d, void *opaque); 270 typedef void (*pci_bus_fn)(PCIBus *b, void *opaque); 271 typedef void *(*pci_bus_ret_fn)(PCIBus *b, void *opaque); 272 273 bool pci_bus_is_express(const PCIBus *bus); 274 275 void pci_root_bus_init(PCIBus *bus, size_t bus_size, DeviceState *parent, 276 const char *name, 277 MemoryRegion *address_space_mem, 278 MemoryRegion *address_space_io, 279 uint8_t devfn_min, const char *typename); 280 PCIBus *pci_root_bus_new(DeviceState *parent, const char *name, 281 MemoryRegion *address_space_mem, 282 MemoryRegion *address_space_io, 283 uint8_t devfn_min, const char *typename); 284 void pci_root_bus_cleanup(PCIBus *bus); 285 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, 286 void *irq_opaque, int nirq); 287 void pci_bus_map_irqs(PCIBus *bus, pci_map_irq_fn map_irq); 288 void pci_bus_irqs_cleanup(PCIBus *bus); 289 int pci_bus_get_irq_level(PCIBus *bus, int irq_num); 290 uint32_t pci_bus_get_slot_reserved_mask(PCIBus *bus); 291 void pci_bus_set_slot_reserved_mask(PCIBus *bus, uint32_t mask); 292 void pci_bus_clear_slot_reserved_mask(PCIBus *bus, uint32_t mask); 293 /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */ 294 static inline int pci_swizzle(int slot, int pin) 295 { 296 return (slot + pin) % PCI_NUM_PINS; 297 } 298 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin); 299 PCIBus *pci_register_root_bus(DeviceState *parent, const char *name, 300 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 301 void *irq_opaque, 302 MemoryRegion *address_space_mem, 303 MemoryRegion *address_space_io, 304 uint8_t devfn_min, int nirq, 305 const char *typename); 306 void pci_unregister_root_bus(PCIBus *bus); 307 void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn); 308 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin); 309 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new); 310 void pci_bus_fire_intx_routing_notifier(PCIBus *bus); 311 void pci_device_set_intx_routing_notifier(PCIDevice *dev, 312 PCIINTxRoutingNotifier notifier); 313 void pci_device_reset(PCIDevice *dev); 314 315 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus, 316 const char *default_model, 317 const char *default_devaddr); 318 319 PCIDevice *pci_vga_init(PCIBus *bus); 320 321 static inline PCIBus *pci_get_bus(const PCIDevice *dev) 322 { 323 return PCI_BUS(qdev_get_parent_bus(DEVICE(dev))); 324 } 325 int pci_bus_num(PCIBus *s); 326 void pci_bus_range(PCIBus *bus, int *min_bus, int *max_bus); 327 static inline int pci_dev_bus_num(const PCIDevice *dev) 328 { 329 return pci_bus_num(pci_get_bus(dev)); 330 } 331 332 int pci_bus_numa_node(PCIBus *bus); 333 void pci_for_each_device(PCIBus *bus, int bus_num, 334 pci_bus_dev_fn fn, 335 void *opaque); 336 void pci_for_each_device_reverse(PCIBus *bus, int bus_num, 337 pci_bus_dev_fn fn, 338 void *opaque); 339 void pci_for_each_device_under_bus(PCIBus *bus, 340 pci_bus_dev_fn fn, void *opaque); 341 void pci_for_each_device_under_bus_reverse(PCIBus *bus, 342 pci_bus_dev_fn fn, 343 void *opaque); 344 void pci_for_each_bus_depth_first(PCIBus *bus, pci_bus_ret_fn begin, 345 pci_bus_fn end, void *parent_state); 346 PCIDevice *pci_get_function_0(PCIDevice *pci_dev); 347 348 /* Use this wrapper when specific scan order is not required. */ 349 static inline 350 void pci_for_each_bus(PCIBus *bus, pci_bus_fn fn, void *opaque) 351 { 352 pci_for_each_bus_depth_first(bus, NULL, fn, opaque); 353 } 354 355 PCIBus *pci_device_root_bus(const PCIDevice *d); 356 const char *pci_root_bus_path(PCIDevice *dev); 357 bool pci_bus_bypass_iommu(PCIBus *bus); 358 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn); 359 int pci_qdev_find_device(const char *id, PCIDevice **pdev); 360 void pci_bus_get_w64_range(PCIBus *bus, Range *range); 361 362 void pci_device_deassert_intx(PCIDevice *dev); 363 364 typedef AddressSpace *(*PCIIOMMUFunc)(PCIBus *, void *, int); 365 366 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev); 367 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque); 368 369 pcibus_t pci_bar_address(PCIDevice *d, 370 int reg, uint8_t type, pcibus_t size); 371 372 static inline void 373 pci_set_byte(uint8_t *config, uint8_t val) 374 { 375 *config = val; 376 } 377 378 static inline uint8_t 379 pci_get_byte(const uint8_t *config) 380 { 381 return *config; 382 } 383 384 static inline void 385 pci_set_word(uint8_t *config, uint16_t val) 386 { 387 stw_le_p(config, val); 388 } 389 390 static inline uint16_t 391 pci_get_word(const uint8_t *config) 392 { 393 return lduw_le_p(config); 394 } 395 396 static inline void 397 pci_set_long(uint8_t *config, uint32_t val) 398 { 399 stl_le_p(config, val); 400 } 401 402 static inline uint32_t 403 pci_get_long(const uint8_t *config) 404 { 405 return ldl_le_p(config); 406 } 407 408 /* 409 * PCI capabilities and/or their fields 410 * are generally DWORD aligned only so 411 * mechanism used by pci_set/get_quad() 412 * must be tolerant to unaligned pointers 413 * 414 */ 415 static inline void 416 pci_set_quad(uint8_t *config, uint64_t val) 417 { 418 stq_le_p(config, val); 419 } 420 421 static inline uint64_t 422 pci_get_quad(const uint8_t *config) 423 { 424 return ldq_le_p(config); 425 } 426 427 static inline void 428 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val) 429 { 430 pci_set_word(&pci_config[PCI_VENDOR_ID], val); 431 } 432 433 static inline void 434 pci_config_set_device_id(uint8_t *pci_config, uint16_t val) 435 { 436 pci_set_word(&pci_config[PCI_DEVICE_ID], val); 437 } 438 439 static inline void 440 pci_config_set_revision(uint8_t *pci_config, uint8_t val) 441 { 442 pci_set_byte(&pci_config[PCI_REVISION_ID], val); 443 } 444 445 static inline void 446 pci_config_set_class(uint8_t *pci_config, uint16_t val) 447 { 448 pci_set_word(&pci_config[PCI_CLASS_DEVICE], val); 449 } 450 451 static inline void 452 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val) 453 { 454 pci_set_byte(&pci_config[PCI_CLASS_PROG], val); 455 } 456 457 static inline void 458 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val) 459 { 460 pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val); 461 } 462 463 /* 464 * helper functions to do bit mask operation on configuration space. 465 * Just to set bit, use test-and-set and discard returned value. 466 * Just to clear bit, use test-and-clear and discard returned value. 467 * NOTE: They aren't atomic. 468 */ 469 static inline uint8_t 470 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask) 471 { 472 uint8_t val = pci_get_byte(config); 473 pci_set_byte(config, val & ~mask); 474 return val & mask; 475 } 476 477 static inline uint8_t 478 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask) 479 { 480 uint8_t val = pci_get_byte(config); 481 pci_set_byte(config, val | mask); 482 return val & mask; 483 } 484 485 static inline uint16_t 486 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask) 487 { 488 uint16_t val = pci_get_word(config); 489 pci_set_word(config, val & ~mask); 490 return val & mask; 491 } 492 493 static inline uint16_t 494 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask) 495 { 496 uint16_t val = pci_get_word(config); 497 pci_set_word(config, val | mask); 498 return val & mask; 499 } 500 501 static inline uint32_t 502 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask) 503 { 504 uint32_t val = pci_get_long(config); 505 pci_set_long(config, val & ~mask); 506 return val & mask; 507 } 508 509 static inline uint32_t 510 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask) 511 { 512 uint32_t val = pci_get_long(config); 513 pci_set_long(config, val | mask); 514 return val & mask; 515 } 516 517 static inline uint64_t 518 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask) 519 { 520 uint64_t val = pci_get_quad(config); 521 pci_set_quad(config, val & ~mask); 522 return val & mask; 523 } 524 525 static inline uint64_t 526 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask) 527 { 528 uint64_t val = pci_get_quad(config); 529 pci_set_quad(config, val | mask); 530 return val & mask; 531 } 532 533 /* Access a register specified by a mask */ 534 static inline void 535 pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg) 536 { 537 uint8_t val = pci_get_byte(config); 538 uint8_t rval; 539 540 assert(mask); 541 rval = reg << ctz32(mask); 542 pci_set_byte(config, (~mask & val) | (mask & rval)); 543 } 544 545 static inline void 546 pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg) 547 { 548 uint16_t val = pci_get_word(config); 549 uint16_t rval; 550 551 assert(mask); 552 rval = reg << ctz32(mask); 553 pci_set_word(config, (~mask & val) | (mask & rval)); 554 } 555 556 static inline void 557 pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg) 558 { 559 uint32_t val = pci_get_long(config); 560 uint32_t rval; 561 562 assert(mask); 563 rval = reg << ctz32(mask); 564 pci_set_long(config, (~mask & val) | (mask & rval)); 565 } 566 567 static inline void 568 pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg) 569 { 570 uint64_t val = pci_get_quad(config); 571 uint64_t rval; 572 573 assert(mask); 574 rval = reg << ctz32(mask); 575 pci_set_quad(config, (~mask & val) | (mask & rval)); 576 } 577 578 PCIDevice *pci_new_multifunction(int devfn, bool multifunction, 579 const char *name); 580 PCIDevice *pci_new(int devfn, const char *name); 581 bool pci_realize_and_unref(PCIDevice *dev, PCIBus *bus, Error **errp); 582 583 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, 584 bool multifunction, 585 const char *name); 586 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name); 587 588 void lsi53c8xx_handle_legacy_cmdline(DeviceState *lsi_dev); 589 590 qemu_irq pci_allocate_irq(PCIDevice *pci_dev); 591 void pci_set_irq(PCIDevice *pci_dev, int level); 592 593 static inline void pci_irq_assert(PCIDevice *pci_dev) 594 { 595 pci_set_irq(pci_dev, 1); 596 } 597 598 static inline void pci_irq_deassert(PCIDevice *pci_dev) 599 { 600 pci_set_irq(pci_dev, 0); 601 } 602 603 /* 604 * FIXME: PCI does not work this way. 605 * All the callers to this method should be fixed. 606 */ 607 static inline void pci_irq_pulse(PCIDevice *pci_dev) 608 { 609 pci_irq_assert(pci_dev); 610 pci_irq_deassert(pci_dev); 611 } 612 613 MSIMessage pci_get_msi_message(PCIDevice *dev, int vector); 614 void pci_set_power(PCIDevice *pci_dev, bool state); 615 616 #endif 617