1 #ifndef QEMU_PCI_H 2 #define QEMU_PCI_H 3 4 #include "qemu-common.h" 5 6 #include "hw/qdev.h" 7 #include "exec/memory.h" 8 #include "sysemu/dma.h" 9 10 /* PCI includes legacy ISA access. */ 11 #include "hw/isa/isa.h" 12 13 #include "hw/pci/pcie.h" 14 15 /* PCI bus */ 16 17 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 18 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 19 #define PCI_FUNC(devfn) ((devfn) & 0x07) 20 #define PCI_SLOT_MAX 32 21 #define PCI_FUNC_MAX 8 22 23 /* Class, Vendor and Device IDs from Linux's pci_ids.h */ 24 #include "hw/pci/pci_ids.h" 25 26 /* QEMU-specific Vendor and Device ID definitions */ 27 28 /* IBM (0x1014) */ 29 #define PCI_DEVICE_ID_IBM_440GX 0x027f 30 #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff 31 32 /* Hitachi (0x1054) */ 33 #define PCI_VENDOR_ID_HITACHI 0x1054 34 #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e 35 36 /* Apple (0x106b) */ 37 #define PCI_DEVICE_ID_APPLE_343S1201 0x0010 38 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e 39 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f 40 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022 41 #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f 42 43 /* Realtek (0x10ec) */ 44 #define PCI_DEVICE_ID_REALTEK_8029 0x8029 45 46 /* Xilinx (0x10ee) */ 47 #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300 48 49 /* Marvell (0x11ab) */ 50 #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620 51 52 /* QEMU/Bochs VGA (0x1234) */ 53 #define PCI_VENDOR_ID_QEMU 0x1234 54 #define PCI_DEVICE_ID_QEMU_VGA 0x1111 55 56 /* VMWare (0x15ad) */ 57 #define PCI_VENDOR_ID_VMWARE 0x15ad 58 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 59 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710 60 #define PCI_DEVICE_ID_VMWARE_NET 0x0720 61 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730 62 #define PCI_DEVICE_ID_VMWARE_PVSCSI 0x07C0 63 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729 64 #define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0 65 66 /* Intel (0x8086) */ 67 #define PCI_DEVICE_ID_INTEL_82551IT 0x1209 68 #define PCI_DEVICE_ID_INTEL_82557 0x1229 69 #define PCI_DEVICE_ID_INTEL_82801IR 0x2922 70 71 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */ 72 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 73 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 74 #define PCI_SUBDEVICE_ID_QEMU 0x1100 75 76 #define PCI_DEVICE_ID_VIRTIO_NET 0x1000 77 #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001 78 #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002 79 #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003 80 #define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004 81 #define PCI_DEVICE_ID_VIRTIO_RNG 0x1005 82 #define PCI_DEVICE_ID_VIRTIO_9P 0x1009 83 84 #define PCI_VENDOR_ID_REDHAT 0x1b36 85 #define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001 86 #define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002 87 #define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003 88 #define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004 89 #define PCI_DEVICE_ID_REDHAT_TEST 0x0005 90 #define PCI_DEVICE_ID_REDHAT_QXL 0x0100 91 92 #define FMT_PCIBUS PRIx64 93 94 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, 95 uint32_t address, uint32_t data, int len); 96 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev, 97 uint32_t address, int len); 98 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, 99 pcibus_t addr, pcibus_t size, int type); 100 typedef void PCIUnregisterFunc(PCIDevice *pci_dev); 101 102 typedef struct PCIIORegion { 103 pcibus_t addr; /* current PCI mapping address. -1 means not mapped */ 104 #define PCI_BAR_UNMAPPED (~(pcibus_t)0) 105 pcibus_t size; 106 uint8_t type; 107 MemoryRegion *memory; 108 MemoryRegion *address_space; 109 } PCIIORegion; 110 111 #define PCI_ROM_SLOT 6 112 #define PCI_NUM_REGIONS 7 113 114 enum { 115 QEMU_PCI_VGA_MEM, 116 QEMU_PCI_VGA_IO_LO, 117 QEMU_PCI_VGA_IO_HI, 118 QEMU_PCI_VGA_NUM_REGIONS, 119 }; 120 121 #define QEMU_PCI_VGA_MEM_BASE 0xa0000 122 #define QEMU_PCI_VGA_MEM_SIZE 0x20000 123 #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0 124 #define QEMU_PCI_VGA_IO_LO_SIZE 0xc 125 #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0 126 #define QEMU_PCI_VGA_IO_HI_SIZE 0x20 127 128 #include "hw/pci/pci_regs.h" 129 130 /* PCI HEADER_TYPE */ 131 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80 132 133 /* Size of the standard PCI config header */ 134 #define PCI_CONFIG_HEADER_SIZE 0x40 135 /* Size of the standard PCI config space */ 136 #define PCI_CONFIG_SPACE_SIZE 0x100 137 /* Size of the standart PCIe config space: 4KB */ 138 #define PCIE_CONFIG_SPACE_SIZE 0x1000 139 140 #define PCI_NUM_PINS 4 /* A-D */ 141 142 /* Bits in cap_present field. */ 143 enum { 144 QEMU_PCI_CAP_MSI = 0x1, 145 QEMU_PCI_CAP_MSIX = 0x2, 146 QEMU_PCI_CAP_EXPRESS = 0x4, 147 148 /* multifunction capable device */ 149 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3 150 QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR), 151 152 /* command register SERR bit enabled */ 153 #define QEMU_PCI_CAP_SERR_BITNR 4 154 QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR), 155 /* Standard hot plug controller. */ 156 #define QEMU_PCI_SHPC_BITNR 5 157 QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR), 158 #define QEMU_PCI_SLOTID_BITNR 6 159 QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR), 160 }; 161 162 #define TYPE_PCI_DEVICE "pci-device" 163 #define PCI_DEVICE(obj) \ 164 OBJECT_CHECK(PCIDevice, (obj), TYPE_PCI_DEVICE) 165 #define PCI_DEVICE_CLASS(klass) \ 166 OBJECT_CLASS_CHECK(PCIDeviceClass, (klass), TYPE_PCI_DEVICE) 167 #define PCI_DEVICE_GET_CLASS(obj) \ 168 OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE) 169 170 typedef struct PCIINTxRoute { 171 enum { 172 PCI_INTX_ENABLED, 173 PCI_INTX_INVERTED, 174 PCI_INTX_DISABLED, 175 } mode; 176 int irq; 177 } PCIINTxRoute; 178 179 typedef struct PCIDeviceClass { 180 DeviceClass parent_class; 181 182 int (*init)(PCIDevice *dev); 183 PCIUnregisterFunc *exit; 184 PCIConfigReadFunc *config_read; 185 PCIConfigWriteFunc *config_write; 186 187 uint16_t vendor_id; 188 uint16_t device_id; 189 uint8_t revision; 190 uint16_t class_id; 191 uint16_t subsystem_vendor_id; /* only for header type = 0 */ 192 uint16_t subsystem_id; /* only for header type = 0 */ 193 194 /* 195 * pci-to-pci bridge or normal device. 196 * This doesn't mean pci host switch. 197 * When card bus bridge is supported, this would be enhanced. 198 */ 199 int is_bridge; 200 201 /* pcie stuff */ 202 int is_express; /* is this device pci express? */ 203 204 /* device isn't hot-pluggable */ 205 int no_hotplug; 206 207 /* rom bar */ 208 const char *romfile; 209 } PCIDeviceClass; 210 211 typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev); 212 typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector, 213 MSIMessage msg); 214 typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector); 215 typedef void (*MSIVectorPollNotifier)(PCIDevice *dev, 216 unsigned int vector_start, 217 unsigned int vector_end); 218 219 struct PCIDevice { 220 DeviceState qdev; 221 222 /* PCI config space */ 223 uint8_t *config; 224 225 /* Used to enable config checks on load. Note that writable bits are 226 * never checked even if set in cmask. */ 227 uint8_t *cmask; 228 229 /* Used to implement R/W bytes */ 230 uint8_t *wmask; 231 232 /* Used to implement RW1C(Write 1 to Clear) bytes */ 233 uint8_t *w1cmask; 234 235 /* Used to allocate config space for capabilities. */ 236 uint8_t *used; 237 238 /* the following fields are read only */ 239 PCIBus *bus; 240 int32_t devfn; 241 char name[64]; 242 PCIIORegion io_regions[PCI_NUM_REGIONS]; 243 AddressSpace bus_master_as; 244 MemoryRegion bus_master_enable_region; 245 246 /* do not access the following fields */ 247 PCIConfigReadFunc *config_read; 248 PCIConfigWriteFunc *config_write; 249 250 /* Legacy PCI VGA regions */ 251 MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS]; 252 bool has_vga; 253 254 /* Current IRQ levels. Used internally by the generic PCI code. */ 255 uint8_t irq_state; 256 257 /* Capability bits */ 258 uint32_t cap_present; 259 260 /* Offset of MSI-X capability in config space */ 261 uint8_t msix_cap; 262 263 /* MSI-X entries */ 264 int msix_entries_nr; 265 266 /* Space to store MSIX table & pending bit array */ 267 uint8_t *msix_table; 268 uint8_t *msix_pba; 269 /* MemoryRegion container for msix exclusive BAR setup */ 270 MemoryRegion msix_exclusive_bar; 271 /* Memory Regions for MSIX table and pending bit entries. */ 272 MemoryRegion msix_table_mmio; 273 MemoryRegion msix_pba_mmio; 274 /* Reference-count for entries actually in use by driver. */ 275 unsigned *msix_entry_used; 276 /* MSIX function mask set or MSIX disabled */ 277 bool msix_function_masked; 278 /* Version id needed for VMState */ 279 int32_t version_id; 280 281 /* Offset of MSI capability in config space */ 282 uint8_t msi_cap; 283 284 /* PCI Express */ 285 PCIExpressDevice exp; 286 287 /* SHPC */ 288 SHPCDevice *shpc; 289 290 /* Location of option rom */ 291 char *romfile; 292 bool has_rom; 293 MemoryRegion rom; 294 uint32_t rom_bar; 295 296 /* INTx routing notifier */ 297 PCIINTxRoutingNotifier intx_routing_notifier; 298 299 /* MSI-X notifiers */ 300 MSIVectorUseNotifier msix_vector_use_notifier; 301 MSIVectorReleaseNotifier msix_vector_release_notifier; 302 MSIVectorPollNotifier msix_vector_poll_notifier; 303 }; 304 305 void pci_register_bar(PCIDevice *pci_dev, int region_num, 306 uint8_t attr, MemoryRegion *memory); 307 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, 308 MemoryRegion *io_lo, MemoryRegion *io_hi); 309 void pci_unregister_vga(PCIDevice *pci_dev); 310 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num); 311 312 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, 313 uint8_t offset, uint8_t size); 314 315 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size); 316 317 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id); 318 319 320 uint32_t pci_default_read_config(PCIDevice *d, 321 uint32_t address, int len); 322 void pci_default_write_config(PCIDevice *d, 323 uint32_t address, uint32_t val, int len); 324 void pci_device_save(PCIDevice *s, QEMUFile *f); 325 int pci_device_load(PCIDevice *s, QEMUFile *f); 326 MemoryRegion *pci_address_space(PCIDevice *dev); 327 MemoryRegion *pci_address_space_io(PCIDevice *dev); 328 329 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level); 330 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); 331 typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin); 332 333 typedef enum { 334 PCI_HOTPLUG_DISABLED, 335 PCI_HOTPLUG_ENABLED, 336 PCI_COLDPLUG_ENABLED, 337 } PCIHotplugState; 338 339 typedef int (*pci_hotplug_fn)(DeviceState *qdev, PCIDevice *pci_dev, 340 PCIHotplugState state); 341 342 #define TYPE_PCI_BUS "PCI" 343 #define PCI_BUS(obj) OBJECT_CHECK(PCIBus, (obj), TYPE_PCI_BUS) 344 #define TYPE_PCIE_BUS "PCIE" 345 346 bool pci_bus_is_express(PCIBus *bus); 347 bool pci_bus_is_root(PCIBus *bus); 348 void pci_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent, 349 const char *name, 350 MemoryRegion *address_space_mem, 351 MemoryRegion *address_space_io, 352 uint8_t devfn_min, const char *typename); 353 PCIBus *pci_bus_new(DeviceState *parent, const char *name, 354 MemoryRegion *address_space_mem, 355 MemoryRegion *address_space_io, 356 uint8_t devfn_min, const char *typename); 357 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 358 void *irq_opaque, int nirq); 359 int pci_bus_get_irq_level(PCIBus *bus, int irq_num); 360 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev); 361 /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */ 362 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin); 363 PCIBus *pci_register_bus(DeviceState *parent, const char *name, 364 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 365 void *irq_opaque, 366 MemoryRegion *address_space_mem, 367 MemoryRegion *address_space_io, 368 uint8_t devfn_min, int nirq, const char *typename); 369 void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn); 370 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin); 371 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new); 372 void pci_bus_fire_intx_routing_notifier(PCIBus *bus); 373 void pci_device_set_intx_routing_notifier(PCIDevice *dev, 374 PCIINTxRoutingNotifier notifier); 375 void pci_device_reset(PCIDevice *dev); 376 void pci_bus_reset(PCIBus *bus); 377 378 PCIDevice *pci_nic_init(NICInfo *nd, PCIBus *rootbus, 379 const char *default_model, 380 const char *default_devaddr); 381 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus, 382 const char *default_model, 383 const char *default_devaddr); 384 385 PCIDevice *pci_vga_init(PCIBus *bus); 386 387 int pci_bus_num(PCIBus *s); 388 void pci_for_each_device(PCIBus *bus, int bus_num, 389 void (*fn)(PCIBus *bus, PCIDevice *d, void *opaque), 390 void *opaque); 391 PCIBus *pci_find_primary_bus(void); 392 PCIBus *pci_device_root_bus(const PCIDevice *d); 393 const char *pci_root_bus_path(PCIDevice *dev); 394 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn); 395 int pci_qdev_find_device(const char *id, PCIDevice **pdev); 396 PCIBus *pci_get_bus_devfn(int *devfnp, PCIBus *root, const char *devaddr); 397 void pci_bus_get_w64_range(PCIBus *bus, Range *range); 398 399 int pci_parse_devaddr(const char *addr, int *domp, int *busp, 400 unsigned int *slotp, unsigned int *funcp); 401 402 void pci_device_deassert_intx(PCIDevice *dev); 403 404 typedef AddressSpace *(*PCIIOMMUFunc)(PCIBus *, void *, int); 405 406 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev); 407 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque); 408 409 static inline void 410 pci_set_byte(uint8_t *config, uint8_t val) 411 { 412 *config = val; 413 } 414 415 static inline uint8_t 416 pci_get_byte(const uint8_t *config) 417 { 418 return *config; 419 } 420 421 static inline void 422 pci_set_word(uint8_t *config, uint16_t val) 423 { 424 stw_le_p(config, val); 425 } 426 427 static inline uint16_t 428 pci_get_word(const uint8_t *config) 429 { 430 return lduw_le_p(config); 431 } 432 433 static inline void 434 pci_set_long(uint8_t *config, uint32_t val) 435 { 436 stl_le_p(config, val); 437 } 438 439 static inline uint32_t 440 pci_get_long(const uint8_t *config) 441 { 442 return ldl_le_p(config); 443 } 444 445 static inline void 446 pci_set_quad(uint8_t *config, uint64_t val) 447 { 448 cpu_to_le64w((uint64_t *)config, val); 449 } 450 451 static inline uint64_t 452 pci_get_quad(const uint8_t *config) 453 { 454 return le64_to_cpup((const uint64_t *)config); 455 } 456 457 static inline void 458 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val) 459 { 460 pci_set_word(&pci_config[PCI_VENDOR_ID], val); 461 } 462 463 static inline void 464 pci_config_set_device_id(uint8_t *pci_config, uint16_t val) 465 { 466 pci_set_word(&pci_config[PCI_DEVICE_ID], val); 467 } 468 469 static inline void 470 pci_config_set_revision(uint8_t *pci_config, uint8_t val) 471 { 472 pci_set_byte(&pci_config[PCI_REVISION_ID], val); 473 } 474 475 static inline void 476 pci_config_set_class(uint8_t *pci_config, uint16_t val) 477 { 478 pci_set_word(&pci_config[PCI_CLASS_DEVICE], val); 479 } 480 481 static inline void 482 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val) 483 { 484 pci_set_byte(&pci_config[PCI_CLASS_PROG], val); 485 } 486 487 static inline void 488 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val) 489 { 490 pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val); 491 } 492 493 /* 494 * helper functions to do bit mask operation on configuration space. 495 * Just to set bit, use test-and-set and discard returned value. 496 * Just to clear bit, use test-and-clear and discard returned value. 497 * NOTE: They aren't atomic. 498 */ 499 static inline uint8_t 500 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask) 501 { 502 uint8_t val = pci_get_byte(config); 503 pci_set_byte(config, val & ~mask); 504 return val & mask; 505 } 506 507 static inline uint8_t 508 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask) 509 { 510 uint8_t val = pci_get_byte(config); 511 pci_set_byte(config, val | mask); 512 return val & mask; 513 } 514 515 static inline uint16_t 516 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask) 517 { 518 uint16_t val = pci_get_word(config); 519 pci_set_word(config, val & ~mask); 520 return val & mask; 521 } 522 523 static inline uint16_t 524 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask) 525 { 526 uint16_t val = pci_get_word(config); 527 pci_set_word(config, val | mask); 528 return val & mask; 529 } 530 531 static inline uint32_t 532 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask) 533 { 534 uint32_t val = pci_get_long(config); 535 pci_set_long(config, val & ~mask); 536 return val & mask; 537 } 538 539 static inline uint32_t 540 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask) 541 { 542 uint32_t val = pci_get_long(config); 543 pci_set_long(config, val | mask); 544 return val & mask; 545 } 546 547 static inline uint64_t 548 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask) 549 { 550 uint64_t val = pci_get_quad(config); 551 pci_set_quad(config, val & ~mask); 552 return val & mask; 553 } 554 555 static inline uint64_t 556 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask) 557 { 558 uint64_t val = pci_get_quad(config); 559 pci_set_quad(config, val | mask); 560 return val & mask; 561 } 562 563 /* Access a register specified by a mask */ 564 static inline void 565 pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg) 566 { 567 uint8_t val = pci_get_byte(config); 568 uint8_t rval = reg << (ffs(mask) - 1); 569 pci_set_byte(config, (~mask & val) | (mask & rval)); 570 } 571 572 static inline uint8_t 573 pci_get_byte_by_mask(uint8_t *config, uint8_t mask) 574 { 575 uint8_t val = pci_get_byte(config); 576 return (val & mask) >> (ffs(mask) - 1); 577 } 578 579 static inline void 580 pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg) 581 { 582 uint16_t val = pci_get_word(config); 583 uint16_t rval = reg << (ffs(mask) - 1); 584 pci_set_word(config, (~mask & val) | (mask & rval)); 585 } 586 587 static inline uint16_t 588 pci_get_word_by_mask(uint8_t *config, uint16_t mask) 589 { 590 uint16_t val = pci_get_word(config); 591 return (val & mask) >> (ffs(mask) - 1); 592 } 593 594 static inline void 595 pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg) 596 { 597 uint32_t val = pci_get_long(config); 598 uint32_t rval = reg << (ffs(mask) - 1); 599 pci_set_long(config, (~mask & val) | (mask & rval)); 600 } 601 602 static inline uint32_t 603 pci_get_long_by_mask(uint8_t *config, uint32_t mask) 604 { 605 uint32_t val = pci_get_long(config); 606 return (val & mask) >> (ffs(mask) - 1); 607 } 608 609 static inline void 610 pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg) 611 { 612 uint64_t val = pci_get_quad(config); 613 uint64_t rval = reg << (ffs(mask) - 1); 614 pci_set_quad(config, (~mask & val) | (mask & rval)); 615 } 616 617 static inline uint64_t 618 pci_get_quad_by_mask(uint8_t *config, uint64_t mask) 619 { 620 uint64_t val = pci_get_quad(config); 621 return (val & mask) >> (ffs(mask) - 1); 622 } 623 624 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction, 625 const char *name); 626 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, 627 bool multifunction, 628 const char *name); 629 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name); 630 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name); 631 632 qemu_irq pci_allocate_irq(PCIDevice *pci_dev); 633 void pci_set_irq(PCIDevice *pci_dev, int level); 634 635 static inline void pci_irq_assert(PCIDevice *pci_dev) 636 { 637 pci_set_irq(pci_dev, 1); 638 } 639 640 static inline void pci_irq_deassert(PCIDevice *pci_dev) 641 { 642 pci_set_irq(pci_dev, 0); 643 } 644 645 /* 646 * FIXME: PCI does not work this way. 647 * All the callers to this method should be fixed. 648 */ 649 static inline void pci_irq_pulse(PCIDevice *pci_dev) 650 { 651 pci_irq_assert(pci_dev); 652 pci_irq_deassert(pci_dev); 653 } 654 655 static inline int pci_is_express(const PCIDevice *d) 656 { 657 return d->cap_present & QEMU_PCI_CAP_EXPRESS; 658 } 659 660 static inline uint32_t pci_config_size(const PCIDevice *d) 661 { 662 return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE; 663 } 664 665 /* DMA access functions */ 666 static inline AddressSpace *pci_get_address_space(PCIDevice *dev) 667 { 668 return &dev->bus_master_as; 669 } 670 671 static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr, 672 void *buf, dma_addr_t len, DMADirection dir) 673 { 674 dma_memory_rw(pci_get_address_space(dev), addr, buf, len, dir); 675 return 0; 676 } 677 678 static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr, 679 void *buf, dma_addr_t len) 680 { 681 return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE); 682 } 683 684 static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr, 685 const void *buf, dma_addr_t len) 686 { 687 return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE); 688 } 689 690 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \ 691 static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev, \ 692 dma_addr_t addr) \ 693 { \ 694 return ld##_l##_dma(pci_get_address_space(dev), addr); \ 695 } \ 696 static inline void st##_s##_pci_dma(PCIDevice *dev, \ 697 dma_addr_t addr, uint##_bits##_t val) \ 698 { \ 699 st##_s##_dma(pci_get_address_space(dev), addr, val); \ 700 } 701 702 PCI_DMA_DEFINE_LDST(ub, b, 8); 703 PCI_DMA_DEFINE_LDST(uw_le, w_le, 16) 704 PCI_DMA_DEFINE_LDST(l_le, l_le, 32); 705 PCI_DMA_DEFINE_LDST(q_le, q_le, 64); 706 PCI_DMA_DEFINE_LDST(uw_be, w_be, 16) 707 PCI_DMA_DEFINE_LDST(l_be, l_be, 32); 708 PCI_DMA_DEFINE_LDST(q_be, q_be, 64); 709 710 #undef PCI_DMA_DEFINE_LDST 711 712 static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr, 713 dma_addr_t *plen, DMADirection dir) 714 { 715 void *buf; 716 717 buf = dma_memory_map(pci_get_address_space(dev), addr, plen, dir); 718 return buf; 719 } 720 721 static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len, 722 DMADirection dir, dma_addr_t access_len) 723 { 724 dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len); 725 } 726 727 static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev, 728 int alloc_hint) 729 { 730 qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev)); 731 } 732 733 extern const VMStateDescription vmstate_pci_device; 734 735 #define VMSTATE_PCI_DEVICE(_field, _state) { \ 736 .name = (stringify(_field)), \ 737 .size = sizeof(PCIDevice), \ 738 .vmsd = &vmstate_pci_device, \ 739 .flags = VMS_STRUCT, \ 740 .offset = vmstate_offset_value(_state, _field, PCIDevice), \ 741 } 742 743 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \ 744 .name = (stringify(_field)), \ 745 .size = sizeof(PCIDevice), \ 746 .vmsd = &vmstate_pci_device, \ 747 .flags = VMS_STRUCT|VMS_POINTER, \ 748 .offset = vmstate_offset_pointer(_state, _field, PCIDevice), \ 749 } 750 751 #endif 752