1 #ifndef QEMU_PCI_H 2 #define QEMU_PCI_H 3 4 #include "qemu-common.h" 5 6 #include "hw/qdev.h" 7 #include "exec/memory.h" 8 #include "sysemu/dma.h" 9 10 /* PCI includes legacy ISA access. */ 11 #include "hw/isa/isa.h" 12 13 #include "hw/pci/pcie.h" 14 15 /* PCI bus */ 16 17 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 18 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 19 #define PCI_FUNC(devfn) ((devfn) & 0x07) 20 #define PCI_SLOT_MAX 32 21 #define PCI_FUNC_MAX 8 22 23 /* Class, Vendor and Device IDs from Linux's pci_ids.h */ 24 #include "hw/pci/pci_ids.h" 25 26 /* QEMU-specific Vendor and Device ID definitions */ 27 28 /* IBM (0x1014) */ 29 #define PCI_DEVICE_ID_IBM_440GX 0x027f 30 #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff 31 32 /* Hitachi (0x1054) */ 33 #define PCI_VENDOR_ID_HITACHI 0x1054 34 #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e 35 36 /* Apple (0x106b) */ 37 #define PCI_DEVICE_ID_APPLE_343S1201 0x0010 38 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e 39 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f 40 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022 41 #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f 42 43 /* Realtek (0x10ec) */ 44 #define PCI_DEVICE_ID_REALTEK_8029 0x8029 45 46 /* Xilinx (0x10ee) */ 47 #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300 48 49 /* Marvell (0x11ab) */ 50 #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620 51 52 /* QEMU/Bochs VGA (0x1234) */ 53 #define PCI_VENDOR_ID_QEMU 0x1234 54 #define PCI_DEVICE_ID_QEMU_VGA 0x1111 55 56 /* VMWare (0x15ad) */ 57 #define PCI_VENDOR_ID_VMWARE 0x15ad 58 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 59 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710 60 #define PCI_DEVICE_ID_VMWARE_NET 0x0720 61 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730 62 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729 63 #define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0 64 65 /* Intel (0x8086) */ 66 #define PCI_DEVICE_ID_INTEL_82551IT 0x1209 67 #define PCI_DEVICE_ID_INTEL_82557 0x1229 68 #define PCI_DEVICE_ID_INTEL_82801IR 0x2922 69 70 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */ 71 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 72 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 73 #define PCI_SUBDEVICE_ID_QEMU 0x1100 74 75 #define PCI_DEVICE_ID_VIRTIO_NET 0x1000 76 #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001 77 #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002 78 #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003 79 #define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004 80 #define PCI_DEVICE_ID_VIRTIO_RNG 0x1005 81 #define PCI_DEVICE_ID_VIRTIO_9P 0x1009 82 83 #define PCI_VENDOR_ID_REDHAT 0x1b36 84 #define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001 85 #define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002 86 #define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003 87 #define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004 88 #define PCI_DEVICE_ID_REDHAT_QXL 0x0100 89 90 #define FMT_PCIBUS PRIx64 91 92 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, 93 uint32_t address, uint32_t data, int len); 94 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev, 95 uint32_t address, int len); 96 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, 97 pcibus_t addr, pcibus_t size, int type); 98 typedef void PCIUnregisterFunc(PCIDevice *pci_dev); 99 100 typedef struct PCIIORegion { 101 pcibus_t addr; /* current PCI mapping address. -1 means not mapped */ 102 #define PCI_BAR_UNMAPPED (~(pcibus_t)0) 103 pcibus_t size; 104 uint8_t type; 105 MemoryRegion *memory; 106 MemoryRegion *address_space; 107 } PCIIORegion; 108 109 #define PCI_ROM_SLOT 6 110 #define PCI_NUM_REGIONS 7 111 112 enum { 113 QEMU_PCI_VGA_MEM, 114 QEMU_PCI_VGA_IO_LO, 115 QEMU_PCI_VGA_IO_HI, 116 QEMU_PCI_VGA_NUM_REGIONS, 117 }; 118 119 #define QEMU_PCI_VGA_MEM_BASE 0xa0000 120 #define QEMU_PCI_VGA_MEM_SIZE 0x20000 121 #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0 122 #define QEMU_PCI_VGA_IO_LO_SIZE 0xc 123 #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0 124 #define QEMU_PCI_VGA_IO_HI_SIZE 0x20 125 126 #include "hw/pci/pci_regs.h" 127 128 /* PCI HEADER_TYPE */ 129 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80 130 131 /* Size of the standard PCI config header */ 132 #define PCI_CONFIG_HEADER_SIZE 0x40 133 /* Size of the standard PCI config space */ 134 #define PCI_CONFIG_SPACE_SIZE 0x100 135 /* Size of the standart PCIe config space: 4KB */ 136 #define PCIE_CONFIG_SPACE_SIZE 0x1000 137 138 #define PCI_NUM_PINS 4 /* A-D */ 139 140 /* Bits in cap_present field. */ 141 enum { 142 QEMU_PCI_CAP_MSI = 0x1, 143 QEMU_PCI_CAP_MSIX = 0x2, 144 QEMU_PCI_CAP_EXPRESS = 0x4, 145 146 /* multifunction capable device */ 147 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3 148 QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR), 149 150 /* command register SERR bit enabled */ 151 #define QEMU_PCI_CAP_SERR_BITNR 4 152 QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR), 153 /* Standard hot plug controller. */ 154 #define QEMU_PCI_SHPC_BITNR 5 155 QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR), 156 #define QEMU_PCI_SLOTID_BITNR 6 157 QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR), 158 }; 159 160 #define TYPE_PCI_DEVICE "pci-device" 161 #define PCI_DEVICE(obj) \ 162 OBJECT_CHECK(PCIDevice, (obj), TYPE_PCI_DEVICE) 163 #define PCI_DEVICE_CLASS(klass) \ 164 OBJECT_CLASS_CHECK(PCIDeviceClass, (klass), TYPE_PCI_DEVICE) 165 #define PCI_DEVICE_GET_CLASS(obj) \ 166 OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE) 167 168 typedef struct PCIINTxRoute { 169 enum { 170 PCI_INTX_ENABLED, 171 PCI_INTX_INVERTED, 172 PCI_INTX_DISABLED, 173 } mode; 174 int irq; 175 } PCIINTxRoute; 176 177 typedef struct PCIDeviceClass { 178 DeviceClass parent_class; 179 180 int (*init)(PCIDevice *dev); 181 PCIUnregisterFunc *exit; 182 PCIConfigReadFunc *config_read; 183 PCIConfigWriteFunc *config_write; 184 185 uint16_t vendor_id; 186 uint16_t device_id; 187 uint8_t revision; 188 uint16_t class_id; 189 uint16_t subsystem_vendor_id; /* only for header type = 0 */ 190 uint16_t subsystem_id; /* only for header type = 0 */ 191 192 /* 193 * pci-to-pci bridge or normal device. 194 * This doesn't mean pci host switch. 195 * When card bus bridge is supported, this would be enhanced. 196 */ 197 int is_bridge; 198 199 /* pcie stuff */ 200 int is_express; /* is this device pci express? */ 201 202 /* device isn't hot-pluggable */ 203 int no_hotplug; 204 205 /* rom bar */ 206 const char *romfile; 207 } PCIDeviceClass; 208 209 typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev); 210 typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector, 211 MSIMessage msg); 212 typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector); 213 typedef void (*MSIVectorPollNotifier)(PCIDevice *dev, 214 unsigned int vector_start, 215 unsigned int vector_end); 216 217 struct PCIDevice { 218 DeviceState qdev; 219 220 /* PCI config space */ 221 uint8_t *config; 222 223 /* Used to enable config checks on load. Note that writable bits are 224 * never checked even if set in cmask. */ 225 uint8_t *cmask; 226 227 /* Used to implement R/W bytes */ 228 uint8_t *wmask; 229 230 /* Used to implement RW1C(Write 1 to Clear) bytes */ 231 uint8_t *w1cmask; 232 233 /* Used to allocate config space for capabilities. */ 234 uint8_t *used; 235 236 /* the following fields are read only */ 237 PCIBus *bus; 238 int32_t devfn; 239 char name[64]; 240 PCIIORegion io_regions[PCI_NUM_REGIONS]; 241 AddressSpace bus_master_as; 242 MemoryRegion bus_master_enable_region; 243 DMAContext *dma; 244 245 /* do not access the following fields */ 246 PCIConfigReadFunc *config_read; 247 PCIConfigWriteFunc *config_write; 248 249 /* IRQ objects for the INTA-INTD pins. */ 250 qemu_irq *irq; 251 252 /* Legacy PCI VGA regions */ 253 MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS]; 254 bool has_vga; 255 256 /* Current IRQ levels. Used internally by the generic PCI code. */ 257 uint8_t irq_state; 258 259 /* Capability bits */ 260 uint32_t cap_present; 261 262 /* Offset of MSI-X capability in config space */ 263 uint8_t msix_cap; 264 265 /* MSI-X entries */ 266 int msix_entries_nr; 267 268 /* Space to store MSIX table & pending bit array */ 269 uint8_t *msix_table; 270 uint8_t *msix_pba; 271 /* MemoryRegion container for msix exclusive BAR setup */ 272 MemoryRegion msix_exclusive_bar; 273 /* Memory Regions for MSIX table and pending bit entries. */ 274 MemoryRegion msix_table_mmio; 275 MemoryRegion msix_pba_mmio; 276 /* Reference-count for entries actually in use by driver. */ 277 unsigned *msix_entry_used; 278 /* MSIX function mask set or MSIX disabled */ 279 bool msix_function_masked; 280 /* Version id needed for VMState */ 281 int32_t version_id; 282 283 /* Offset of MSI capability in config space */ 284 uint8_t msi_cap; 285 286 /* PCI Express */ 287 PCIExpressDevice exp; 288 289 /* SHPC */ 290 SHPCDevice *shpc; 291 292 /* Location of option rom */ 293 char *romfile; 294 bool has_rom; 295 MemoryRegion rom; 296 uint32_t rom_bar; 297 298 /* INTx routing notifier */ 299 PCIINTxRoutingNotifier intx_routing_notifier; 300 301 /* MSI-X notifiers */ 302 MSIVectorUseNotifier msix_vector_use_notifier; 303 MSIVectorReleaseNotifier msix_vector_release_notifier; 304 MSIVectorPollNotifier msix_vector_poll_notifier; 305 }; 306 307 void pci_register_bar(PCIDevice *pci_dev, int region_num, 308 uint8_t attr, MemoryRegion *memory); 309 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, 310 MemoryRegion *io_lo, MemoryRegion *io_hi); 311 void pci_unregister_vga(PCIDevice *pci_dev); 312 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num); 313 314 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, 315 uint8_t offset, uint8_t size); 316 317 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size); 318 319 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id); 320 321 322 uint32_t pci_default_read_config(PCIDevice *d, 323 uint32_t address, int len); 324 void pci_default_write_config(PCIDevice *d, 325 uint32_t address, uint32_t val, int len); 326 void pci_device_save(PCIDevice *s, QEMUFile *f); 327 int pci_device_load(PCIDevice *s, QEMUFile *f); 328 MemoryRegion *pci_address_space(PCIDevice *dev); 329 MemoryRegion *pci_address_space_io(PCIDevice *dev); 330 331 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level); 332 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); 333 typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin); 334 335 typedef enum { 336 PCI_HOTPLUG_DISABLED, 337 PCI_HOTPLUG_ENABLED, 338 PCI_COLDPLUG_ENABLED, 339 } PCIHotplugState; 340 341 typedef int (*pci_hotplug_fn)(DeviceState *qdev, PCIDevice *pci_dev, 342 PCIHotplugState state); 343 344 #define TYPE_PCI_BUS "PCI" 345 #define PCI_BUS(obj) OBJECT_CHECK(PCIBus, (obj), TYPE_PCI_BUS) 346 #define TYPE_PCIE_BUS "PCIE" 347 348 bool pci_bus_is_express(PCIBus *bus); 349 bool pci_bus_is_root(PCIBus *bus); 350 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent, 351 const char *name, 352 MemoryRegion *address_space_mem, 353 MemoryRegion *address_space_io, 354 uint8_t devfn_min, const char *typename); 355 PCIBus *pci_bus_new(DeviceState *parent, const char *name, 356 MemoryRegion *address_space_mem, 357 MemoryRegion *address_space_io, 358 uint8_t devfn_min, const char *typename); 359 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 360 void *irq_opaque, int nirq); 361 int pci_bus_get_irq_level(PCIBus *bus, int irq_num); 362 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev); 363 /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */ 364 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin); 365 PCIBus *pci_register_bus(DeviceState *parent, const char *name, 366 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 367 void *irq_opaque, 368 MemoryRegion *address_space_mem, 369 MemoryRegion *address_space_io, 370 uint8_t devfn_min, int nirq, const char *typename); 371 void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn); 372 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin); 373 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new); 374 void pci_bus_fire_intx_routing_notifier(PCIBus *bus); 375 void pci_device_set_intx_routing_notifier(PCIDevice *dev, 376 PCIINTxRoutingNotifier notifier); 377 void pci_device_reset(PCIDevice *dev); 378 void pci_bus_reset(PCIBus *bus); 379 380 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model, 381 const char *default_devaddr); 382 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model, 383 const char *default_devaddr); 384 385 PCIDevice *pci_vga_init(PCIBus *bus); 386 387 int pci_bus_num(PCIBus *s); 388 void pci_for_each_device(PCIBus *bus, int bus_num, 389 void (*fn)(PCIBus *bus, PCIDevice *d, void *opaque), 390 void *opaque); 391 PCIBus *pci_find_root_bus(int domain); 392 int pci_find_domain(const PCIBus *bus); 393 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn); 394 int pci_qdev_find_device(const char *id, PCIDevice **pdev); 395 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr); 396 397 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp, 398 unsigned *slotp); 399 400 void pci_device_deassert_intx(PCIDevice *dev); 401 402 typedef DMAContext *(*PCIDMAContextFunc)(PCIBus *, void *, int); 403 404 void pci_setup_iommu(PCIBus *bus, PCIDMAContextFunc fn, void *opaque); 405 406 static inline void 407 pci_set_byte(uint8_t *config, uint8_t val) 408 { 409 *config = val; 410 } 411 412 static inline uint8_t 413 pci_get_byte(const uint8_t *config) 414 { 415 return *config; 416 } 417 418 static inline void 419 pci_set_word(uint8_t *config, uint16_t val) 420 { 421 cpu_to_le16wu((uint16_t *)config, val); 422 } 423 424 static inline uint16_t 425 pci_get_word(const uint8_t *config) 426 { 427 return le16_to_cpupu((const uint16_t *)config); 428 } 429 430 static inline void 431 pci_set_long(uint8_t *config, uint32_t val) 432 { 433 cpu_to_le32wu((uint32_t *)config, val); 434 } 435 436 static inline uint32_t 437 pci_get_long(const uint8_t *config) 438 { 439 return le32_to_cpupu((const uint32_t *)config); 440 } 441 442 static inline void 443 pci_set_quad(uint8_t *config, uint64_t val) 444 { 445 cpu_to_le64w((uint64_t *)config, val); 446 } 447 448 static inline uint64_t 449 pci_get_quad(const uint8_t *config) 450 { 451 return le64_to_cpup((const uint64_t *)config); 452 } 453 454 static inline void 455 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val) 456 { 457 pci_set_word(&pci_config[PCI_VENDOR_ID], val); 458 } 459 460 static inline void 461 pci_config_set_device_id(uint8_t *pci_config, uint16_t val) 462 { 463 pci_set_word(&pci_config[PCI_DEVICE_ID], val); 464 } 465 466 static inline void 467 pci_config_set_revision(uint8_t *pci_config, uint8_t val) 468 { 469 pci_set_byte(&pci_config[PCI_REVISION_ID], val); 470 } 471 472 static inline void 473 pci_config_set_class(uint8_t *pci_config, uint16_t val) 474 { 475 pci_set_word(&pci_config[PCI_CLASS_DEVICE], val); 476 } 477 478 static inline void 479 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val) 480 { 481 pci_set_byte(&pci_config[PCI_CLASS_PROG], val); 482 } 483 484 static inline void 485 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val) 486 { 487 pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val); 488 } 489 490 /* 491 * helper functions to do bit mask operation on configuration space. 492 * Just to set bit, use test-and-set and discard returned value. 493 * Just to clear bit, use test-and-clear and discard returned value. 494 * NOTE: They aren't atomic. 495 */ 496 static inline uint8_t 497 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask) 498 { 499 uint8_t val = pci_get_byte(config); 500 pci_set_byte(config, val & ~mask); 501 return val & mask; 502 } 503 504 static inline uint8_t 505 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask) 506 { 507 uint8_t val = pci_get_byte(config); 508 pci_set_byte(config, val | mask); 509 return val & mask; 510 } 511 512 static inline uint16_t 513 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask) 514 { 515 uint16_t val = pci_get_word(config); 516 pci_set_word(config, val & ~mask); 517 return val & mask; 518 } 519 520 static inline uint16_t 521 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask) 522 { 523 uint16_t val = pci_get_word(config); 524 pci_set_word(config, val | mask); 525 return val & mask; 526 } 527 528 static inline uint32_t 529 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask) 530 { 531 uint32_t val = pci_get_long(config); 532 pci_set_long(config, val & ~mask); 533 return val & mask; 534 } 535 536 static inline uint32_t 537 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask) 538 { 539 uint32_t val = pci_get_long(config); 540 pci_set_long(config, val | mask); 541 return val & mask; 542 } 543 544 static inline uint64_t 545 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask) 546 { 547 uint64_t val = pci_get_quad(config); 548 pci_set_quad(config, val & ~mask); 549 return val & mask; 550 } 551 552 static inline uint64_t 553 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask) 554 { 555 uint64_t val = pci_get_quad(config); 556 pci_set_quad(config, val | mask); 557 return val & mask; 558 } 559 560 /* Access a register specified by a mask */ 561 static inline void 562 pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg) 563 { 564 uint8_t val = pci_get_byte(config); 565 uint8_t rval = reg << (ffs(mask) - 1); 566 pci_set_byte(config, (~mask & val) | (mask & rval)); 567 } 568 569 static inline uint8_t 570 pci_get_byte_by_mask(uint8_t *config, uint8_t mask) 571 { 572 uint8_t val = pci_get_byte(config); 573 return (val & mask) >> (ffs(mask) - 1); 574 } 575 576 static inline void 577 pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg) 578 { 579 uint16_t val = pci_get_word(config); 580 uint16_t rval = reg << (ffs(mask) - 1); 581 pci_set_word(config, (~mask & val) | (mask & rval)); 582 } 583 584 static inline uint16_t 585 pci_get_word_by_mask(uint8_t *config, uint16_t mask) 586 { 587 uint16_t val = pci_get_word(config); 588 return (val & mask) >> (ffs(mask) - 1); 589 } 590 591 static inline void 592 pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg) 593 { 594 uint32_t val = pci_get_long(config); 595 uint32_t rval = reg << (ffs(mask) - 1); 596 pci_set_long(config, (~mask & val) | (mask & rval)); 597 } 598 599 static inline uint32_t 600 pci_get_long_by_mask(uint8_t *config, uint32_t mask) 601 { 602 uint32_t val = pci_get_long(config); 603 return (val & mask) >> (ffs(mask) - 1); 604 } 605 606 static inline void 607 pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg) 608 { 609 uint64_t val = pci_get_quad(config); 610 uint64_t rval = reg << (ffs(mask) - 1); 611 pci_set_quad(config, (~mask & val) | (mask & rval)); 612 } 613 614 static inline uint64_t 615 pci_get_quad_by_mask(uint8_t *config, uint64_t mask) 616 { 617 uint64_t val = pci_get_quad(config); 618 return (val & mask) >> (ffs(mask) - 1); 619 } 620 621 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction, 622 const char *name); 623 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, 624 bool multifunction, 625 const char *name); 626 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name); 627 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name); 628 629 static inline int pci_is_express(const PCIDevice *d) 630 { 631 return d->cap_present & QEMU_PCI_CAP_EXPRESS; 632 } 633 634 static inline uint32_t pci_config_size(const PCIDevice *d) 635 { 636 return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE; 637 } 638 639 /* DMA access functions */ 640 static inline DMAContext *pci_dma_context(PCIDevice *dev) 641 { 642 return dev->dma; 643 } 644 645 static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr, 646 void *buf, dma_addr_t len, DMADirection dir) 647 { 648 dma_memory_rw(pci_dma_context(dev), addr, buf, len, dir); 649 return 0; 650 } 651 652 static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr, 653 void *buf, dma_addr_t len) 654 { 655 return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE); 656 } 657 658 static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr, 659 const void *buf, dma_addr_t len) 660 { 661 return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE); 662 } 663 664 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \ 665 static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev, \ 666 dma_addr_t addr) \ 667 { \ 668 return ld##_l##_dma(pci_dma_context(dev), addr); \ 669 } \ 670 static inline void st##_s##_pci_dma(PCIDevice *dev, \ 671 dma_addr_t addr, uint##_bits##_t val) \ 672 { \ 673 st##_s##_dma(pci_dma_context(dev), addr, val); \ 674 } 675 676 PCI_DMA_DEFINE_LDST(ub, b, 8); 677 PCI_DMA_DEFINE_LDST(uw_le, w_le, 16) 678 PCI_DMA_DEFINE_LDST(l_le, l_le, 32); 679 PCI_DMA_DEFINE_LDST(q_le, q_le, 64); 680 PCI_DMA_DEFINE_LDST(uw_be, w_be, 16) 681 PCI_DMA_DEFINE_LDST(l_be, l_be, 32); 682 PCI_DMA_DEFINE_LDST(q_be, q_be, 64); 683 684 #undef PCI_DMA_DEFINE_LDST 685 686 static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr, 687 dma_addr_t *plen, DMADirection dir) 688 { 689 void *buf; 690 691 buf = dma_memory_map(pci_dma_context(dev), addr, plen, dir); 692 return buf; 693 } 694 695 static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len, 696 DMADirection dir, dma_addr_t access_len) 697 { 698 dma_memory_unmap(pci_dma_context(dev), buffer, len, dir, access_len); 699 } 700 701 static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev, 702 int alloc_hint) 703 { 704 qemu_sglist_init(qsg, alloc_hint, pci_dma_context(dev)); 705 } 706 707 extern const VMStateDescription vmstate_pci_device; 708 709 #define VMSTATE_PCI_DEVICE(_field, _state) { \ 710 .name = (stringify(_field)), \ 711 .size = sizeof(PCIDevice), \ 712 .vmsd = &vmstate_pci_device, \ 713 .flags = VMS_STRUCT, \ 714 .offset = vmstate_offset_value(_state, _field, PCIDevice), \ 715 } 716 717 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \ 718 .name = (stringify(_field)), \ 719 .size = sizeof(PCIDevice), \ 720 .vmsd = &vmstate_pci_device, \ 721 .flags = VMS_STRUCT|VMS_POINTER, \ 722 .offset = vmstate_offset_pointer(_state, _field, PCIDevice), \ 723 } 724 725 #endif 726