1 #ifndef QEMU_PCI_H 2 #define QEMU_PCI_H 3 4 #include "hw/qdev.h" 5 #include "exec/memory.h" 6 #include "sysemu/dma.h" 7 8 /* PCI includes legacy ISA access. */ 9 #include "hw/isa/isa.h" 10 11 #include "hw/pci/pcie.h" 12 13 extern bool pci_available; 14 15 /* PCI bus */ 16 17 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 18 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 19 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 20 #define PCI_FUNC(devfn) ((devfn) & 0x07) 21 #define PCI_BUILD_BDF(bus, devfn) ((bus << 8) | (devfn)) 22 #define PCI_BUS_MAX 256 23 #define PCI_DEVFN_MAX 256 24 #define PCI_SLOT_MAX 32 25 #define PCI_FUNC_MAX 8 26 27 /* Class, Vendor and Device IDs from Linux's pci_ids.h */ 28 #include "hw/pci/pci_ids.h" 29 30 /* QEMU-specific Vendor and Device ID definitions */ 31 32 /* IBM (0x1014) */ 33 #define PCI_DEVICE_ID_IBM_440GX 0x027f 34 #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff 35 36 /* Hitachi (0x1054) */ 37 #define PCI_VENDOR_ID_HITACHI 0x1054 38 #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e 39 40 /* Apple (0x106b) */ 41 #define PCI_DEVICE_ID_APPLE_343S1201 0x0010 42 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e 43 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f 44 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022 45 #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f 46 47 /* Realtek (0x10ec) */ 48 #define PCI_DEVICE_ID_REALTEK_8029 0x8029 49 50 /* Xilinx (0x10ee) */ 51 #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300 52 53 /* Marvell (0x11ab) */ 54 #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620 55 56 /* QEMU/Bochs VGA (0x1234) */ 57 #define PCI_VENDOR_ID_QEMU 0x1234 58 #define PCI_DEVICE_ID_QEMU_VGA 0x1111 59 60 /* VMWare (0x15ad) */ 61 #define PCI_VENDOR_ID_VMWARE 0x15ad 62 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 63 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710 64 #define PCI_DEVICE_ID_VMWARE_NET 0x0720 65 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730 66 #define PCI_DEVICE_ID_VMWARE_PVSCSI 0x07C0 67 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729 68 #define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0 69 70 /* Intel (0x8086) */ 71 #define PCI_DEVICE_ID_INTEL_82551IT 0x1209 72 #define PCI_DEVICE_ID_INTEL_82557 0x1229 73 #define PCI_DEVICE_ID_INTEL_82801IR 0x2922 74 75 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */ 76 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 77 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 78 #define PCI_SUBDEVICE_ID_QEMU 0x1100 79 80 #define PCI_DEVICE_ID_VIRTIO_NET 0x1000 81 #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001 82 #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002 83 #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003 84 #define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004 85 #define PCI_DEVICE_ID_VIRTIO_RNG 0x1005 86 #define PCI_DEVICE_ID_VIRTIO_9P 0x1009 87 #define PCI_DEVICE_ID_VIRTIO_VSOCK 0x1012 88 89 #define PCI_VENDOR_ID_REDHAT 0x1b36 90 #define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001 91 #define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002 92 #define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003 93 #define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004 94 #define PCI_DEVICE_ID_REDHAT_TEST 0x0005 95 #define PCI_DEVICE_ID_REDHAT_ROCKER 0x0006 96 #define PCI_DEVICE_ID_REDHAT_SDHCI 0x0007 97 #define PCI_DEVICE_ID_REDHAT_PCIE_HOST 0x0008 98 #define PCI_DEVICE_ID_REDHAT_PXB 0x0009 99 #define PCI_DEVICE_ID_REDHAT_BRIDGE_SEAT 0x000a 100 #define PCI_DEVICE_ID_REDHAT_PXB_PCIE 0x000b 101 #define PCI_DEVICE_ID_REDHAT_PCIE_RP 0x000c 102 #define PCI_DEVICE_ID_REDHAT_XHCI 0x000d 103 #define PCI_DEVICE_ID_REDHAT_QXL 0x0100 104 105 #define FMT_PCIBUS PRIx64 106 107 typedef uint64_t pcibus_t; 108 109 struct PCIHostDeviceAddress { 110 unsigned int domain; 111 unsigned int bus; 112 unsigned int slot; 113 unsigned int function; 114 }; 115 116 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, 117 uint32_t address, uint32_t data, int len); 118 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev, 119 uint32_t address, int len); 120 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, 121 pcibus_t addr, pcibus_t size, int type); 122 typedef void PCIUnregisterFunc(PCIDevice *pci_dev); 123 124 typedef struct PCIIORegion { 125 pcibus_t addr; /* current PCI mapping address. -1 means not mapped */ 126 #define PCI_BAR_UNMAPPED (~(pcibus_t)0) 127 pcibus_t size; 128 uint8_t type; 129 MemoryRegion *memory; 130 MemoryRegion *address_space; 131 } PCIIORegion; 132 133 #define PCI_ROM_SLOT 6 134 #define PCI_NUM_REGIONS 7 135 136 enum { 137 QEMU_PCI_VGA_MEM, 138 QEMU_PCI_VGA_IO_LO, 139 QEMU_PCI_VGA_IO_HI, 140 QEMU_PCI_VGA_NUM_REGIONS, 141 }; 142 143 #define QEMU_PCI_VGA_MEM_BASE 0xa0000 144 #define QEMU_PCI_VGA_MEM_SIZE 0x20000 145 #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0 146 #define QEMU_PCI_VGA_IO_LO_SIZE 0xc 147 #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0 148 #define QEMU_PCI_VGA_IO_HI_SIZE 0x20 149 150 #include "hw/pci/pci_regs.h" 151 152 /* PCI HEADER_TYPE */ 153 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80 154 155 /* Size of the standard PCI config header */ 156 #define PCI_CONFIG_HEADER_SIZE 0x40 157 /* Size of the standard PCI config space */ 158 #define PCI_CONFIG_SPACE_SIZE 0x100 159 /* Size of the standard PCIe config space: 4KB */ 160 #define PCIE_CONFIG_SPACE_SIZE 0x1000 161 162 #define PCI_NUM_PINS 4 /* A-D */ 163 164 /* Bits in cap_present field. */ 165 enum { 166 QEMU_PCI_CAP_MSI = 0x1, 167 QEMU_PCI_CAP_MSIX = 0x2, 168 QEMU_PCI_CAP_EXPRESS = 0x4, 169 170 /* multifunction capable device */ 171 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3 172 QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR), 173 174 /* command register SERR bit enabled */ 175 #define QEMU_PCI_CAP_SERR_BITNR 4 176 QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR), 177 /* Standard hot plug controller. */ 178 #define QEMU_PCI_SHPC_BITNR 5 179 QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR), 180 #define QEMU_PCI_SLOTID_BITNR 6 181 QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR), 182 /* PCI Express capability - Power Controller Present */ 183 #define QEMU_PCIE_SLTCAP_PCP_BITNR 7 184 QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR), 185 /* Link active status in endpoint capability is always set */ 186 #define QEMU_PCIE_LNKSTA_DLLLA_BITNR 8 187 QEMU_PCIE_LNKSTA_DLLLA = (1 << QEMU_PCIE_LNKSTA_DLLLA_BITNR), 188 #define QEMU_PCIE_EXTCAP_INIT_BITNR 9 189 QEMU_PCIE_EXTCAP_INIT = (1 << QEMU_PCIE_EXTCAP_INIT_BITNR), 190 }; 191 192 #define TYPE_PCI_DEVICE "pci-device" 193 #define PCI_DEVICE(obj) \ 194 OBJECT_CHECK(PCIDevice, (obj), TYPE_PCI_DEVICE) 195 #define PCI_DEVICE_CLASS(klass) \ 196 OBJECT_CLASS_CHECK(PCIDeviceClass, (klass), TYPE_PCI_DEVICE) 197 #define PCI_DEVICE_GET_CLASS(obj) \ 198 OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE) 199 200 typedef struct PCIINTxRoute { 201 enum { 202 PCI_INTX_ENABLED, 203 PCI_INTX_INVERTED, 204 PCI_INTX_DISABLED, 205 } mode; 206 int irq; 207 } PCIINTxRoute; 208 209 typedef struct PCIDeviceClass { 210 DeviceClass parent_class; 211 212 void (*realize)(PCIDevice *dev, Error **errp); 213 int (*init)(PCIDevice *dev);/* TODO convert to realize() and remove */ 214 PCIUnregisterFunc *exit; 215 PCIConfigReadFunc *config_read; 216 PCIConfigWriteFunc *config_write; 217 218 uint16_t vendor_id; 219 uint16_t device_id; 220 uint8_t revision; 221 uint16_t class_id; 222 uint16_t subsystem_vendor_id; /* only for header type = 0 */ 223 uint16_t subsystem_id; /* only for header type = 0 */ 224 225 /* 226 * pci-to-pci bridge or normal device. 227 * This doesn't mean pci host switch. 228 * When card bus bridge is supported, this would be enhanced. 229 */ 230 int is_bridge; 231 232 /* pcie stuff */ 233 int is_express; /* is this device pci express? */ 234 235 /* rom bar */ 236 const char *romfile; 237 } PCIDeviceClass; 238 239 typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev); 240 typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector, 241 MSIMessage msg); 242 typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector); 243 typedef void (*MSIVectorPollNotifier)(PCIDevice *dev, 244 unsigned int vector_start, 245 unsigned int vector_end); 246 247 enum PCIReqIDType { 248 PCI_REQ_ID_INVALID = 0, 249 PCI_REQ_ID_BDF, 250 PCI_REQ_ID_SECONDARY_BUS, 251 PCI_REQ_ID_MAX, 252 }; 253 typedef enum PCIReqIDType PCIReqIDType; 254 255 struct PCIReqIDCache { 256 PCIDevice *dev; 257 PCIReqIDType type; 258 }; 259 typedef struct PCIReqIDCache PCIReqIDCache; 260 261 struct PCIDevice { 262 DeviceState qdev; 263 264 /* PCI config space */ 265 uint8_t *config; 266 267 /* Used to enable config checks on load. Note that writable bits are 268 * never checked even if set in cmask. */ 269 uint8_t *cmask; 270 271 /* Used to implement R/W bytes */ 272 uint8_t *wmask; 273 274 /* Used to implement RW1C(Write 1 to Clear) bytes */ 275 uint8_t *w1cmask; 276 277 /* Used to allocate config space for capabilities. */ 278 uint8_t *used; 279 280 /* the following fields are read only */ 281 PCIBus *bus; 282 int32_t devfn; 283 /* Cached device to fetch requester ID from, to avoid the PCI 284 * tree walking every time we invoke PCI request (e.g., 285 * MSI). For conventional PCI root complex, this field is 286 * meaningless. */ 287 PCIReqIDCache requester_id_cache; 288 char name[64]; 289 PCIIORegion io_regions[PCI_NUM_REGIONS]; 290 AddressSpace bus_master_as; 291 MemoryRegion bus_master_container_region; 292 MemoryRegion bus_master_enable_region; 293 294 /* do not access the following fields */ 295 PCIConfigReadFunc *config_read; 296 PCIConfigWriteFunc *config_write; 297 298 /* Legacy PCI VGA regions */ 299 MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS]; 300 bool has_vga; 301 302 /* Current IRQ levels. Used internally by the generic PCI code. */ 303 uint8_t irq_state; 304 305 /* Capability bits */ 306 uint32_t cap_present; 307 308 /* Offset of MSI-X capability in config space */ 309 uint8_t msix_cap; 310 311 /* MSI-X entries */ 312 int msix_entries_nr; 313 314 /* Space to store MSIX table & pending bit array */ 315 uint8_t *msix_table; 316 uint8_t *msix_pba; 317 /* MemoryRegion container for msix exclusive BAR setup */ 318 MemoryRegion msix_exclusive_bar; 319 /* Memory Regions for MSIX table and pending bit entries. */ 320 MemoryRegion msix_table_mmio; 321 MemoryRegion msix_pba_mmio; 322 /* Reference-count for entries actually in use by driver. */ 323 unsigned *msix_entry_used; 324 /* MSIX function mask set or MSIX disabled */ 325 bool msix_function_masked; 326 /* Version id needed for VMState */ 327 int32_t version_id; 328 329 /* Offset of MSI capability in config space */ 330 uint8_t msi_cap; 331 332 /* PCI Express */ 333 PCIExpressDevice exp; 334 335 /* SHPC */ 336 SHPCDevice *shpc; 337 338 /* Location of option rom */ 339 char *romfile; 340 bool has_rom; 341 MemoryRegion rom; 342 uint32_t rom_bar; 343 344 /* INTx routing notifier */ 345 PCIINTxRoutingNotifier intx_routing_notifier; 346 347 /* MSI-X notifiers */ 348 MSIVectorUseNotifier msix_vector_use_notifier; 349 MSIVectorReleaseNotifier msix_vector_release_notifier; 350 MSIVectorPollNotifier msix_vector_poll_notifier; 351 }; 352 353 void pci_register_bar(PCIDevice *pci_dev, int region_num, 354 uint8_t attr, MemoryRegion *memory); 355 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, 356 MemoryRegion *io_lo, MemoryRegion *io_hi); 357 void pci_unregister_vga(PCIDevice *pci_dev); 358 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num); 359 360 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, 361 uint8_t offset, uint8_t size, 362 Error **errp); 363 364 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size); 365 366 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id); 367 368 369 uint32_t pci_default_read_config(PCIDevice *d, 370 uint32_t address, int len); 371 void pci_default_write_config(PCIDevice *d, 372 uint32_t address, uint32_t val, int len); 373 void pci_device_save(PCIDevice *s, QEMUFile *f); 374 int pci_device_load(PCIDevice *s, QEMUFile *f); 375 MemoryRegion *pci_address_space(PCIDevice *dev); 376 MemoryRegion *pci_address_space_io(PCIDevice *dev); 377 378 /* 379 * Should not normally be used by devices. For use by sPAPR target 380 * where QEMU emulates firmware. 381 */ 382 int pci_bar(PCIDevice *d, int reg); 383 384 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level); 385 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); 386 typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin); 387 388 #define TYPE_PCI_BUS "PCI" 389 #define PCI_BUS(obj) OBJECT_CHECK(PCIBus, (obj), TYPE_PCI_BUS) 390 #define PCI_BUS_CLASS(klass) OBJECT_CLASS_CHECK(PCIBusClass, (klass), TYPE_PCI_BUS) 391 #define PCI_BUS_GET_CLASS(obj) OBJECT_GET_CLASS(PCIBusClass, (obj), TYPE_PCI_BUS) 392 #define TYPE_PCIE_BUS "PCIE" 393 394 bool pci_bus_is_express(PCIBus *bus); 395 bool pci_bus_is_root(PCIBus *bus); 396 void pci_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent, 397 const char *name, 398 MemoryRegion *address_space_mem, 399 MemoryRegion *address_space_io, 400 uint8_t devfn_min, const char *typename); 401 PCIBus *pci_bus_new(DeviceState *parent, const char *name, 402 MemoryRegion *address_space_mem, 403 MemoryRegion *address_space_io, 404 uint8_t devfn_min, const char *typename); 405 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 406 void *irq_opaque, int nirq); 407 int pci_bus_get_irq_level(PCIBus *bus, int irq_num); 408 /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */ 409 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin); 410 PCIBus *pci_register_bus(DeviceState *parent, const char *name, 411 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 412 void *irq_opaque, 413 MemoryRegion *address_space_mem, 414 MemoryRegion *address_space_io, 415 uint8_t devfn_min, int nirq, const char *typename); 416 void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn); 417 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin); 418 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new); 419 void pci_bus_fire_intx_routing_notifier(PCIBus *bus); 420 void pci_device_set_intx_routing_notifier(PCIDevice *dev, 421 PCIINTxRoutingNotifier notifier); 422 void pci_device_reset(PCIDevice *dev); 423 424 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus, 425 const char *default_model, 426 const char *default_devaddr); 427 428 PCIDevice *pci_vga_init(PCIBus *bus); 429 430 int pci_bus_num(PCIBus *s); 431 int pci_bus_numa_node(PCIBus *bus); 432 void pci_for_each_device(PCIBus *bus, int bus_num, 433 void (*fn)(PCIBus *bus, PCIDevice *d, void *opaque), 434 void *opaque); 435 void pci_for_each_device_reverse(PCIBus *bus, int bus_num, 436 void (*fn)(PCIBus *bus, PCIDevice *d, 437 void *opaque), 438 void *opaque); 439 void pci_for_each_bus_depth_first(PCIBus *bus, 440 void *(*begin)(PCIBus *bus, void *parent_state), 441 void (*end)(PCIBus *bus, void *state), 442 void *parent_state); 443 PCIDevice *pci_get_function_0(PCIDevice *pci_dev); 444 445 /* Use this wrapper when specific scan order is not required. */ 446 static inline 447 void pci_for_each_bus(PCIBus *bus, 448 void (*fn)(PCIBus *bus, void *opaque), 449 void *opaque) 450 { 451 pci_for_each_bus_depth_first(bus, NULL, fn, opaque); 452 } 453 454 PCIBus *pci_find_primary_bus(void); 455 PCIBus *pci_device_root_bus(const PCIDevice *d); 456 const char *pci_root_bus_path(PCIDevice *dev); 457 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn); 458 int pci_qdev_find_device(const char *id, PCIDevice **pdev); 459 void pci_bus_get_w64_range(PCIBus *bus, Range *range); 460 461 void pci_device_deassert_intx(PCIDevice *dev); 462 463 typedef AddressSpace *(*PCIIOMMUFunc)(PCIBus *, void *, int); 464 465 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev); 466 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque); 467 468 static inline void 469 pci_set_byte(uint8_t *config, uint8_t val) 470 { 471 *config = val; 472 } 473 474 static inline uint8_t 475 pci_get_byte(const uint8_t *config) 476 { 477 return *config; 478 } 479 480 static inline void 481 pci_set_word(uint8_t *config, uint16_t val) 482 { 483 stw_le_p(config, val); 484 } 485 486 static inline uint16_t 487 pci_get_word(const uint8_t *config) 488 { 489 return lduw_le_p(config); 490 } 491 492 static inline void 493 pci_set_long(uint8_t *config, uint32_t val) 494 { 495 stl_le_p(config, val); 496 } 497 498 static inline uint32_t 499 pci_get_long(const uint8_t *config) 500 { 501 return ldl_le_p(config); 502 } 503 504 /* 505 * PCI capabilities and/or their fields 506 * are generally DWORD aligned only so 507 * mechanism used by pci_set/get_quad() 508 * must be tolerant to unaligned pointers 509 * 510 */ 511 static inline void 512 pci_set_quad(uint8_t *config, uint64_t val) 513 { 514 stq_le_p(config, val); 515 } 516 517 static inline uint64_t 518 pci_get_quad(const uint8_t *config) 519 { 520 return ldq_le_p(config); 521 } 522 523 static inline void 524 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val) 525 { 526 pci_set_word(&pci_config[PCI_VENDOR_ID], val); 527 } 528 529 static inline void 530 pci_config_set_device_id(uint8_t *pci_config, uint16_t val) 531 { 532 pci_set_word(&pci_config[PCI_DEVICE_ID], val); 533 } 534 535 static inline void 536 pci_config_set_revision(uint8_t *pci_config, uint8_t val) 537 { 538 pci_set_byte(&pci_config[PCI_REVISION_ID], val); 539 } 540 541 static inline void 542 pci_config_set_class(uint8_t *pci_config, uint16_t val) 543 { 544 pci_set_word(&pci_config[PCI_CLASS_DEVICE], val); 545 } 546 547 static inline void 548 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val) 549 { 550 pci_set_byte(&pci_config[PCI_CLASS_PROG], val); 551 } 552 553 static inline void 554 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val) 555 { 556 pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val); 557 } 558 559 /* 560 * helper functions to do bit mask operation on configuration space. 561 * Just to set bit, use test-and-set and discard returned value. 562 * Just to clear bit, use test-and-clear and discard returned value. 563 * NOTE: They aren't atomic. 564 */ 565 static inline uint8_t 566 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask) 567 { 568 uint8_t val = pci_get_byte(config); 569 pci_set_byte(config, val & ~mask); 570 return val & mask; 571 } 572 573 static inline uint8_t 574 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask) 575 { 576 uint8_t val = pci_get_byte(config); 577 pci_set_byte(config, val | mask); 578 return val & mask; 579 } 580 581 static inline uint16_t 582 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask) 583 { 584 uint16_t val = pci_get_word(config); 585 pci_set_word(config, val & ~mask); 586 return val & mask; 587 } 588 589 static inline uint16_t 590 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask) 591 { 592 uint16_t val = pci_get_word(config); 593 pci_set_word(config, val | mask); 594 return val & mask; 595 } 596 597 static inline uint32_t 598 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask) 599 { 600 uint32_t val = pci_get_long(config); 601 pci_set_long(config, val & ~mask); 602 return val & mask; 603 } 604 605 static inline uint32_t 606 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask) 607 { 608 uint32_t val = pci_get_long(config); 609 pci_set_long(config, val | mask); 610 return val & mask; 611 } 612 613 static inline uint64_t 614 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask) 615 { 616 uint64_t val = pci_get_quad(config); 617 pci_set_quad(config, val & ~mask); 618 return val & mask; 619 } 620 621 static inline uint64_t 622 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask) 623 { 624 uint64_t val = pci_get_quad(config); 625 pci_set_quad(config, val | mask); 626 return val & mask; 627 } 628 629 /* Access a register specified by a mask */ 630 static inline void 631 pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg) 632 { 633 uint8_t val = pci_get_byte(config); 634 uint8_t rval = reg << ctz32(mask); 635 pci_set_byte(config, (~mask & val) | (mask & rval)); 636 } 637 638 static inline uint8_t 639 pci_get_byte_by_mask(uint8_t *config, uint8_t mask) 640 { 641 uint8_t val = pci_get_byte(config); 642 return (val & mask) >> ctz32(mask); 643 } 644 645 static inline void 646 pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg) 647 { 648 uint16_t val = pci_get_word(config); 649 uint16_t rval = reg << ctz32(mask); 650 pci_set_word(config, (~mask & val) | (mask & rval)); 651 } 652 653 static inline uint16_t 654 pci_get_word_by_mask(uint8_t *config, uint16_t mask) 655 { 656 uint16_t val = pci_get_word(config); 657 return (val & mask) >> ctz32(mask); 658 } 659 660 static inline void 661 pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg) 662 { 663 uint32_t val = pci_get_long(config); 664 uint32_t rval = reg << ctz32(mask); 665 pci_set_long(config, (~mask & val) | (mask & rval)); 666 } 667 668 static inline uint32_t 669 pci_get_long_by_mask(uint8_t *config, uint32_t mask) 670 { 671 uint32_t val = pci_get_long(config); 672 return (val & mask) >> ctz32(mask); 673 } 674 675 static inline void 676 pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg) 677 { 678 uint64_t val = pci_get_quad(config); 679 uint64_t rval = reg << ctz32(mask); 680 pci_set_quad(config, (~mask & val) | (mask & rval)); 681 } 682 683 static inline uint64_t 684 pci_get_quad_by_mask(uint8_t *config, uint64_t mask) 685 { 686 uint64_t val = pci_get_quad(config); 687 return (val & mask) >> ctz32(mask); 688 } 689 690 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction, 691 const char *name); 692 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, 693 bool multifunction, 694 const char *name); 695 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name); 696 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name); 697 698 void lsi53c895a_create(PCIBus *bus); 699 700 qemu_irq pci_allocate_irq(PCIDevice *pci_dev); 701 void pci_set_irq(PCIDevice *pci_dev, int level); 702 703 static inline void pci_irq_assert(PCIDevice *pci_dev) 704 { 705 pci_set_irq(pci_dev, 1); 706 } 707 708 static inline void pci_irq_deassert(PCIDevice *pci_dev) 709 { 710 pci_set_irq(pci_dev, 0); 711 } 712 713 /* 714 * FIXME: PCI does not work this way. 715 * All the callers to this method should be fixed. 716 */ 717 static inline void pci_irq_pulse(PCIDevice *pci_dev) 718 { 719 pci_irq_assert(pci_dev); 720 pci_irq_deassert(pci_dev); 721 } 722 723 static inline int pci_is_express(const PCIDevice *d) 724 { 725 return d->cap_present & QEMU_PCI_CAP_EXPRESS; 726 } 727 728 static inline uint32_t pci_config_size(const PCIDevice *d) 729 { 730 return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE; 731 } 732 733 static inline uint16_t pci_get_bdf(PCIDevice *dev) 734 { 735 return PCI_BUILD_BDF(pci_bus_num(dev->bus), dev->devfn); 736 } 737 738 uint16_t pci_requester_id(PCIDevice *dev); 739 740 /* DMA access functions */ 741 static inline AddressSpace *pci_get_address_space(PCIDevice *dev) 742 { 743 return &dev->bus_master_as; 744 } 745 746 static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr, 747 void *buf, dma_addr_t len, DMADirection dir) 748 { 749 dma_memory_rw(pci_get_address_space(dev), addr, buf, len, dir); 750 return 0; 751 } 752 753 static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr, 754 void *buf, dma_addr_t len) 755 { 756 return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE); 757 } 758 759 static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr, 760 const void *buf, dma_addr_t len) 761 { 762 return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE); 763 } 764 765 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \ 766 static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev, \ 767 dma_addr_t addr) \ 768 { \ 769 return ld##_l##_dma(pci_get_address_space(dev), addr); \ 770 } \ 771 static inline void st##_s##_pci_dma(PCIDevice *dev, \ 772 dma_addr_t addr, uint##_bits##_t val) \ 773 { \ 774 st##_s##_dma(pci_get_address_space(dev), addr, val); \ 775 } 776 777 PCI_DMA_DEFINE_LDST(ub, b, 8); 778 PCI_DMA_DEFINE_LDST(uw_le, w_le, 16) 779 PCI_DMA_DEFINE_LDST(l_le, l_le, 32); 780 PCI_DMA_DEFINE_LDST(q_le, q_le, 64); 781 PCI_DMA_DEFINE_LDST(uw_be, w_be, 16) 782 PCI_DMA_DEFINE_LDST(l_be, l_be, 32); 783 PCI_DMA_DEFINE_LDST(q_be, q_be, 64); 784 785 #undef PCI_DMA_DEFINE_LDST 786 787 static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr, 788 dma_addr_t *plen, DMADirection dir) 789 { 790 void *buf; 791 792 buf = dma_memory_map(pci_get_address_space(dev), addr, plen, dir); 793 return buf; 794 } 795 796 static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len, 797 DMADirection dir, dma_addr_t access_len) 798 { 799 dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len); 800 } 801 802 static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev, 803 int alloc_hint) 804 { 805 qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev)); 806 } 807 808 extern const VMStateDescription vmstate_pci_device; 809 810 #define VMSTATE_PCI_DEVICE(_field, _state) { \ 811 .name = (stringify(_field)), \ 812 .size = sizeof(PCIDevice), \ 813 .vmsd = &vmstate_pci_device, \ 814 .flags = VMS_STRUCT, \ 815 .offset = vmstate_offset_value(_state, _field, PCIDevice), \ 816 } 817 818 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \ 819 .name = (stringify(_field)), \ 820 .size = sizeof(PCIDevice), \ 821 .vmsd = &vmstate_pci_device, \ 822 .flags = VMS_STRUCT|VMS_POINTER, \ 823 .offset = vmstate_offset_pointer(_state, _field, PCIDevice), \ 824 } 825 826 MSIMessage pci_get_msi_message(PCIDevice *dev, int vector); 827 828 #endif 829