1 #ifndef QEMU_PCI_H 2 #define QEMU_PCI_H 3 4 #include "qemu-common.h" 5 6 #include "hw/qdev.h" 7 #include "exec/memory.h" 8 #include "sysemu/dma.h" 9 #include "qapi/error.h" 10 11 /* PCI includes legacy ISA access. */ 12 #include "hw/isa/isa.h" 13 14 #include "hw/pci/pcie.h" 15 16 /* PCI bus */ 17 18 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 19 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 20 #define PCI_FUNC(devfn) ((devfn) & 0x07) 21 #define PCI_SLOT_MAX 32 22 #define PCI_FUNC_MAX 8 23 24 /* Class, Vendor and Device IDs from Linux's pci_ids.h */ 25 #include "hw/pci/pci_ids.h" 26 27 /* QEMU-specific Vendor and Device ID definitions */ 28 29 /* IBM (0x1014) */ 30 #define PCI_DEVICE_ID_IBM_440GX 0x027f 31 #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff 32 33 /* Hitachi (0x1054) */ 34 #define PCI_VENDOR_ID_HITACHI 0x1054 35 #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e 36 37 /* Apple (0x106b) */ 38 #define PCI_DEVICE_ID_APPLE_343S1201 0x0010 39 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e 40 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f 41 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022 42 #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f 43 44 /* Realtek (0x10ec) */ 45 #define PCI_DEVICE_ID_REALTEK_8029 0x8029 46 47 /* Xilinx (0x10ee) */ 48 #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300 49 50 /* Marvell (0x11ab) */ 51 #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620 52 53 /* QEMU/Bochs VGA (0x1234) */ 54 #define PCI_VENDOR_ID_QEMU 0x1234 55 #define PCI_DEVICE_ID_QEMU_VGA 0x1111 56 57 /* VMWare (0x15ad) */ 58 #define PCI_VENDOR_ID_VMWARE 0x15ad 59 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 60 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710 61 #define PCI_DEVICE_ID_VMWARE_NET 0x0720 62 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730 63 #define PCI_DEVICE_ID_VMWARE_PVSCSI 0x07C0 64 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729 65 #define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0 66 67 /* Intel (0x8086) */ 68 #define PCI_DEVICE_ID_INTEL_82551IT 0x1209 69 #define PCI_DEVICE_ID_INTEL_82557 0x1229 70 #define PCI_DEVICE_ID_INTEL_82801IR 0x2922 71 72 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */ 73 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 74 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 75 #define PCI_SUBDEVICE_ID_QEMU 0x1100 76 77 #define PCI_DEVICE_ID_VIRTIO_NET 0x1000 78 #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001 79 #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002 80 #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003 81 #define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004 82 #define PCI_DEVICE_ID_VIRTIO_RNG 0x1005 83 #define PCI_DEVICE_ID_VIRTIO_9P 0x1009 84 85 #define PCI_VENDOR_ID_REDHAT 0x1b36 86 #define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001 87 #define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002 88 #define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003 89 #define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004 90 #define PCI_DEVICE_ID_REDHAT_TEST 0x0005 91 #define PCI_DEVICE_ID_REDHAT_ROCKER 0x0006 92 #define PCI_DEVICE_ID_REDHAT_SDHCI 0x0007 93 #define PCI_DEVICE_ID_REDHAT_PCIE_HOST 0x0008 94 #define PCI_DEVICE_ID_REDHAT_PXB 0x0009 95 #define PCI_DEVICE_ID_REDHAT_QXL 0x0100 96 97 #define FMT_PCIBUS PRIx64 98 99 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, 100 uint32_t address, uint32_t data, int len); 101 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev, 102 uint32_t address, int len); 103 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, 104 pcibus_t addr, pcibus_t size, int type); 105 typedef void PCIUnregisterFunc(PCIDevice *pci_dev); 106 107 typedef struct PCIIORegion { 108 pcibus_t addr; /* current PCI mapping address. -1 means not mapped */ 109 #define PCI_BAR_UNMAPPED (~(pcibus_t)0) 110 pcibus_t size; 111 uint8_t type; 112 MemoryRegion *memory; 113 MemoryRegion *address_space; 114 } PCIIORegion; 115 116 #define PCI_ROM_SLOT 6 117 #define PCI_NUM_REGIONS 7 118 119 enum { 120 QEMU_PCI_VGA_MEM, 121 QEMU_PCI_VGA_IO_LO, 122 QEMU_PCI_VGA_IO_HI, 123 QEMU_PCI_VGA_NUM_REGIONS, 124 }; 125 126 #define QEMU_PCI_VGA_MEM_BASE 0xa0000 127 #define QEMU_PCI_VGA_MEM_SIZE 0x20000 128 #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0 129 #define QEMU_PCI_VGA_IO_LO_SIZE 0xc 130 #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0 131 #define QEMU_PCI_VGA_IO_HI_SIZE 0x20 132 133 #include "hw/pci/pci_regs.h" 134 135 /* PCI HEADER_TYPE */ 136 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80 137 138 /* Size of the standard PCI config header */ 139 #define PCI_CONFIG_HEADER_SIZE 0x40 140 /* Size of the standard PCI config space */ 141 #define PCI_CONFIG_SPACE_SIZE 0x100 142 /* Size of the standard PCIe config space: 4KB */ 143 #define PCIE_CONFIG_SPACE_SIZE 0x1000 144 145 #define PCI_NUM_PINS 4 /* A-D */ 146 147 /* Bits in cap_present field. */ 148 enum { 149 QEMU_PCI_CAP_MSI = 0x1, 150 QEMU_PCI_CAP_MSIX = 0x2, 151 QEMU_PCI_CAP_EXPRESS = 0x4, 152 153 /* multifunction capable device */ 154 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3 155 QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR), 156 157 /* command register SERR bit enabled */ 158 #define QEMU_PCI_CAP_SERR_BITNR 4 159 QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR), 160 /* Standard hot plug controller. */ 161 #define QEMU_PCI_SHPC_BITNR 5 162 QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR), 163 #define QEMU_PCI_SLOTID_BITNR 6 164 QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR), 165 /* PCI Express capability - Power Controller Present */ 166 #define QEMU_PCIE_SLTCAP_PCP_BITNR 7 167 QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR), 168 }; 169 170 #define TYPE_PCI_DEVICE "pci-device" 171 #define PCI_DEVICE(obj) \ 172 OBJECT_CHECK(PCIDevice, (obj), TYPE_PCI_DEVICE) 173 #define PCI_DEVICE_CLASS(klass) \ 174 OBJECT_CLASS_CHECK(PCIDeviceClass, (klass), TYPE_PCI_DEVICE) 175 #define PCI_DEVICE_GET_CLASS(obj) \ 176 OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE) 177 178 typedef struct PCIINTxRoute { 179 enum { 180 PCI_INTX_ENABLED, 181 PCI_INTX_INVERTED, 182 PCI_INTX_DISABLED, 183 } mode; 184 int irq; 185 } PCIINTxRoute; 186 187 typedef struct PCIDeviceClass { 188 DeviceClass parent_class; 189 190 void (*realize)(PCIDevice *dev, Error **errp); 191 int (*init)(PCIDevice *dev);/* TODO convert to realize() and remove */ 192 PCIUnregisterFunc *exit; 193 PCIConfigReadFunc *config_read; 194 PCIConfigWriteFunc *config_write; 195 196 uint16_t vendor_id; 197 uint16_t device_id; 198 uint8_t revision; 199 uint16_t class_id; 200 uint16_t subsystem_vendor_id; /* only for header type = 0 */ 201 uint16_t subsystem_id; /* only for header type = 0 */ 202 203 /* 204 * pci-to-pci bridge or normal device. 205 * This doesn't mean pci host switch. 206 * When card bus bridge is supported, this would be enhanced. 207 */ 208 int is_bridge; 209 210 /* pcie stuff */ 211 int is_express; /* is this device pci express? */ 212 213 /* rom bar */ 214 const char *romfile; 215 } PCIDeviceClass; 216 217 typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev); 218 typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector, 219 MSIMessage msg); 220 typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector); 221 typedef void (*MSIVectorPollNotifier)(PCIDevice *dev, 222 unsigned int vector_start, 223 unsigned int vector_end); 224 225 struct PCIDevice { 226 DeviceState qdev; 227 228 /* PCI config space */ 229 uint8_t *config; 230 231 /* Used to enable config checks on load. Note that writable bits are 232 * never checked even if set in cmask. */ 233 uint8_t *cmask; 234 235 /* Used to implement R/W bytes */ 236 uint8_t *wmask; 237 238 /* Used to implement RW1C(Write 1 to Clear) bytes */ 239 uint8_t *w1cmask; 240 241 /* Used to allocate config space for capabilities. */ 242 uint8_t *used; 243 244 /* the following fields are read only */ 245 PCIBus *bus; 246 int32_t devfn; 247 char name[64]; 248 PCIIORegion io_regions[PCI_NUM_REGIONS]; 249 AddressSpace bus_master_as; 250 MemoryRegion bus_master_enable_region; 251 252 /* do not access the following fields */ 253 PCIConfigReadFunc *config_read; 254 PCIConfigWriteFunc *config_write; 255 256 /* Legacy PCI VGA regions */ 257 MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS]; 258 bool has_vga; 259 260 /* Current IRQ levels. Used internally by the generic PCI code. */ 261 uint8_t irq_state; 262 263 /* Capability bits */ 264 uint32_t cap_present; 265 266 /* Offset of MSI-X capability in config space */ 267 uint8_t msix_cap; 268 269 /* MSI-X entries */ 270 int msix_entries_nr; 271 272 /* Space to store MSIX table & pending bit array */ 273 uint8_t *msix_table; 274 uint8_t *msix_pba; 275 /* MemoryRegion container for msix exclusive BAR setup */ 276 MemoryRegion msix_exclusive_bar; 277 /* Memory Regions for MSIX table and pending bit entries. */ 278 MemoryRegion msix_table_mmio; 279 MemoryRegion msix_pba_mmio; 280 /* Reference-count for entries actually in use by driver. */ 281 unsigned *msix_entry_used; 282 /* MSIX function mask set or MSIX disabled */ 283 bool msix_function_masked; 284 /* Version id needed for VMState */ 285 int32_t version_id; 286 287 /* Offset of MSI capability in config space */ 288 uint8_t msi_cap; 289 290 /* PCI Express */ 291 PCIExpressDevice exp; 292 293 /* SHPC */ 294 SHPCDevice *shpc; 295 296 /* Location of option rom */ 297 char *romfile; 298 bool has_rom; 299 MemoryRegion rom; 300 uint32_t rom_bar; 301 302 /* INTx routing notifier */ 303 PCIINTxRoutingNotifier intx_routing_notifier; 304 305 /* MSI-X notifiers */ 306 MSIVectorUseNotifier msix_vector_use_notifier; 307 MSIVectorReleaseNotifier msix_vector_release_notifier; 308 MSIVectorPollNotifier msix_vector_poll_notifier; 309 }; 310 311 void pci_register_bar(PCIDevice *pci_dev, int region_num, 312 uint8_t attr, MemoryRegion *memory); 313 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, 314 MemoryRegion *io_lo, MemoryRegion *io_hi); 315 void pci_unregister_vga(PCIDevice *pci_dev); 316 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num); 317 318 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, 319 uint8_t offset, uint8_t size); 320 int pci_add_capability2(PCIDevice *pdev, uint8_t cap_id, 321 uint8_t offset, uint8_t size, 322 Error **errp); 323 324 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size); 325 326 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id); 327 328 329 uint32_t pci_default_read_config(PCIDevice *d, 330 uint32_t address, int len); 331 void pci_default_write_config(PCIDevice *d, 332 uint32_t address, uint32_t val, int len); 333 void pci_device_save(PCIDevice *s, QEMUFile *f); 334 int pci_device_load(PCIDevice *s, QEMUFile *f); 335 MemoryRegion *pci_address_space(PCIDevice *dev); 336 MemoryRegion *pci_address_space_io(PCIDevice *dev); 337 338 /* 339 * Should not normally be used by devices. For use by sPAPR target 340 * where QEMU emulates firmware. 341 */ 342 int pci_bar(PCIDevice *d, int reg); 343 344 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level); 345 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); 346 typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin); 347 348 #define TYPE_PCI_BUS "PCI" 349 #define PCI_BUS(obj) OBJECT_CHECK(PCIBus, (obj), TYPE_PCI_BUS) 350 #define PCI_BUS_CLASS(klass) OBJECT_CLASS_CHECK(PCIBusClass, (klass), TYPE_PCI_BUS) 351 #define PCI_BUS_GET_CLASS(obj) OBJECT_GET_CLASS(PCIBusClass, (obj), TYPE_PCI_BUS) 352 #define TYPE_PCIE_BUS "PCIE" 353 354 bool pci_bus_is_express(PCIBus *bus); 355 bool pci_bus_is_root(PCIBus *bus); 356 void pci_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent, 357 const char *name, 358 MemoryRegion *address_space_mem, 359 MemoryRegion *address_space_io, 360 uint8_t devfn_min, const char *typename); 361 PCIBus *pci_bus_new(DeviceState *parent, const char *name, 362 MemoryRegion *address_space_mem, 363 MemoryRegion *address_space_io, 364 uint8_t devfn_min, const char *typename); 365 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 366 void *irq_opaque, int nirq); 367 int pci_bus_get_irq_level(PCIBus *bus, int irq_num); 368 /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */ 369 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin); 370 PCIBus *pci_register_bus(DeviceState *parent, const char *name, 371 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 372 void *irq_opaque, 373 MemoryRegion *address_space_mem, 374 MemoryRegion *address_space_io, 375 uint8_t devfn_min, int nirq, const char *typename); 376 void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn); 377 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin); 378 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new); 379 void pci_bus_fire_intx_routing_notifier(PCIBus *bus); 380 void pci_device_set_intx_routing_notifier(PCIDevice *dev, 381 PCIINTxRoutingNotifier notifier); 382 void pci_device_reset(PCIDevice *dev); 383 384 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus, 385 const char *default_model, 386 const char *default_devaddr); 387 388 PCIDevice *pci_vga_init(PCIBus *bus); 389 390 int pci_bus_num(PCIBus *s); 391 int pci_bus_numa_node(PCIBus *bus); 392 void pci_for_each_device(PCIBus *bus, int bus_num, 393 void (*fn)(PCIBus *bus, PCIDevice *d, void *opaque), 394 void *opaque); 395 void pci_for_each_bus_depth_first(PCIBus *bus, 396 void *(*begin)(PCIBus *bus, void *parent_state), 397 void (*end)(PCIBus *bus, void *state), 398 void *parent_state); 399 400 /* Use this wrapper when specific scan order is not required. */ 401 static inline 402 void pci_for_each_bus(PCIBus *bus, 403 void (*fn)(PCIBus *bus, void *opaque), 404 void *opaque) 405 { 406 pci_for_each_bus_depth_first(bus, NULL, fn, opaque); 407 } 408 409 PCIBus *pci_find_primary_bus(void); 410 PCIBus *pci_device_root_bus(const PCIDevice *d); 411 const char *pci_root_bus_path(PCIDevice *dev); 412 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn); 413 int pci_qdev_find_device(const char *id, PCIDevice **pdev); 414 void pci_bus_get_w64_range(PCIBus *bus, Range *range); 415 416 void pci_device_deassert_intx(PCIDevice *dev); 417 418 typedef AddressSpace *(*PCIIOMMUFunc)(PCIBus *, void *, int); 419 420 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev); 421 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque); 422 423 static inline void 424 pci_set_byte(uint8_t *config, uint8_t val) 425 { 426 *config = val; 427 } 428 429 static inline uint8_t 430 pci_get_byte(const uint8_t *config) 431 { 432 return *config; 433 } 434 435 static inline void 436 pci_set_word(uint8_t *config, uint16_t val) 437 { 438 stw_le_p(config, val); 439 } 440 441 static inline uint16_t 442 pci_get_word(const uint8_t *config) 443 { 444 return lduw_le_p(config); 445 } 446 447 static inline void 448 pci_set_long(uint8_t *config, uint32_t val) 449 { 450 stl_le_p(config, val); 451 } 452 453 static inline uint32_t 454 pci_get_long(const uint8_t *config) 455 { 456 return ldl_le_p(config); 457 } 458 459 static inline void 460 pci_set_quad(uint8_t *config, uint64_t val) 461 { 462 cpu_to_le64w((uint64_t *)config, val); 463 } 464 465 static inline uint64_t 466 pci_get_quad(const uint8_t *config) 467 { 468 return le64_to_cpup((const uint64_t *)config); 469 } 470 471 static inline void 472 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val) 473 { 474 pci_set_word(&pci_config[PCI_VENDOR_ID], val); 475 } 476 477 static inline void 478 pci_config_set_device_id(uint8_t *pci_config, uint16_t val) 479 { 480 pci_set_word(&pci_config[PCI_DEVICE_ID], val); 481 } 482 483 static inline void 484 pci_config_set_revision(uint8_t *pci_config, uint8_t val) 485 { 486 pci_set_byte(&pci_config[PCI_REVISION_ID], val); 487 } 488 489 static inline void 490 pci_config_set_class(uint8_t *pci_config, uint16_t val) 491 { 492 pci_set_word(&pci_config[PCI_CLASS_DEVICE], val); 493 } 494 495 static inline void 496 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val) 497 { 498 pci_set_byte(&pci_config[PCI_CLASS_PROG], val); 499 } 500 501 static inline void 502 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val) 503 { 504 pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val); 505 } 506 507 /* 508 * helper functions to do bit mask operation on configuration space. 509 * Just to set bit, use test-and-set and discard returned value. 510 * Just to clear bit, use test-and-clear and discard returned value. 511 * NOTE: They aren't atomic. 512 */ 513 static inline uint8_t 514 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask) 515 { 516 uint8_t val = pci_get_byte(config); 517 pci_set_byte(config, val & ~mask); 518 return val & mask; 519 } 520 521 static inline uint8_t 522 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask) 523 { 524 uint8_t val = pci_get_byte(config); 525 pci_set_byte(config, val | mask); 526 return val & mask; 527 } 528 529 static inline uint16_t 530 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask) 531 { 532 uint16_t val = pci_get_word(config); 533 pci_set_word(config, val & ~mask); 534 return val & mask; 535 } 536 537 static inline uint16_t 538 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask) 539 { 540 uint16_t val = pci_get_word(config); 541 pci_set_word(config, val | mask); 542 return val & mask; 543 } 544 545 static inline uint32_t 546 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask) 547 { 548 uint32_t val = pci_get_long(config); 549 pci_set_long(config, val & ~mask); 550 return val & mask; 551 } 552 553 static inline uint32_t 554 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask) 555 { 556 uint32_t val = pci_get_long(config); 557 pci_set_long(config, val | mask); 558 return val & mask; 559 } 560 561 static inline uint64_t 562 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask) 563 { 564 uint64_t val = pci_get_quad(config); 565 pci_set_quad(config, val & ~mask); 566 return val & mask; 567 } 568 569 static inline uint64_t 570 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask) 571 { 572 uint64_t val = pci_get_quad(config); 573 pci_set_quad(config, val | mask); 574 return val & mask; 575 } 576 577 /* Access a register specified by a mask */ 578 static inline void 579 pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg) 580 { 581 uint8_t val = pci_get_byte(config); 582 uint8_t rval = reg << ctz32(mask); 583 pci_set_byte(config, (~mask & val) | (mask & rval)); 584 } 585 586 static inline uint8_t 587 pci_get_byte_by_mask(uint8_t *config, uint8_t mask) 588 { 589 uint8_t val = pci_get_byte(config); 590 return (val & mask) >> ctz32(mask); 591 } 592 593 static inline void 594 pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg) 595 { 596 uint16_t val = pci_get_word(config); 597 uint16_t rval = reg << ctz32(mask); 598 pci_set_word(config, (~mask & val) | (mask & rval)); 599 } 600 601 static inline uint16_t 602 pci_get_word_by_mask(uint8_t *config, uint16_t mask) 603 { 604 uint16_t val = pci_get_word(config); 605 return (val & mask) >> ctz32(mask); 606 } 607 608 static inline void 609 pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg) 610 { 611 uint32_t val = pci_get_long(config); 612 uint32_t rval = reg << ctz32(mask); 613 pci_set_long(config, (~mask & val) | (mask & rval)); 614 } 615 616 static inline uint32_t 617 pci_get_long_by_mask(uint8_t *config, uint32_t mask) 618 { 619 uint32_t val = pci_get_long(config); 620 return (val & mask) >> ctz32(mask); 621 } 622 623 static inline void 624 pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg) 625 { 626 uint64_t val = pci_get_quad(config); 627 uint64_t rval = reg << ctz32(mask); 628 pci_set_quad(config, (~mask & val) | (mask & rval)); 629 } 630 631 static inline uint64_t 632 pci_get_quad_by_mask(uint8_t *config, uint64_t mask) 633 { 634 uint64_t val = pci_get_quad(config); 635 return (val & mask) >> ctz32(mask); 636 } 637 638 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction, 639 const char *name); 640 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, 641 bool multifunction, 642 const char *name); 643 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name); 644 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name); 645 646 qemu_irq pci_allocate_irq(PCIDevice *pci_dev); 647 void pci_set_irq(PCIDevice *pci_dev, int level); 648 649 static inline void pci_irq_assert(PCIDevice *pci_dev) 650 { 651 pci_set_irq(pci_dev, 1); 652 } 653 654 static inline void pci_irq_deassert(PCIDevice *pci_dev) 655 { 656 pci_set_irq(pci_dev, 0); 657 } 658 659 /* 660 * FIXME: PCI does not work this way. 661 * All the callers to this method should be fixed. 662 */ 663 static inline void pci_irq_pulse(PCIDevice *pci_dev) 664 { 665 pci_irq_assert(pci_dev); 666 pci_irq_deassert(pci_dev); 667 } 668 669 static inline int pci_is_express(const PCIDevice *d) 670 { 671 return d->cap_present & QEMU_PCI_CAP_EXPRESS; 672 } 673 674 static inline uint32_t pci_config_size(const PCIDevice *d) 675 { 676 return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE; 677 } 678 679 /* DMA access functions */ 680 static inline AddressSpace *pci_get_address_space(PCIDevice *dev) 681 { 682 return &dev->bus_master_as; 683 } 684 685 static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr, 686 void *buf, dma_addr_t len, DMADirection dir) 687 { 688 dma_memory_rw(pci_get_address_space(dev), addr, buf, len, dir); 689 return 0; 690 } 691 692 static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr, 693 void *buf, dma_addr_t len) 694 { 695 return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE); 696 } 697 698 static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr, 699 const void *buf, dma_addr_t len) 700 { 701 return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE); 702 } 703 704 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \ 705 static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev, \ 706 dma_addr_t addr) \ 707 { \ 708 return ld##_l##_dma(pci_get_address_space(dev), addr); \ 709 } \ 710 static inline void st##_s##_pci_dma(PCIDevice *dev, \ 711 dma_addr_t addr, uint##_bits##_t val) \ 712 { \ 713 st##_s##_dma(pci_get_address_space(dev), addr, val); \ 714 } 715 716 PCI_DMA_DEFINE_LDST(ub, b, 8); 717 PCI_DMA_DEFINE_LDST(uw_le, w_le, 16) 718 PCI_DMA_DEFINE_LDST(l_le, l_le, 32); 719 PCI_DMA_DEFINE_LDST(q_le, q_le, 64); 720 PCI_DMA_DEFINE_LDST(uw_be, w_be, 16) 721 PCI_DMA_DEFINE_LDST(l_be, l_be, 32); 722 PCI_DMA_DEFINE_LDST(q_be, q_be, 64); 723 724 #undef PCI_DMA_DEFINE_LDST 725 726 static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr, 727 dma_addr_t *plen, DMADirection dir) 728 { 729 void *buf; 730 731 buf = dma_memory_map(pci_get_address_space(dev), addr, plen, dir); 732 return buf; 733 } 734 735 static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len, 736 DMADirection dir, dma_addr_t access_len) 737 { 738 dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len); 739 } 740 741 static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev, 742 int alloc_hint) 743 { 744 qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev)); 745 } 746 747 extern const VMStateDescription vmstate_pci_device; 748 749 #define VMSTATE_PCI_DEVICE(_field, _state) { \ 750 .name = (stringify(_field)), \ 751 .size = sizeof(PCIDevice), \ 752 .vmsd = &vmstate_pci_device, \ 753 .flags = VMS_STRUCT, \ 754 .offset = vmstate_offset_value(_state, _field, PCIDevice), \ 755 } 756 757 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \ 758 .name = (stringify(_field)), \ 759 .size = sizeof(PCIDevice), \ 760 .vmsd = &vmstate_pci_device, \ 761 .flags = VMS_STRUCT|VMS_POINTER, \ 762 .offset = vmstate_offset_pointer(_state, _field, PCIDevice), \ 763 } 764 765 #endif 766