1 #ifndef QEMU_PCI_H 2 #define QEMU_PCI_H 3 4 #include "system/memory.h" 5 #include "system/dma.h" 6 #include "system/host_iommu_device.h" 7 8 /* PCI includes legacy ISA access. */ 9 #include "hw/isa/isa.h" 10 11 extern bool pci_available; 12 13 /* PCI bus */ 14 15 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 16 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 17 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 18 #define PCI_FUNC(devfn) ((devfn) & 0x07) 19 #define PCI_BUILD_BDF(bus, devfn) (((bus) << 8) | (devfn)) 20 #define PCI_BDF_TO_DEVFN(x) ((x) & 0xff) 21 #define PCI_BUS_MAX 256 22 #define PCI_DEVFN_MAX 256 23 #define PCI_SLOT_MAX 32 24 #define PCI_FUNC_MAX 8 25 26 #define PCI_SBDF(seg, bus, dev, func) \ 27 ((((uint32_t)(seg)) << 16) | \ 28 (PCI_BUILD_BDF(bus, PCI_DEVFN(dev, func)))) 29 30 /* Class, Vendor and Device IDs from Linux's pci_ids.h */ 31 #include "hw/pci/pci_ids.h" 32 33 /* QEMU-specific Vendor and Device ID definitions */ 34 35 /* IBM (0x1014) */ 36 #define PCI_DEVICE_ID_IBM_440GX 0x027f 37 #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff 38 39 /* Hitachi (0x1054) */ 40 #define PCI_VENDOR_ID_HITACHI 0x1054 41 #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e 42 43 /* Apple (0x106b) */ 44 #define PCI_DEVICE_ID_APPLE_343S1201 0x0010 45 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e 46 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f 47 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022 48 #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f 49 50 /* Realtek (0x10ec) */ 51 #define PCI_DEVICE_ID_REALTEK_8029 0x8029 52 53 /* Xilinx (0x10ee) */ 54 #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300 55 56 /* Marvell (0x11ab) */ 57 #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620 58 59 /* QEMU/Bochs VGA (0x1234) */ 60 #define PCI_VENDOR_ID_QEMU 0x1234 61 #define PCI_DEVICE_ID_QEMU_VGA 0x1111 62 #define PCI_DEVICE_ID_QEMU_IPMI 0x1112 63 64 /* VMWare (0x15ad) */ 65 #define PCI_VENDOR_ID_VMWARE 0x15ad 66 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 67 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710 68 #define PCI_DEVICE_ID_VMWARE_NET 0x0720 69 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730 70 #define PCI_DEVICE_ID_VMWARE_PVSCSI 0x07C0 71 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729 72 #define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0 73 74 /* Intel (0x8086) */ 75 #define PCI_DEVICE_ID_INTEL_82551IT 0x1209 76 #define PCI_DEVICE_ID_INTEL_82557 0x1229 77 #define PCI_DEVICE_ID_INTEL_82801IR 0x2922 78 79 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */ 80 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 81 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 82 #define PCI_SUBDEVICE_ID_QEMU 0x1100 83 84 /* legacy virtio-pci devices */ 85 #define PCI_DEVICE_ID_VIRTIO_NET 0x1000 86 #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001 87 #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002 88 #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003 89 #define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004 90 #define PCI_DEVICE_ID_VIRTIO_RNG 0x1005 91 #define PCI_DEVICE_ID_VIRTIO_9P 0x1009 92 #define PCI_DEVICE_ID_VIRTIO_VSOCK 0x1012 93 94 /* 95 * modern virtio-pci devices get their id assigned automatically, 96 * there is no need to add #defines here. It gets calculated as 97 * 98 * PCI_DEVICE_ID = PCI_DEVICE_ID_VIRTIO_10_BASE + 99 * virtio_bus_get_vdev_id(bus) 100 */ 101 #define PCI_DEVICE_ID_VIRTIO_10_BASE 0x1040 102 103 #define PCI_VENDOR_ID_REDHAT 0x1b36 104 #define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001 105 #define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002 106 #define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003 107 #define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004 108 #define PCI_DEVICE_ID_REDHAT_TEST 0x0005 109 #define PCI_DEVICE_ID_REDHAT_ROCKER 0x0006 110 #define PCI_DEVICE_ID_REDHAT_SDHCI 0x0007 111 #define PCI_DEVICE_ID_REDHAT_PCIE_HOST 0x0008 112 #define PCI_DEVICE_ID_REDHAT_PXB 0x0009 113 #define PCI_DEVICE_ID_REDHAT_BRIDGE_SEAT 0x000a 114 #define PCI_DEVICE_ID_REDHAT_PXB_PCIE 0x000b 115 #define PCI_DEVICE_ID_REDHAT_PCIE_RP 0x000c 116 #define PCI_DEVICE_ID_REDHAT_XHCI 0x000d 117 #define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000e 118 #define PCI_DEVICE_ID_REDHAT_MDPY 0x000f 119 #define PCI_DEVICE_ID_REDHAT_NVME 0x0010 120 #define PCI_DEVICE_ID_REDHAT_PVPANIC 0x0011 121 #define PCI_DEVICE_ID_REDHAT_ACPI_ERST 0x0012 122 #define PCI_DEVICE_ID_REDHAT_UFS 0x0013 123 #define PCI_DEVICE_ID_REDHAT_RISCV_IOMMU 0x0014 124 #define PCI_DEVICE_ID_REDHAT_QXL 0x0100 125 126 #define FMT_PCIBUS PRIx64 127 128 typedef uint64_t pcibus_t; 129 130 struct PCIHostDeviceAddress { 131 unsigned int domain; 132 unsigned int bus; 133 unsigned int slot; 134 unsigned int function; 135 }; 136 137 /* 138 * Represents the Address Type (AT) field in a PCI request, 139 * see MemTxAttrs.address_type 140 */ 141 typedef enum PCIAddressType { 142 PCI_AT_UNTRANSLATED = 0, /* Default when no attribute is set */ 143 PCI_AT_TRANSLATED = 1, 144 } PCIAddressType; 145 146 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, 147 uint32_t address, uint32_t data, int len); 148 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev, 149 uint32_t address, int len); 150 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, 151 pcibus_t addr, pcibus_t size, int type); 152 typedef void PCIUnregisterFunc(PCIDevice *pci_dev); 153 154 typedef void MSITriggerFunc(PCIDevice *dev, MSIMessage msg); 155 typedef MSIMessage MSIPrepareMessageFunc(PCIDevice *dev, unsigned vector); 156 typedef MSIMessage MSIxPrepareMessageFunc(PCIDevice *dev, unsigned vector); 157 158 typedef struct PCIIORegion { 159 pcibus_t addr; /* current PCI mapping address. -1 means not mapped */ 160 #define PCI_BAR_UNMAPPED (~(pcibus_t)0) 161 pcibus_t size; 162 uint8_t type; 163 MemoryRegion *memory; 164 MemoryRegion *address_space; 165 } PCIIORegion; 166 167 #define PCI_ROM_SLOT 6 168 #define PCI_NUM_REGIONS 7 169 170 enum { 171 QEMU_PCI_VGA_MEM, 172 QEMU_PCI_VGA_IO_LO, 173 QEMU_PCI_VGA_IO_HI, 174 QEMU_PCI_VGA_NUM_REGIONS, 175 }; 176 177 #define QEMU_PCI_VGA_MEM_BASE 0xa0000 178 #define QEMU_PCI_VGA_MEM_SIZE 0x20000 179 #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0 180 #define QEMU_PCI_VGA_IO_LO_SIZE 0xc 181 #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0 182 #define QEMU_PCI_VGA_IO_HI_SIZE 0x20 183 184 #include "hw/pci/pci_regs.h" 185 186 /* PCI HEADER_TYPE */ 187 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80 188 189 /* Size of the standard PCI config header */ 190 #define PCI_CONFIG_HEADER_SIZE 0x40 191 /* Size of the standard PCI config space */ 192 #define PCI_CONFIG_SPACE_SIZE 0x100 193 /* Size of the standard PCIe config space: 4KB */ 194 #define PCIE_CONFIG_SPACE_SIZE 0x1000 195 196 #define PCI_NUM_PINS 4 /* A-D */ 197 198 /* Bits in cap_present field. */ 199 enum { 200 QEMU_PCI_CAP_MSI = 0x1, 201 QEMU_PCI_CAP_MSIX = 0x2, 202 QEMU_PCI_CAP_EXPRESS = 0x4, 203 204 /* multifunction capable device */ 205 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3 206 QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR), 207 208 /* command register SERR bit enabled - unused since QEMU v5.0 */ 209 #define QEMU_PCI_CAP_SERR_BITNR 4 210 QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR), 211 /* Standard hot plug controller. */ 212 #define QEMU_PCI_SHPC_BITNR 5 213 QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR), 214 #define QEMU_PCI_SLOTID_BITNR 6 215 QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR), 216 /* PCI Express capability - Power Controller Present */ 217 #define QEMU_PCIE_SLTCAP_PCP_BITNR 7 218 QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR), 219 /* Link active status in endpoint capability is always set */ 220 #define QEMU_PCIE_LNKSTA_DLLLA_BITNR 8 221 QEMU_PCIE_LNKSTA_DLLLA = (1 << QEMU_PCIE_LNKSTA_DLLLA_BITNR), 222 #define QEMU_PCIE_EXTCAP_INIT_BITNR 9 223 QEMU_PCIE_EXTCAP_INIT = (1 << QEMU_PCIE_EXTCAP_INIT_BITNR), 224 #define QEMU_PCIE_CXL_BITNR 10 225 QEMU_PCIE_CAP_CXL = (1 << QEMU_PCIE_CXL_BITNR), 226 #define QEMU_PCIE_ERR_UNC_MASK_BITNR 11 227 QEMU_PCIE_ERR_UNC_MASK = (1 << QEMU_PCIE_ERR_UNC_MASK_BITNR), 228 #define QEMU_PCIE_ARI_NEXTFN_1_BITNR 12 229 QEMU_PCIE_ARI_NEXTFN_1 = (1 << QEMU_PCIE_ARI_NEXTFN_1_BITNR), 230 #define QEMU_PCIE_EXT_TAG_BITNR 13 231 QEMU_PCIE_EXT_TAG = (1 << QEMU_PCIE_EXT_TAG_BITNR), 232 #define QEMU_PCI_CAP_PM_BITNR 14 233 QEMU_PCI_CAP_PM = (1 << QEMU_PCI_CAP_PM_BITNR), 234 #define QEMU_PCI_SKIP_RESET_ON_CPR_BITNR 15 235 QEMU_PCI_SKIP_RESET_ON_CPR = (1 << QEMU_PCI_SKIP_RESET_ON_CPR_BITNR), 236 }; 237 238 typedef struct PCIINTxRoute { 239 enum { 240 PCI_INTX_ENABLED, 241 PCI_INTX_INVERTED, 242 PCI_INTX_DISABLED, 243 } mode; 244 int irq; 245 } PCIINTxRoute; 246 247 typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev); 248 typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector, 249 MSIMessage msg); 250 typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector); 251 typedef void (*MSIVectorPollNotifier)(PCIDevice *dev, 252 unsigned int vector_start, 253 unsigned int vector_end); 254 255 void pci_register_bar(PCIDevice *pci_dev, int region_num, 256 uint8_t attr, MemoryRegion *memory); 257 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, 258 MemoryRegion *io_lo, MemoryRegion *io_hi); 259 void pci_unregister_vga(PCIDevice *pci_dev); 260 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num); 261 262 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, 263 uint8_t offset, uint8_t size, 264 Error **errp); 265 266 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size); 267 268 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id); 269 270 271 uint32_t pci_default_read_config(PCIDevice *d, 272 uint32_t address, int len); 273 void pci_default_write_config(PCIDevice *d, 274 uint32_t address, uint32_t val, int len); 275 void pci_device_save(PCIDevice *s, QEMUFile *f); 276 int pci_device_load(PCIDevice *s, QEMUFile *f); 277 MemoryRegion *pci_address_space(PCIDevice *dev); 278 MemoryRegion *pci_address_space_io(PCIDevice *dev); 279 280 /* 281 * Should not normally be used by devices. For use by sPAPR target 282 * where QEMU emulates firmware. 283 */ 284 int pci_bar(PCIDevice *d, int reg); 285 286 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level); 287 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); 288 typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin); 289 290 #define TYPE_PCI_BUS "PCI" 291 OBJECT_DECLARE_TYPE(PCIBus, PCIBusClass, PCI_BUS) 292 #define TYPE_PCIE_BUS "PCIE" 293 #define TYPE_CXL_BUS "CXL" 294 295 typedef void (*pci_bus_dev_fn)(PCIBus *b, PCIDevice *d, void *opaque); 296 typedef void (*pci_bus_fn)(PCIBus *b, void *opaque); 297 typedef void *(*pci_bus_ret_fn)(PCIBus *b, void *opaque); 298 299 bool pci_bus_is_express(const PCIBus *bus); 300 301 void pci_root_bus_init(PCIBus *bus, size_t bus_size, DeviceState *parent, 302 const char *name, 303 MemoryRegion *mem, MemoryRegion *io, 304 uint8_t devfn_min, const char *typename); 305 PCIBus *pci_root_bus_new(DeviceState *parent, const char *name, 306 MemoryRegion *mem, MemoryRegion *io, 307 uint8_t devfn_min, const char *typename); 308 void pci_root_bus_cleanup(PCIBus *bus); 309 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, 310 void *irq_opaque, int nirq); 311 void pci_bus_map_irqs(PCIBus *bus, pci_map_irq_fn map_irq); 312 void pci_bus_irqs_cleanup(PCIBus *bus); 313 int pci_bus_get_irq_level(PCIBus *bus, int irq_num); 314 uint32_t pci_bus_get_slot_reserved_mask(PCIBus *bus); 315 void pci_bus_set_slot_reserved_mask(PCIBus *bus, uint32_t mask); 316 void pci_bus_clear_slot_reserved_mask(PCIBus *bus, uint32_t mask); 317 bool pci_bus_add_fw_cfg_extra_pci_roots(FWCfgState *fw_cfg, 318 PCIBus *bus, 319 Error **errp); 320 /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */ 321 static inline int pci_swizzle(int slot, int pin) 322 { 323 return (slot + pin) % PCI_NUM_PINS; 324 } 325 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin); 326 PCIBus *pci_register_root_bus(DeviceState *parent, const char *name, 327 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 328 void *irq_opaque, 329 MemoryRegion *mem, MemoryRegion *io, 330 uint8_t devfn_min, int nirq, 331 const char *typename); 332 void pci_unregister_root_bus(PCIBus *bus); 333 void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn); 334 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin); 335 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new); 336 void pci_bus_fire_intx_routing_notifier(PCIBus *bus); 337 void pci_device_set_intx_routing_notifier(PCIDevice *dev, 338 PCIINTxRoutingNotifier notifier); 339 void pci_device_reset(PCIDevice *dev); 340 341 void pci_init_nic_devices(PCIBus *bus, const char *default_model); 342 bool pci_init_nic_in_slot(PCIBus *rootbus, const char *default_model, 343 const char *alias, const char *devaddr); 344 PCIDevice *pci_vga_init(PCIBus *bus); 345 346 static inline PCIBus *pci_get_bus(const PCIDevice *dev) 347 { 348 return PCI_BUS(qdev_get_parent_bus(DEVICE(dev))); 349 } 350 int pci_bus_num(PCIBus *s); 351 void pci_bus_range(PCIBus *bus, int *min_bus, int *max_bus); 352 static inline int pci_dev_bus_num(const PCIDevice *dev) 353 { 354 return pci_bus_num(pci_get_bus(dev)); 355 } 356 357 int pci_bus_numa_node(PCIBus *bus); 358 void pci_for_each_device(PCIBus *bus, int bus_num, 359 pci_bus_dev_fn fn, 360 void *opaque); 361 void pci_for_each_device_reverse(PCIBus *bus, int bus_num, 362 pci_bus_dev_fn fn, 363 void *opaque); 364 void pci_for_each_device_under_bus(PCIBus *bus, 365 pci_bus_dev_fn fn, void *opaque); 366 void pci_for_each_device_under_bus_reverse(PCIBus *bus, 367 pci_bus_dev_fn fn, 368 void *opaque); 369 void pci_for_each_bus_depth_first(PCIBus *bus, pci_bus_ret_fn begin, 370 pci_bus_fn end, void *parent_state); 371 PCIDevice *pci_get_function_0(PCIDevice *pci_dev); 372 373 /* Use this wrapper when specific scan order is not required. */ 374 static inline 375 void pci_for_each_bus(PCIBus *bus, pci_bus_fn fn, void *opaque) 376 { 377 pci_for_each_bus_depth_first(bus, NULL, fn, opaque); 378 } 379 380 PCIBus *pci_device_root_bus(const PCIDevice *d); 381 const char *pci_root_bus_path(PCIDevice *dev); 382 bool pci_bus_bypass_iommu(PCIBus *bus); 383 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn); 384 int pci_qdev_find_device(const char *id, PCIDevice **pdev); 385 void pci_bus_get_w64_range(PCIBus *bus, Range *range); 386 387 void pci_device_deassert_intx(PCIDevice *dev); 388 389 /* Page Request Interface */ 390 typedef enum { 391 IOMMU_PRI_RESP_SUCCESS, 392 IOMMU_PRI_RESP_INVALID_REQUEST, 393 IOMMU_PRI_RESP_FAILURE, 394 } IOMMUPRIResponseCode; 395 396 typedef struct IOMMUPRIResponse { 397 IOMMUPRIResponseCode response_code; 398 uint16_t prgi; 399 } IOMMUPRIResponse; 400 401 struct IOMMUPRINotifier; 402 403 typedef void (*IOMMUPRINotify)(struct IOMMUPRINotifier *notifier, 404 IOMMUPRIResponse *response); 405 406 typedef struct IOMMUPRINotifier { 407 IOMMUPRINotify notify; 408 } IOMMUPRINotifier; 409 410 #define PCI_PRI_PRGI_MASK 0x1ffU 411 412 /** 413 * struct PCIIOMMUOps: callbacks structure for specific IOMMU handlers 414 * of a PCIBus 415 * 416 * Allows to modify the behavior of some IOMMU operations of the PCI 417 * framework for a set of devices on a PCI bus. 418 */ 419 typedef struct PCIIOMMUOps { 420 /** 421 * @get_address_space: get the address space for a set of devices 422 * on a PCI bus. 423 * 424 * Mandatory callback which returns a pointer to an #AddressSpace 425 * 426 * @bus: the #PCIBus being accessed. 427 * 428 * @opaque: the data passed to pci_setup_iommu(). 429 * 430 * @devfn: device and function number 431 */ 432 AddressSpace * (*get_address_space)(PCIBus *bus, void *opaque, int devfn); 433 /** 434 * @set_iommu_device: attach a HostIOMMUDevice to a vIOMMU 435 * 436 * Optional callback, if not implemented in vIOMMU, then vIOMMU can't 437 * retrieve host information from the associated HostIOMMUDevice. 438 * 439 * @bus: the #PCIBus of the PCI device. 440 * 441 * @opaque: the data passed to pci_setup_iommu(). 442 * 443 * @devfn: device and function number of the PCI device. 444 * 445 * @dev: the #HostIOMMUDevice to attach. 446 * 447 * @errp: pass an Error out only when return false 448 * 449 * Returns: true if HostIOMMUDevice is attached or else false with errp set. 450 */ 451 bool (*set_iommu_device)(PCIBus *bus, void *opaque, int devfn, 452 HostIOMMUDevice *dev, Error **errp); 453 /** 454 * @unset_iommu_device: detach a HostIOMMUDevice from a vIOMMU 455 * 456 * Optional callback. 457 * 458 * @bus: the #PCIBus of the PCI device. 459 * 460 * @opaque: the data passed to pci_setup_iommu(). 461 * 462 * @devfn: device and function number of the PCI device. 463 */ 464 void (*unset_iommu_device)(PCIBus *bus, void *opaque, int devfn); 465 /** 466 * @get_iotlb_info: get properties required to initialize a device IOTLB. 467 * 468 * Callback required if devices are allowed to cache translations. 469 * 470 * @opaque: the data passed to pci_setup_iommu(). 471 * 472 * @addr_width: the address width of the IOMMU (output parameter). 473 * 474 * @min_page_size: the page size of the IOMMU (output parameter). 475 */ 476 void (*get_iotlb_info)(void *opaque, uint8_t *addr_width, 477 uint32_t *min_page_size); 478 /** 479 * @init_iotlb_notifier: initialize an IOMMU notifier. 480 * 481 * Optional callback. 482 * 483 * @bus: the #PCIBus of the PCI device. 484 * 485 * @opaque: the data passed to pci_setup_iommu(). 486 * 487 * @devfn: device and function number of the PCI device. 488 * 489 * @n: the notifier to be initialized. 490 * 491 * @fn: the callback to be installed. 492 * 493 * @user_opaque: a user pointer that can be used to track a state. 494 */ 495 void (*init_iotlb_notifier)(PCIBus *bus, void *opaque, int devfn, 496 IOMMUNotifier *n, IOMMUNotify fn, 497 void *user_opaque); 498 /** 499 * @register_iotlb_notifier: setup an IOTLB invalidation notifier. 500 * 501 * Callback required if devices are allowed to cache translations. 502 * 503 * @bus: the #PCIBus of the PCI device. 504 * 505 * @opaque: the data passed to pci_setup_iommu(). 506 * 507 * @devfn: device and function number of the PCI device. 508 * 509 * @pasid: the pasid of the address space to watch. 510 * 511 * @n: the notifier to register. 512 */ 513 void (*register_iotlb_notifier)(PCIBus *bus, void *opaque, int devfn, 514 uint32_t pasid, IOMMUNotifier *n); 515 /** 516 * @unregister_iotlb_notifier: remove an IOTLB invalidation notifier. 517 * 518 * Callback required if devices are allowed to cache translations. 519 * 520 * @bus: the #PCIBus of the PCI device. 521 * 522 * @opaque: the data passed to pci_setup_iommu(). 523 * 524 * @devfn: device and function number of the PCI device. 525 * 526 * @pasid: the pasid of the address space to stop watching. 527 * 528 * @n: the notifier to unregister. 529 */ 530 void (*unregister_iotlb_notifier)(PCIBus *bus, void *opaque, int devfn, 531 uint32_t pasid, IOMMUNotifier *n); 532 /** 533 * @ats_request_translation: issue an ATS request. 534 * 535 * Callback required if devices are allowed to use the address 536 * translation service. 537 * 538 * @bus: the #PCIBus of the PCI device. 539 * 540 * @opaque: the data passed to pci_setup_iommu(). 541 * 542 * @devfn: device and function number of the PCI device. 543 * 544 * @pasid: the pasid of the address space to use for the request. 545 * 546 * @priv_req: privileged mode bit (PASID TLP). 547 * 548 * @exec_req: execute request bit (PASID TLP). 549 * 550 * @addr: start address of the memory range to be translated. 551 * 552 * @length: length of the memory range in bytes. 553 * 554 * @no_write: request a read-only translation (if supported). 555 * 556 * @result: buffer in which the TLB entries will be stored. 557 * 558 * @result_length: result buffer length. 559 * 560 * @err_count: number of untranslated subregions. 561 * 562 * Returns: the number of translations stored in the result buffer, or 563 * -ENOMEM if the buffer is not large enough. 564 */ 565 ssize_t (*ats_request_translation)(PCIBus *bus, void *opaque, int devfn, 566 uint32_t pasid, bool priv_req, 567 bool exec_req, hwaddr addr, 568 size_t length, bool no_write, 569 IOMMUTLBEntry *result, 570 size_t result_length, 571 uint32_t *err_count); 572 /** 573 * @pri_register_notifier: setup the PRI completion callback. 574 * 575 * Callback required if devices are allowed to use the page request 576 * interface. 577 * 578 * @bus: the #PCIBus of the PCI device. 579 * 580 * @opaque: the data passed to pci_setup_iommu(). 581 * 582 * @devfn: device and function number of the PCI device. 583 * 584 * @pasid: the pasid of the address space to track. 585 * 586 * @notifier: the notifier to register. 587 */ 588 void (*pri_register_notifier)(PCIBus *bus, void *opaque, int devfn, 589 uint32_t pasid, IOMMUPRINotifier *notifier); 590 /** 591 * @pri_unregister_notifier: remove the PRI completion callback. 592 * 593 * Callback required if devices are allowed to use the page request 594 * interface. 595 * 596 * @bus: the #PCIBus of the PCI device. 597 * 598 * @opaque: the data passed to pci_setup_iommu(). 599 * 600 * @devfn: device and function number of the PCI device. 601 * 602 * @pasid: the pasid of the address space to stop tracking. 603 */ 604 void (*pri_unregister_notifier)(PCIBus *bus, void *opaque, int devfn, 605 uint32_t pasid); 606 /** 607 * @pri_request_page: issue a PRI request. 608 * 609 * Callback required if devices are allowed to use the page request 610 * interface. 611 * 612 * @bus: the #PCIBus of the PCI device. 613 * 614 * @opaque: the data passed to pci_setup_iommu(). 615 * 616 * @devfn: device and function number of the PCI device. 617 * 618 * @pasid: the pasid of the address space to use for the request. 619 * 620 * @priv_req: privileged mode bit (PASID TLP). 621 * 622 * @exec_req: execute request bit (PASID TLP). 623 * 624 * @addr: untranslated address of the requested page. 625 * 626 * @lpig: last page in group. 627 * 628 * @prgi: page request group index. 629 * 630 * @is_read: request read access. 631 * 632 * @is_write: request write access. 633 */ 634 int (*pri_request_page)(PCIBus *bus, void *opaque, int devfn, 635 uint32_t pasid, bool priv_req, bool exec_req, 636 hwaddr addr, bool lpig, uint16_t prgi, bool is_read, 637 bool is_write); 638 } PCIIOMMUOps; 639 640 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev); 641 bool pci_device_set_iommu_device(PCIDevice *dev, HostIOMMUDevice *hiod, 642 Error **errp); 643 void pci_device_unset_iommu_device(PCIDevice *dev); 644 645 /** 646 * pci_iommu_get_iotlb_info: get properties required to initialize a 647 * device IOTLB. 648 * 649 * Returns 0 on success, or a negative errno otherwise. 650 * 651 * @dev: the device that wants to get the information. 652 * @addr_width: the address width of the IOMMU (output parameter). 653 * @min_page_size: the page size of the IOMMU (output parameter). 654 */ 655 int pci_iommu_get_iotlb_info(PCIDevice *dev, uint8_t *addr_width, 656 uint32_t *min_page_size); 657 658 /** 659 * pci_iommu_init_iotlb_notifier: initialize an IOMMU notifier. 660 * 661 * This function is used by devices before registering an IOTLB notifier. 662 * 663 * @dev: the device. 664 * @n: the notifier to be initialized. 665 * @fn: the callback to be installed. 666 * @opaque: a user pointer that can be used to track a state. 667 */ 668 int pci_iommu_init_iotlb_notifier(PCIDevice *dev, IOMMUNotifier *n, 669 IOMMUNotify fn, void *opaque); 670 671 /** 672 * pci_ats_request_translation: perform an ATS request. 673 * 674 * Returns the number of translations stored in @result in case of success, 675 * a negative error code otherwise. 676 * -ENOMEM is returned when the result buffer is not large enough to store 677 * all the translations. 678 * 679 * @dev: the ATS-capable PCI device. 680 * @pasid: the pasid of the address space in which the translation will be done. 681 * @priv_req: privileged mode bit (PASID TLP). 682 * @exec_req: execute request bit (PASID TLP). 683 * @addr: start address of the memory range to be translated. 684 * @length: length of the memory range in bytes. 685 * @no_write: request a read-only translation (if supported). 686 * @result: buffer in which the TLB entries will be stored. 687 * @result_length: result buffer length. 688 * @err_count: number of untranslated subregions. 689 */ 690 ssize_t pci_ats_request_translation(PCIDevice *dev, uint32_t pasid, 691 bool priv_req, bool exec_req, 692 hwaddr addr, size_t length, 693 bool no_write, IOMMUTLBEntry *result, 694 size_t result_length, 695 uint32_t *err_count); 696 697 /** 698 * pci_pri_request_page: perform a PRI request. 699 * 700 * Returns 0 if the PRI request has been sent to the guest OS, 701 * an error code otherwise. 702 * 703 * @dev: the PRI-capable PCI device. 704 * @pasid: the pasid of the address space in which the translation will be done. 705 * @priv_req: privileged mode bit (PASID TLP). 706 * @exec_req: execute request bit (PASID TLP). 707 * @addr: untranslated address of the requested page. 708 * @lpig: last page in group. 709 * @prgi: page request group index. 710 * @is_read: request read access. 711 * @is_write: request write access. 712 */ 713 int pci_pri_request_page(PCIDevice *dev, uint32_t pasid, bool priv_req, 714 bool exec_req, hwaddr addr, bool lpig, 715 uint16_t prgi, bool is_read, bool is_write); 716 717 /** 718 * pci_pri_register_notifier: register the PRI callback for a given address 719 * space. 720 * 721 * Returns 0 on success, an error code otherwise. 722 * 723 * @dev: the PRI-capable PCI device. 724 * @pasid: the pasid of the address space to track. 725 * @notifier: the notifier to register. 726 */ 727 int pci_pri_register_notifier(PCIDevice *dev, uint32_t pasid, 728 IOMMUPRINotifier *notifier); 729 730 /** 731 * pci_pri_unregister_notifier: remove the PRI callback from a given address 732 * space. 733 * 734 * @dev: the PRI-capable PCI device. 735 * @pasid: the pasid of the address space to stop tracking. 736 */ 737 void pci_pri_unregister_notifier(PCIDevice *dev, uint32_t pasid); 738 739 /** 740 * pci_iommu_register_iotlb_notifier: register a notifier for changes to 741 * IOMMU translation entries in a specific address space. 742 * 743 * Returns 0 on success, or a negative errno otherwise. 744 * 745 * @dev: the device that wants to get notified. 746 * @pasid: the pasid of the address space to track. 747 * @n: the notifier to register. 748 */ 749 int pci_iommu_register_iotlb_notifier(PCIDevice *dev, uint32_t pasid, 750 IOMMUNotifier *n); 751 752 /** 753 * pci_iommu_unregister_iotlb_notifier: unregister a notifier that has been 754 * registerd with pci_iommu_register_iotlb_notifier. 755 * 756 * Returns 0 on success, or a negative errno otherwise. 757 * 758 * @dev: the device that wants to stop notifications. 759 * @pasid: the pasid of the address space to stop tracking. 760 * @n: the notifier to unregister. 761 */ 762 int pci_iommu_unregister_iotlb_notifier(PCIDevice *dev, uint32_t pasid, 763 IOMMUNotifier *n); 764 765 /** 766 * pci_setup_iommu: Initialize specific IOMMU handlers for a PCIBus 767 * 768 * Let PCI host bridges define specific operations. 769 * 770 * @bus: the #PCIBus being updated. 771 * @ops: the #PCIIOMMUOps 772 * @opaque: passed to callbacks of the @ops structure. 773 */ 774 void pci_setup_iommu(PCIBus *bus, const PCIIOMMUOps *ops, void *opaque); 775 776 pcibus_t pci_bar_address(PCIDevice *d, 777 int reg, uint8_t type, pcibus_t size); 778 779 static inline void 780 pci_set_byte(uint8_t *config, uint8_t val) 781 { 782 *config = val; 783 } 784 785 static inline uint8_t 786 pci_get_byte(const uint8_t *config) 787 { 788 return *config; 789 } 790 791 static inline void 792 pci_set_word(uint8_t *config, uint16_t val) 793 { 794 stw_le_p(config, val); 795 } 796 797 static inline uint16_t 798 pci_get_word(const uint8_t *config) 799 { 800 return lduw_le_p(config); 801 } 802 803 static inline void 804 pci_set_long(uint8_t *config, uint32_t val) 805 { 806 stl_le_p(config, val); 807 } 808 809 static inline uint32_t 810 pci_get_long(const uint8_t *config) 811 { 812 return ldl_le_p(config); 813 } 814 815 /* 816 * PCI capabilities and/or their fields 817 * are generally DWORD aligned only so 818 * mechanism used by pci_set/get_quad() 819 * must be tolerant to unaligned pointers 820 * 821 */ 822 static inline void 823 pci_set_quad(uint8_t *config, uint64_t val) 824 { 825 stq_le_p(config, val); 826 } 827 828 static inline uint64_t 829 pci_get_quad(const uint8_t *config) 830 { 831 return ldq_le_p(config); 832 } 833 834 static inline void 835 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val) 836 { 837 pci_set_word(&pci_config[PCI_VENDOR_ID], val); 838 } 839 840 static inline void 841 pci_config_set_device_id(uint8_t *pci_config, uint16_t val) 842 { 843 pci_set_word(&pci_config[PCI_DEVICE_ID], val); 844 } 845 846 static inline void 847 pci_config_set_revision(uint8_t *pci_config, uint8_t val) 848 { 849 pci_set_byte(&pci_config[PCI_REVISION_ID], val); 850 } 851 852 static inline void 853 pci_config_set_class(uint8_t *pci_config, uint16_t val) 854 { 855 pci_set_word(&pci_config[PCI_CLASS_DEVICE], val); 856 } 857 858 static inline void 859 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val) 860 { 861 pci_set_byte(&pci_config[PCI_CLASS_PROG], val); 862 } 863 864 static inline void 865 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val) 866 { 867 pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val); 868 } 869 870 /* 871 * helper functions to do bit mask operation on configuration space. 872 * Just to set bit, use test-and-set and discard returned value. 873 * Just to clear bit, use test-and-clear and discard returned value. 874 * NOTE: They aren't atomic. 875 */ 876 static inline uint8_t 877 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask) 878 { 879 uint8_t val = pci_get_byte(config); 880 pci_set_byte(config, val & ~mask); 881 return val & mask; 882 } 883 884 static inline uint8_t 885 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask) 886 { 887 uint8_t val = pci_get_byte(config); 888 pci_set_byte(config, val | mask); 889 return val & mask; 890 } 891 892 static inline uint16_t 893 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask) 894 { 895 uint16_t val = pci_get_word(config); 896 pci_set_word(config, val & ~mask); 897 return val & mask; 898 } 899 900 static inline uint16_t 901 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask) 902 { 903 uint16_t val = pci_get_word(config); 904 pci_set_word(config, val | mask); 905 return val & mask; 906 } 907 908 static inline uint32_t 909 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask) 910 { 911 uint32_t val = pci_get_long(config); 912 pci_set_long(config, val & ~mask); 913 return val & mask; 914 } 915 916 static inline uint32_t 917 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask) 918 { 919 uint32_t val = pci_get_long(config); 920 pci_set_long(config, val | mask); 921 return val & mask; 922 } 923 924 static inline uint64_t 925 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask) 926 { 927 uint64_t val = pci_get_quad(config); 928 pci_set_quad(config, val & ~mask); 929 return val & mask; 930 } 931 932 static inline uint64_t 933 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask) 934 { 935 uint64_t val = pci_get_quad(config); 936 pci_set_quad(config, val | mask); 937 return val & mask; 938 } 939 940 /* Access a register specified by a mask */ 941 static inline void 942 pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg) 943 { 944 uint8_t val = pci_get_byte(config); 945 uint8_t rval; 946 947 assert(mask); 948 rval = reg << ctz32(mask); 949 pci_set_byte(config, (~mask & val) | (mask & rval)); 950 } 951 952 static inline void 953 pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg) 954 { 955 uint16_t val = pci_get_word(config); 956 uint16_t rval; 957 958 assert(mask); 959 rval = reg << ctz32(mask); 960 pci_set_word(config, (~mask & val) | (mask & rval)); 961 } 962 963 static inline void 964 pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg) 965 { 966 uint32_t val = pci_get_long(config); 967 uint32_t rval; 968 969 assert(mask); 970 rval = reg << ctz32(mask); 971 pci_set_long(config, (~mask & val) | (mask & rval)); 972 } 973 974 static inline void 975 pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg) 976 { 977 uint64_t val = pci_get_quad(config); 978 uint64_t rval; 979 980 assert(mask); 981 rval = reg << ctz32(mask); 982 pci_set_quad(config, (~mask & val) | (mask & rval)); 983 } 984 985 PCIDevice *pci_new_multifunction(int devfn, const char *name); 986 PCIDevice *pci_new(int devfn, const char *name); 987 bool pci_realize_and_unref(PCIDevice *dev, PCIBus *bus, Error **errp); 988 989 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, 990 const char *name); 991 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name); 992 993 void lsi53c8xx_handle_legacy_cmdline(DeviceState *lsi_dev); 994 995 qemu_irq pci_allocate_irq(PCIDevice *pci_dev); 996 void pci_set_irq(PCIDevice *pci_dev, int level); 997 int pci_irq_disabled(PCIDevice *d); 998 999 static inline void pci_irq_assert(PCIDevice *pci_dev) 1000 { 1001 pci_set_irq(pci_dev, 1); 1002 } 1003 1004 static inline void pci_irq_deassert(PCIDevice *pci_dev) 1005 { 1006 pci_set_irq(pci_dev, 0); 1007 } 1008 1009 MSIMessage pci_get_msi_message(PCIDevice *dev, int vector); 1010 void pci_set_enabled(PCIDevice *pci_dev, bool state); 1011 void pci_set_power(PCIDevice *pci_dev, bool state); 1012 int pci_pm_init(PCIDevice *pci_dev, uint8_t offset, Error **errp); 1013 1014 #endif 1015