1 #ifndef QEMU_PCI_H 2 #define QEMU_PCI_H 3 4 #include "exec/memory.h" 5 #include "sysemu/dma.h" 6 7 /* PCI includes legacy ISA access. */ 8 #include "hw/isa/isa.h" 9 10 extern bool pci_available; 11 12 /* PCI bus */ 13 14 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 15 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 16 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 17 #define PCI_FUNC(devfn) ((devfn) & 0x07) 18 #define PCI_BUILD_BDF(bus, devfn) ((bus << 8) | (devfn)) 19 #define PCI_BDF_TO_DEVFN(x) ((x) & 0xff) 20 #define PCI_BUS_MAX 256 21 #define PCI_DEVFN_MAX 256 22 #define PCI_SLOT_MAX 32 23 #define PCI_FUNC_MAX 8 24 25 /* Class, Vendor and Device IDs from Linux's pci_ids.h */ 26 #include "hw/pci/pci_ids.h" 27 28 /* QEMU-specific Vendor and Device ID definitions */ 29 30 /* IBM (0x1014) */ 31 #define PCI_DEVICE_ID_IBM_440GX 0x027f 32 #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff 33 34 /* Hitachi (0x1054) */ 35 #define PCI_VENDOR_ID_HITACHI 0x1054 36 #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e 37 38 /* Apple (0x106b) */ 39 #define PCI_DEVICE_ID_APPLE_343S1201 0x0010 40 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e 41 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f 42 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022 43 #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f 44 45 /* Realtek (0x10ec) */ 46 #define PCI_DEVICE_ID_REALTEK_8029 0x8029 47 48 /* Xilinx (0x10ee) */ 49 #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300 50 51 /* Marvell (0x11ab) */ 52 #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620 53 54 /* QEMU/Bochs VGA (0x1234) */ 55 #define PCI_VENDOR_ID_QEMU 0x1234 56 #define PCI_DEVICE_ID_QEMU_VGA 0x1111 57 #define PCI_DEVICE_ID_QEMU_IPMI 0x1112 58 59 /* VMWare (0x15ad) */ 60 #define PCI_VENDOR_ID_VMWARE 0x15ad 61 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 62 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710 63 #define PCI_DEVICE_ID_VMWARE_NET 0x0720 64 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730 65 #define PCI_DEVICE_ID_VMWARE_PVSCSI 0x07C0 66 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729 67 #define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0 68 69 /* Intel (0x8086) */ 70 #define PCI_DEVICE_ID_INTEL_82551IT 0x1209 71 #define PCI_DEVICE_ID_INTEL_82557 0x1229 72 #define PCI_DEVICE_ID_INTEL_82801IR 0x2922 73 74 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */ 75 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 76 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 77 #define PCI_SUBDEVICE_ID_QEMU 0x1100 78 79 /* legacy virtio-pci devices */ 80 #define PCI_DEVICE_ID_VIRTIO_NET 0x1000 81 #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001 82 #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002 83 #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003 84 #define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004 85 #define PCI_DEVICE_ID_VIRTIO_RNG 0x1005 86 #define PCI_DEVICE_ID_VIRTIO_9P 0x1009 87 #define PCI_DEVICE_ID_VIRTIO_VSOCK 0x1012 88 89 /* 90 * modern virtio-pci devices get their id assigned automatically, 91 * there is no need to add #defines here. It gets calculated as 92 * 93 * PCI_DEVICE_ID = PCI_DEVICE_ID_VIRTIO_10_BASE + 94 * virtio_bus_get_vdev_id(bus) 95 */ 96 #define PCI_DEVICE_ID_VIRTIO_10_BASE 0x1040 97 98 #define PCI_VENDOR_ID_REDHAT 0x1b36 99 #define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001 100 #define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002 101 #define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003 102 #define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004 103 #define PCI_DEVICE_ID_REDHAT_TEST 0x0005 104 #define PCI_DEVICE_ID_REDHAT_ROCKER 0x0006 105 #define PCI_DEVICE_ID_REDHAT_SDHCI 0x0007 106 #define PCI_DEVICE_ID_REDHAT_PCIE_HOST 0x0008 107 #define PCI_DEVICE_ID_REDHAT_PXB 0x0009 108 #define PCI_DEVICE_ID_REDHAT_BRIDGE_SEAT 0x000a 109 #define PCI_DEVICE_ID_REDHAT_PXB_PCIE 0x000b 110 #define PCI_DEVICE_ID_REDHAT_PCIE_RP 0x000c 111 #define PCI_DEVICE_ID_REDHAT_XHCI 0x000d 112 #define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000e 113 #define PCI_DEVICE_ID_REDHAT_MDPY 0x000f 114 #define PCI_DEVICE_ID_REDHAT_NVME 0x0010 115 #define PCI_DEVICE_ID_REDHAT_PVPANIC 0x0011 116 #define PCI_DEVICE_ID_REDHAT_ACPI_ERST 0x0012 117 #define PCI_DEVICE_ID_REDHAT_UFS 0x0013 118 #define PCI_DEVICE_ID_REDHAT_QXL 0x0100 119 120 #define FMT_PCIBUS PRIx64 121 122 typedef uint64_t pcibus_t; 123 124 struct PCIHostDeviceAddress { 125 unsigned int domain; 126 unsigned int bus; 127 unsigned int slot; 128 unsigned int function; 129 }; 130 131 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, 132 uint32_t address, uint32_t data, int len); 133 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev, 134 uint32_t address, int len); 135 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, 136 pcibus_t addr, pcibus_t size, int type); 137 typedef void PCIUnregisterFunc(PCIDevice *pci_dev); 138 139 typedef void MSITriggerFunc(PCIDevice *dev, MSIMessage msg); 140 typedef MSIMessage MSIPrepareMessageFunc(PCIDevice *dev, unsigned vector); 141 typedef MSIMessage MSIxPrepareMessageFunc(PCIDevice *dev, unsigned vector); 142 143 typedef struct PCIIORegion { 144 pcibus_t addr; /* current PCI mapping address. -1 means not mapped */ 145 #define PCI_BAR_UNMAPPED (~(pcibus_t)0) 146 pcibus_t size; 147 uint8_t type; 148 MemoryRegion *memory; 149 MemoryRegion *address_space; 150 } PCIIORegion; 151 152 #define PCI_ROM_SLOT 6 153 #define PCI_NUM_REGIONS 7 154 155 enum { 156 QEMU_PCI_VGA_MEM, 157 QEMU_PCI_VGA_IO_LO, 158 QEMU_PCI_VGA_IO_HI, 159 QEMU_PCI_VGA_NUM_REGIONS, 160 }; 161 162 #define QEMU_PCI_VGA_MEM_BASE 0xa0000 163 #define QEMU_PCI_VGA_MEM_SIZE 0x20000 164 #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0 165 #define QEMU_PCI_VGA_IO_LO_SIZE 0xc 166 #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0 167 #define QEMU_PCI_VGA_IO_HI_SIZE 0x20 168 169 #include "hw/pci/pci_regs.h" 170 171 /* PCI HEADER_TYPE */ 172 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80 173 174 /* Size of the standard PCI config header */ 175 #define PCI_CONFIG_HEADER_SIZE 0x40 176 /* Size of the standard PCI config space */ 177 #define PCI_CONFIG_SPACE_SIZE 0x100 178 /* Size of the standard PCIe config space: 4KB */ 179 #define PCIE_CONFIG_SPACE_SIZE 0x1000 180 181 #define PCI_NUM_PINS 4 /* A-D */ 182 183 /* Bits in cap_present field. */ 184 enum { 185 QEMU_PCI_CAP_MSI = 0x1, 186 QEMU_PCI_CAP_MSIX = 0x2, 187 QEMU_PCI_CAP_EXPRESS = 0x4, 188 189 /* multifunction capable device */ 190 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3 191 QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR), 192 193 /* command register SERR bit enabled - unused since QEMU v5.0 */ 194 #define QEMU_PCI_CAP_SERR_BITNR 4 195 QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR), 196 /* Standard hot plug controller. */ 197 #define QEMU_PCI_SHPC_BITNR 5 198 QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR), 199 #define QEMU_PCI_SLOTID_BITNR 6 200 QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR), 201 /* PCI Express capability - Power Controller Present */ 202 #define QEMU_PCIE_SLTCAP_PCP_BITNR 7 203 QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR), 204 /* Link active status in endpoint capability is always set */ 205 #define QEMU_PCIE_LNKSTA_DLLLA_BITNR 8 206 QEMU_PCIE_LNKSTA_DLLLA = (1 << QEMU_PCIE_LNKSTA_DLLLA_BITNR), 207 #define QEMU_PCIE_EXTCAP_INIT_BITNR 9 208 QEMU_PCIE_EXTCAP_INIT = (1 << QEMU_PCIE_EXTCAP_INIT_BITNR), 209 #define QEMU_PCIE_CXL_BITNR 10 210 QEMU_PCIE_CAP_CXL = (1 << QEMU_PCIE_CXL_BITNR), 211 #define QEMU_PCIE_ERR_UNC_MASK_BITNR 11 212 QEMU_PCIE_ERR_UNC_MASK = (1 << QEMU_PCIE_ERR_UNC_MASK_BITNR), 213 #define QEMU_PCIE_ARI_NEXTFN_1_BITNR 12 214 QEMU_PCIE_ARI_NEXTFN_1 = (1 << QEMU_PCIE_ARI_NEXTFN_1_BITNR), 215 }; 216 217 typedef struct PCIINTxRoute { 218 enum { 219 PCI_INTX_ENABLED, 220 PCI_INTX_INVERTED, 221 PCI_INTX_DISABLED, 222 } mode; 223 int irq; 224 } PCIINTxRoute; 225 226 typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev); 227 typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector, 228 MSIMessage msg); 229 typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector); 230 typedef void (*MSIVectorPollNotifier)(PCIDevice *dev, 231 unsigned int vector_start, 232 unsigned int vector_end); 233 234 void pci_register_bar(PCIDevice *pci_dev, int region_num, 235 uint8_t attr, MemoryRegion *memory); 236 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, 237 MemoryRegion *io_lo, MemoryRegion *io_hi); 238 void pci_unregister_vga(PCIDevice *pci_dev); 239 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num); 240 241 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, 242 uint8_t offset, uint8_t size, 243 Error **errp); 244 245 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size); 246 247 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id); 248 249 250 uint32_t pci_default_read_config(PCIDevice *d, 251 uint32_t address, int len); 252 void pci_default_write_config(PCIDevice *d, 253 uint32_t address, uint32_t val, int len); 254 void pci_device_save(PCIDevice *s, QEMUFile *f); 255 int pci_device_load(PCIDevice *s, QEMUFile *f); 256 MemoryRegion *pci_address_space(PCIDevice *dev); 257 MemoryRegion *pci_address_space_io(PCIDevice *dev); 258 259 /* 260 * Should not normally be used by devices. For use by sPAPR target 261 * where QEMU emulates firmware. 262 */ 263 int pci_bar(PCIDevice *d, int reg); 264 265 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level); 266 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); 267 typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin); 268 269 #define TYPE_PCI_BUS "PCI" 270 OBJECT_DECLARE_TYPE(PCIBus, PCIBusClass, PCI_BUS) 271 #define TYPE_PCIE_BUS "PCIE" 272 #define TYPE_CXL_BUS "CXL" 273 274 typedef void (*pci_bus_dev_fn)(PCIBus *b, PCIDevice *d, void *opaque); 275 typedef void (*pci_bus_fn)(PCIBus *b, void *opaque); 276 typedef void *(*pci_bus_ret_fn)(PCIBus *b, void *opaque); 277 278 bool pci_bus_is_express(const PCIBus *bus); 279 280 void pci_root_bus_init(PCIBus *bus, size_t bus_size, DeviceState *parent, 281 const char *name, 282 MemoryRegion *address_space_mem, 283 MemoryRegion *address_space_io, 284 uint8_t devfn_min, const char *typename); 285 PCIBus *pci_root_bus_new(DeviceState *parent, const char *name, 286 MemoryRegion *address_space_mem, 287 MemoryRegion *address_space_io, 288 uint8_t devfn_min, const char *typename); 289 void pci_root_bus_cleanup(PCIBus *bus); 290 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, 291 void *irq_opaque, int nirq); 292 void pci_bus_map_irqs(PCIBus *bus, pci_map_irq_fn map_irq); 293 void pci_bus_irqs_cleanup(PCIBus *bus); 294 int pci_bus_get_irq_level(PCIBus *bus, int irq_num); 295 uint32_t pci_bus_get_slot_reserved_mask(PCIBus *bus); 296 void pci_bus_set_slot_reserved_mask(PCIBus *bus, uint32_t mask); 297 void pci_bus_clear_slot_reserved_mask(PCIBus *bus, uint32_t mask); 298 /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */ 299 static inline int pci_swizzle(int slot, int pin) 300 { 301 return (slot + pin) % PCI_NUM_PINS; 302 } 303 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin); 304 PCIBus *pci_register_root_bus(DeviceState *parent, const char *name, 305 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 306 void *irq_opaque, 307 MemoryRegion *address_space_mem, 308 MemoryRegion *address_space_io, 309 uint8_t devfn_min, int nirq, 310 const char *typename); 311 void pci_unregister_root_bus(PCIBus *bus); 312 void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn); 313 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin); 314 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new); 315 void pci_bus_fire_intx_routing_notifier(PCIBus *bus); 316 void pci_device_set_intx_routing_notifier(PCIDevice *dev, 317 PCIINTxRoutingNotifier notifier); 318 void pci_device_reset(PCIDevice *dev); 319 320 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus, 321 const char *default_model, 322 const char *default_devaddr); 323 324 PCIDevice *pci_vga_init(PCIBus *bus); 325 326 static inline PCIBus *pci_get_bus(const PCIDevice *dev) 327 { 328 return PCI_BUS(qdev_get_parent_bus(DEVICE(dev))); 329 } 330 int pci_bus_num(PCIBus *s); 331 void pci_bus_range(PCIBus *bus, int *min_bus, int *max_bus); 332 static inline int pci_dev_bus_num(const PCIDevice *dev) 333 { 334 return pci_bus_num(pci_get_bus(dev)); 335 } 336 337 int pci_bus_numa_node(PCIBus *bus); 338 void pci_for_each_device(PCIBus *bus, int bus_num, 339 pci_bus_dev_fn fn, 340 void *opaque); 341 void pci_for_each_device_reverse(PCIBus *bus, int bus_num, 342 pci_bus_dev_fn fn, 343 void *opaque); 344 void pci_for_each_device_under_bus(PCIBus *bus, 345 pci_bus_dev_fn fn, void *opaque); 346 void pci_for_each_device_under_bus_reverse(PCIBus *bus, 347 pci_bus_dev_fn fn, 348 void *opaque); 349 void pci_for_each_bus_depth_first(PCIBus *bus, pci_bus_ret_fn begin, 350 pci_bus_fn end, void *parent_state); 351 PCIDevice *pci_get_function_0(PCIDevice *pci_dev); 352 353 /* Use this wrapper when specific scan order is not required. */ 354 static inline 355 void pci_for_each_bus(PCIBus *bus, pci_bus_fn fn, void *opaque) 356 { 357 pci_for_each_bus_depth_first(bus, NULL, fn, opaque); 358 } 359 360 PCIBus *pci_device_root_bus(const PCIDevice *d); 361 const char *pci_root_bus_path(PCIDevice *dev); 362 bool pci_bus_bypass_iommu(PCIBus *bus); 363 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn); 364 int pci_qdev_find_device(const char *id, PCIDevice **pdev); 365 void pci_bus_get_w64_range(PCIBus *bus, Range *range); 366 367 void pci_device_deassert_intx(PCIDevice *dev); 368 369 typedef AddressSpace *(*PCIIOMMUFunc)(PCIBus *, void *, int); 370 371 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev); 372 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque); 373 374 pcibus_t pci_bar_address(PCIDevice *d, 375 int reg, uint8_t type, pcibus_t size); 376 377 static inline void 378 pci_set_byte(uint8_t *config, uint8_t val) 379 { 380 *config = val; 381 } 382 383 static inline uint8_t 384 pci_get_byte(const uint8_t *config) 385 { 386 return *config; 387 } 388 389 static inline void 390 pci_set_word(uint8_t *config, uint16_t val) 391 { 392 stw_le_p(config, val); 393 } 394 395 static inline uint16_t 396 pci_get_word(const uint8_t *config) 397 { 398 return lduw_le_p(config); 399 } 400 401 static inline void 402 pci_set_long(uint8_t *config, uint32_t val) 403 { 404 stl_le_p(config, val); 405 } 406 407 static inline uint32_t 408 pci_get_long(const uint8_t *config) 409 { 410 return ldl_le_p(config); 411 } 412 413 /* 414 * PCI capabilities and/or their fields 415 * are generally DWORD aligned only so 416 * mechanism used by pci_set/get_quad() 417 * must be tolerant to unaligned pointers 418 * 419 */ 420 static inline void 421 pci_set_quad(uint8_t *config, uint64_t val) 422 { 423 stq_le_p(config, val); 424 } 425 426 static inline uint64_t 427 pci_get_quad(const uint8_t *config) 428 { 429 return ldq_le_p(config); 430 } 431 432 static inline void 433 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val) 434 { 435 pci_set_word(&pci_config[PCI_VENDOR_ID], val); 436 } 437 438 static inline void 439 pci_config_set_device_id(uint8_t *pci_config, uint16_t val) 440 { 441 pci_set_word(&pci_config[PCI_DEVICE_ID], val); 442 } 443 444 static inline void 445 pci_config_set_revision(uint8_t *pci_config, uint8_t val) 446 { 447 pci_set_byte(&pci_config[PCI_REVISION_ID], val); 448 } 449 450 static inline void 451 pci_config_set_class(uint8_t *pci_config, uint16_t val) 452 { 453 pci_set_word(&pci_config[PCI_CLASS_DEVICE], val); 454 } 455 456 static inline void 457 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val) 458 { 459 pci_set_byte(&pci_config[PCI_CLASS_PROG], val); 460 } 461 462 static inline void 463 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val) 464 { 465 pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val); 466 } 467 468 /* 469 * helper functions to do bit mask operation on configuration space. 470 * Just to set bit, use test-and-set and discard returned value. 471 * Just to clear bit, use test-and-clear and discard returned value. 472 * NOTE: They aren't atomic. 473 */ 474 static inline uint8_t 475 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask) 476 { 477 uint8_t val = pci_get_byte(config); 478 pci_set_byte(config, val & ~mask); 479 return val & mask; 480 } 481 482 static inline uint8_t 483 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask) 484 { 485 uint8_t val = pci_get_byte(config); 486 pci_set_byte(config, val | mask); 487 return val & mask; 488 } 489 490 static inline uint16_t 491 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask) 492 { 493 uint16_t val = pci_get_word(config); 494 pci_set_word(config, val & ~mask); 495 return val & mask; 496 } 497 498 static inline uint16_t 499 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask) 500 { 501 uint16_t val = pci_get_word(config); 502 pci_set_word(config, val | mask); 503 return val & mask; 504 } 505 506 static inline uint32_t 507 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask) 508 { 509 uint32_t val = pci_get_long(config); 510 pci_set_long(config, val & ~mask); 511 return val & mask; 512 } 513 514 static inline uint32_t 515 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask) 516 { 517 uint32_t val = pci_get_long(config); 518 pci_set_long(config, val | mask); 519 return val & mask; 520 } 521 522 static inline uint64_t 523 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask) 524 { 525 uint64_t val = pci_get_quad(config); 526 pci_set_quad(config, val & ~mask); 527 return val & mask; 528 } 529 530 static inline uint64_t 531 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask) 532 { 533 uint64_t val = pci_get_quad(config); 534 pci_set_quad(config, val | mask); 535 return val & mask; 536 } 537 538 /* Access a register specified by a mask */ 539 static inline void 540 pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg) 541 { 542 uint8_t val = pci_get_byte(config); 543 uint8_t rval; 544 545 assert(mask); 546 rval = reg << ctz32(mask); 547 pci_set_byte(config, (~mask & val) | (mask & rval)); 548 } 549 550 static inline void 551 pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg) 552 { 553 uint16_t val = pci_get_word(config); 554 uint16_t rval; 555 556 assert(mask); 557 rval = reg << ctz32(mask); 558 pci_set_word(config, (~mask & val) | (mask & rval)); 559 } 560 561 static inline void 562 pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg) 563 { 564 uint32_t val = pci_get_long(config); 565 uint32_t rval; 566 567 assert(mask); 568 rval = reg << ctz32(mask); 569 pci_set_long(config, (~mask & val) | (mask & rval)); 570 } 571 572 static inline void 573 pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg) 574 { 575 uint64_t val = pci_get_quad(config); 576 uint64_t rval; 577 578 assert(mask); 579 rval = reg << ctz32(mask); 580 pci_set_quad(config, (~mask & val) | (mask & rval)); 581 } 582 583 PCIDevice *pci_new_multifunction(int devfn, const char *name); 584 PCIDevice *pci_new(int devfn, const char *name); 585 bool pci_realize_and_unref(PCIDevice *dev, PCIBus *bus, Error **errp); 586 587 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, 588 const char *name); 589 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name); 590 591 void lsi53c8xx_handle_legacy_cmdline(DeviceState *lsi_dev); 592 593 qemu_irq pci_allocate_irq(PCIDevice *pci_dev); 594 void pci_set_irq(PCIDevice *pci_dev, int level); 595 596 static inline void pci_irq_assert(PCIDevice *pci_dev) 597 { 598 pci_set_irq(pci_dev, 1); 599 } 600 601 static inline void pci_irq_deassert(PCIDevice *pci_dev) 602 { 603 pci_set_irq(pci_dev, 0); 604 } 605 606 /* 607 * FIXME: PCI does not work this way. 608 * All the callers to this method should be fixed. 609 */ 610 static inline void pci_irq_pulse(PCIDevice *pci_dev) 611 { 612 pci_irq_assert(pci_dev); 613 pci_irq_deassert(pci_dev); 614 } 615 616 MSIMessage pci_get_msi_message(PCIDevice *dev, int vector); 617 void pci_set_power(PCIDevice *pci_dev, bool state); 618 619 #endif 620