1 /* 2 * QEMU SPAPR PCI BUS definitions 3 * 4 * Copyright (c) 2011 Alexey Kardashevskiy <aik@au1.ibm.com> 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #if !defined(__HW_SPAPR_H__) 20 #error Please include spapr.h before this file! 21 #endif 22 23 #if !defined(__HW_SPAPR_PCI_H__) 24 #define __HW_SPAPR_PCI_H__ 25 26 #include "hw/pci/pci.h" 27 #include "hw/pci/pci_host.h" 28 #include "hw/ppc/xics.h" 29 30 #define SPAPR_MSIX_MAX_DEVS 32 31 32 #define TYPE_SPAPR_PCI_HOST_BRIDGE "spapr-pci-host-bridge" 33 34 #define SPAPR_PCI_HOST_BRIDGE(obj) \ 35 OBJECT_CHECK(sPAPRPHBState, (obj), TYPE_SPAPR_PCI_HOST_BRIDGE) 36 37 #define SPAPR_PCI_HOST_BRIDGE_CLASS(klass) \ 38 OBJECT_CLASS_CHECK(sPAPRPHBClass, (klass), TYPE_SPAPR_PCI_HOST_BRIDGE) 39 #define SPAPR_PCI_HOST_BRIDGE_GET_CLASS(obj) \ 40 OBJECT_GET_CLASS(sPAPRPHBClass, (obj), TYPE_SPAPR_PCI_HOST_BRIDGE) 41 42 typedef struct sPAPRPHBClass sPAPRPHBClass; 43 typedef struct sPAPRPHBState sPAPRPHBState; 44 45 struct sPAPRPHBClass { 46 PCIHostBridgeClass parent_class; 47 48 void (*finish_realize)(sPAPRPHBState *sphb, Error **errp); 49 }; 50 51 struct sPAPRPHBState { 52 PCIHostState parent_obj; 53 54 int32_t index; 55 uint64_t buid; 56 char *dtbusname; 57 58 MemoryRegion memspace, iospace; 59 hwaddr mem_win_addr, mem_win_size, io_win_addr, io_win_size; 60 MemoryRegion memwindow, iowindow; 61 62 uint32_t dma_liobn; 63 uint64_t dma_window_start; 64 uint64_t dma_window_size; 65 sPAPRTCETable *tcet; 66 AddressSpace iommu_as; 67 68 struct spapr_pci_lsi { 69 uint32_t irq; 70 } lsi_table[PCI_NUM_PINS]; 71 72 struct spapr_pci_msi { 73 uint32_t config_addr; 74 uint32_t irq; 75 uint32_t nvec; 76 } msi_table[SPAPR_MSIX_MAX_DEVS]; 77 78 QLIST_ENTRY(sPAPRPHBState) list; 79 }; 80 81 #define SPAPR_PCI_BASE_BUID 0x800000020000000ULL 82 83 #define SPAPR_PCI_WINDOW_BASE 0x10000000000ULL 84 #define SPAPR_PCI_WINDOW_SPACING 0x1000000000ULL 85 #define SPAPR_PCI_MMIO_WIN_OFF 0xA0000000 86 #define SPAPR_PCI_MMIO_WIN_SIZE 0x20000000 87 #define SPAPR_PCI_IO_WIN_OFF 0x80000000 88 #define SPAPR_PCI_IO_WIN_SIZE 0x10000 89 90 #define SPAPR_PCI_MSI_WINDOW 0x40000000000ULL 91 92 #define SPAPR_PCI_MEM_WIN_BUS_OFFSET 0x80000000ULL 93 94 static inline qemu_irq spapr_phb_lsi_qirq(struct sPAPRPHBState *phb, int pin) 95 { 96 return xics_get_qirq(spapr->icp, phb->lsi_table[pin].irq); 97 } 98 99 PCIHostState *spapr_create_phb(sPAPREnvironment *spapr, int index); 100 101 int spapr_populate_pci_dt(sPAPRPHBState *phb, 102 uint32_t xics_phandle, 103 void *fdt); 104 105 void spapr_pci_msi_init(sPAPREnvironment *spapr, hwaddr addr); 106 107 void spapr_pci_rtas_init(void); 108 109 #endif /* __HW_SPAPR_PCI_H__ */ 110