1 /* 2 * QEMU SPAPR PCI BUS definitions 3 * 4 * Copyright (c) 2011 Alexey Kardashevskiy <aik@au1.ibm.com> 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #if !defined(__HW_SPAPR_H__) 20 #error Please include spapr.h before this file! 21 #endif 22 23 #if !defined(__HW_SPAPR_PCI_H__) 24 #define __HW_SPAPR_PCI_H__ 25 26 #include "hw/pci/pci.h" 27 #include "hw/pci/pci_host.h" 28 #include "hw/ppc/xics.h" 29 30 #define SPAPR_MSIX_MAX_DEVS 32 31 32 #define TYPE_SPAPR_PCI_HOST_BRIDGE "spapr-pci-host-bridge" 33 34 #define SPAPR_PCI_HOST_BRIDGE(obj) \ 35 OBJECT_CHECK(sPAPRPHBState, (obj), TYPE_SPAPR_PCI_HOST_BRIDGE) 36 37 typedef struct sPAPRPHBState { 38 PCIHostState parent_obj; 39 40 int32_t index; 41 uint64_t buid; 42 char *dtbusname; 43 44 MemoryRegion memspace, iospace; 45 hwaddr mem_win_addr, mem_win_size, io_win_addr, io_win_size; 46 hwaddr msi_win_addr; 47 MemoryRegion memwindow, iowindow, msiwindow; 48 49 uint32_t dma_liobn; 50 uint64_t dma_window_start; 51 uint64_t dma_window_size; 52 sPAPRTCETable *tcet; 53 AddressSpace iommu_as; 54 55 struct spapr_pci_lsi { 56 uint32_t irq; 57 } lsi_table[PCI_NUM_PINS]; 58 59 struct spapr_pci_msi { 60 uint32_t config_addr; 61 uint32_t irq; 62 uint32_t nvec; 63 } msi_table[SPAPR_MSIX_MAX_DEVS]; 64 65 QLIST_ENTRY(sPAPRPHBState) list; 66 } sPAPRPHBState; 67 68 #define SPAPR_PCI_BASE_BUID 0x800000020000000ULL 69 70 #define SPAPR_PCI_WINDOW_BASE 0x10000000000ULL 71 #define SPAPR_PCI_WINDOW_SPACING 0x1000000000ULL 72 #define SPAPR_PCI_MMIO_WIN_OFF 0xA0000000 73 #define SPAPR_PCI_MMIO_WIN_SIZE 0x20000000 74 #define SPAPR_PCI_IO_WIN_OFF 0x80000000 75 #define SPAPR_PCI_IO_WIN_SIZE 0x10000 76 #define SPAPR_PCI_MSI_WIN_OFF 0x90000000 77 78 #define SPAPR_PCI_MEM_WIN_BUS_OFFSET 0x80000000ULL 79 80 static inline qemu_irq spapr_phb_lsi_qirq(struct sPAPRPHBState *phb, int pin) 81 { 82 return xics_get_qirq(spapr->icp, phb->lsi_table[pin].irq); 83 } 84 85 PCIHostState *spapr_create_phb(sPAPREnvironment *spapr, int index); 86 87 int spapr_populate_pci_dt(sPAPRPHBState *phb, 88 uint32_t xics_phandle, 89 void *fdt); 90 91 void spapr_pci_rtas_init(void); 92 93 #endif /* __HW_SPAPR_PCI_H__ */ 94