1 /* 2 * QEMU SPAPR PCI BUS definitions 3 * 4 * Copyright (c) 2011 Alexey Kardashevskiy <aik@au1.ibm.com> 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #if !defined(__HW_SPAPR_H__) 20 #error Please include spapr.h before this file! 21 #endif 22 23 #if !defined(__HW_SPAPR_PCI_H__) 24 #define __HW_SPAPR_PCI_H__ 25 26 #include "hw/pci/pci.h" 27 #include "hw/pci/pci_host.h" 28 #include "hw/ppc/xics.h" 29 30 #define TYPE_SPAPR_PCI_HOST_BRIDGE "spapr-pci-host-bridge" 31 32 #define SPAPR_PCI_HOST_BRIDGE(obj) \ 33 OBJECT_CHECK(sPAPRPHBState, (obj), TYPE_SPAPR_PCI_HOST_BRIDGE) 34 35 #define SPAPR_PCI_DMA_MAX_WINDOWS 2 36 37 typedef struct sPAPRPHBState sPAPRPHBState; 38 39 typedef struct spapr_pci_msi { 40 uint32_t first_irq; 41 uint32_t num; 42 } spapr_pci_msi; 43 44 typedef struct spapr_pci_msi_mig { 45 uint32_t key; 46 spapr_pci_msi value; 47 } spapr_pci_msi_mig; 48 49 struct sPAPRPHBState { 50 PCIHostState parent_obj; 51 52 uint32_t index; 53 uint64_t buid; 54 char *dtbusname; 55 bool dr_enabled; 56 57 MemoryRegion memspace, iospace; 58 hwaddr mem_win_addr, mem_win_size, io_win_addr, io_win_size; 59 MemoryRegion memwindow, iowindow, msiwindow; 60 61 uint32_t dma_liobn[SPAPR_PCI_DMA_MAX_WINDOWS]; 62 hwaddr dma_win_addr, dma_win_size; 63 AddressSpace iommu_as; 64 MemoryRegion iommu_root; 65 66 struct spapr_pci_lsi { 67 uint32_t irq; 68 } lsi_table[PCI_NUM_PINS]; 69 70 GHashTable *msi; 71 /* Temporary cache for migration purposes */ 72 int32_t msi_devs_num; 73 spapr_pci_msi_mig *msi_devs; 74 75 QLIST_ENTRY(sPAPRPHBState) list; 76 77 bool ddw_enabled; 78 uint64_t page_size_mask; 79 uint64_t dma64_win_addr; 80 }; 81 82 #define SPAPR_PCI_MAX_INDEX 255 83 84 #define SPAPR_PCI_BASE_BUID 0x800000020000000ULL 85 86 #define SPAPR_PCI_MEM_WIN_BUS_OFFSET 0x80000000ULL 87 88 #define SPAPR_PCI_WINDOW_BASE 0x10000000000ULL 89 #define SPAPR_PCI_WINDOW_SPACING 0x1000000000ULL 90 #define SPAPR_PCI_MMIO_WIN_OFF 0xA0000000 91 #define SPAPR_PCI_MMIO_WIN_SIZE (SPAPR_PCI_WINDOW_SPACING - \ 92 SPAPR_PCI_MEM_WIN_BUS_OFFSET) 93 #define SPAPR_PCI_IO_WIN_OFF 0x80000000 94 #define SPAPR_PCI_IO_WIN_SIZE 0x10000 95 96 #define SPAPR_PCI_MSI_WINDOW 0x40000000000ULL 97 98 static inline qemu_irq spapr_phb_lsi_qirq(struct sPAPRPHBState *phb, int pin) 99 { 100 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 101 102 return xics_get_qirq(spapr->xics, phb->lsi_table[pin].irq); 103 } 104 105 PCIHostState *spapr_create_phb(sPAPRMachineState *spapr, int index); 106 107 int spapr_populate_pci_dt(sPAPRPHBState *phb, 108 uint32_t xics_phandle, 109 void *fdt); 110 111 void spapr_pci_msi_init(sPAPRMachineState *spapr, hwaddr addr); 112 113 void spapr_pci_rtas_init(void); 114 115 sPAPRPHBState *spapr_pci_find_phb(sPAPRMachineState *spapr, uint64_t buid); 116 PCIDevice *spapr_pci_find_dev(sPAPRMachineState *spapr, uint64_t buid, 117 uint32_t config_addr); 118 119 /* VFIO EEH hooks */ 120 #ifdef CONFIG_LINUX 121 bool spapr_phb_eeh_available(sPAPRPHBState *sphb); 122 int spapr_phb_vfio_eeh_set_option(sPAPRPHBState *sphb, 123 unsigned int addr, int option); 124 int spapr_phb_vfio_eeh_get_state(sPAPRPHBState *sphb, int *state); 125 int spapr_phb_vfio_eeh_reset(sPAPRPHBState *sphb, int option); 126 int spapr_phb_vfio_eeh_configure(sPAPRPHBState *sphb); 127 void spapr_phb_vfio_reset(DeviceState *qdev); 128 #else 129 static inline bool spapr_phb_eeh_available(sPAPRPHBState *sphb) 130 { 131 return false; 132 } 133 static inline int spapr_phb_vfio_eeh_set_option(sPAPRPHBState *sphb, 134 unsigned int addr, int option) 135 { 136 return RTAS_OUT_HW_ERROR; 137 } 138 static inline int spapr_phb_vfio_eeh_get_state(sPAPRPHBState *sphb, 139 int *state) 140 { 141 return RTAS_OUT_HW_ERROR; 142 } 143 static inline int spapr_phb_vfio_eeh_reset(sPAPRPHBState *sphb, int option) 144 { 145 return RTAS_OUT_HW_ERROR; 146 } 147 static inline int spapr_phb_vfio_eeh_configure(sPAPRPHBState *sphb) 148 { 149 return RTAS_OUT_HW_ERROR; 150 } 151 static inline void spapr_phb_vfio_reset(DeviceState *qdev) 152 { 153 } 154 #endif 155 156 void spapr_phb_dma_reset(sPAPRPHBState *sphb); 157 158 #endif /* __HW_SPAPR_PCI_H__ */ 159