1 /* 2 * QEMU SPAPR PCI BUS definitions 3 * 4 * Copyright (c) 2011 Alexey Kardashevskiy <aik@au1.ibm.com> 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef PCI_HOST_SPAPR_H 21 #define PCI_HOST_SPAPR_H 22 23 #include "hw/ppc/spapr.h" 24 #include "hw/pci/pci.h" 25 #include "hw/pci/pci_host.h" 26 #include "hw/ppc/xics.h" 27 #include "qom/object.h" 28 29 #define TYPE_SPAPR_PCI_HOST_BRIDGE "spapr-pci-host-bridge" 30 31 typedef struct SpaprPhbState SpaprPhbState; 32 DECLARE_INSTANCE_CHECKER(SpaprPhbState, SPAPR_PCI_HOST_BRIDGE, 33 TYPE_SPAPR_PCI_HOST_BRIDGE) 34 35 #define SPAPR_PCI_DMA_MAX_WINDOWS 2 36 37 38 typedef struct SpaprPciMsi { 39 uint32_t first_irq; 40 uint32_t num; 41 } SpaprPciMsi; 42 43 typedef struct SpaprPciMsiMig { 44 uint32_t key; 45 SpaprPciMsi value; 46 } SpaprPciMsiMig; 47 48 typedef struct SpaprPciLsi { 49 uint32_t irq; 50 } SpaprPciLsi; 51 52 typedef struct SpaprPhbPciNvGpuConfig SpaprPhbPciNvGpuConfig; 53 54 struct SpaprPhbState { 55 PCIHostState parent_obj; 56 57 uint32_t index; 58 uint64_t buid; 59 char *dtbusname; 60 bool dr_enabled; 61 62 MemoryRegion memspace, iospace; 63 hwaddr mem_win_addr, mem_win_size, mem64_win_addr, mem64_win_size; 64 uint64_t mem64_win_pciaddr; 65 hwaddr io_win_addr, io_win_size; 66 MemoryRegion mem32window, mem64window, iowindow, msiwindow; 67 68 uint32_t dma_liobn[SPAPR_PCI_DMA_MAX_WINDOWS]; 69 hwaddr dma_win_addr, dma_win_size; 70 AddressSpace iommu_as; 71 MemoryRegion iommu_root; 72 73 SpaprPciLsi lsi_table[PCI_NUM_PINS]; 74 75 GHashTable *msi; 76 /* Temporary cache for migration purposes */ 77 int32_t msi_devs_num; 78 SpaprPciMsiMig *msi_devs; 79 80 QLIST_ENTRY(SpaprPhbState) list; 81 82 bool ddw_enabled; 83 uint64_t page_size_mask; 84 uint64_t dma64_win_addr; 85 86 uint32_t numa_node; 87 88 bool pcie_ecs; /* Allow access to PCIe extended config space? */ 89 90 /* Fields for migration compatibility hacks */ 91 bool pre_2_8_migration; 92 uint32_t mig_liobn; 93 hwaddr mig_mem_win_addr, mig_mem_win_size; 94 hwaddr mig_io_win_addr, mig_io_win_size; 95 hwaddr nv2_gpa_win_addr; 96 hwaddr nv2_atsd_win_addr; 97 SpaprPhbPciNvGpuConfig *nvgpus; 98 bool pre_5_1_assoc; 99 }; 100 101 #define SPAPR_PCI_MEM_WIN_BUS_OFFSET 0x80000000ULL 102 #define SPAPR_PCI_MEM32_WIN_SIZE \ 103 ((1ULL << 32) - SPAPR_PCI_MEM_WIN_BUS_OFFSET) 104 #define SPAPR_PCI_MEM64_WIN_SIZE 0x10000000000ULL /* 1 TiB */ 105 106 /* All PCI outbound windows will be within this range */ 107 #define SPAPR_PCI_BASE (1ULL << 45) /* 32 TiB */ 108 #define SPAPR_PCI_LIMIT (1ULL << 46) /* 64 TiB */ 109 110 #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \ 111 SPAPR_PCI_MEM64_WIN_SIZE - 1) 112 113 #define SPAPR_PCI_IO_WIN_SIZE 0x10000 114 115 #define SPAPR_PCI_MSI_WINDOW 0x40000000000ULL 116 117 #define SPAPR_PCI_NV2RAM64_WIN_BASE SPAPR_PCI_LIMIT 118 #define SPAPR_PCI_NV2RAM64_WIN_SIZE (2 * TiB) /* For up to 6 GPUs 256GB each */ 119 120 /* Max number of these GPUsper a physical box */ 121 #define NVGPU_MAX_NUM 6 122 /* Max number of NVLinks per GPU in any physical box */ 123 #define NVGPU_MAX_LINKS 3 124 125 /* 126 * GPU RAM starts at 64TiB so huge DMA window to cover it all ends at 128TiB 127 * which is enough. We do not need DMA for ATSD so we put them at 128TiB. 128 */ 129 #define SPAPR_PCI_NV2ATSD_WIN_BASE (128 * TiB) 130 #define SPAPR_PCI_NV2ATSD_WIN_SIZE (NVGPU_MAX_NUM * NVGPU_MAX_LINKS * \ 131 64 * KiB) 132 133 int spapr_dt_phb(SpaprMachineState *spapr, SpaprPhbState *phb, 134 uint32_t intc_phandle, void *fdt, int *node_offset); 135 136 void spapr_pci_rtas_init(void); 137 138 SpaprPhbState *spapr_pci_find_phb(SpaprMachineState *spapr, uint64_t buid); 139 PCIDevice *spapr_pci_find_dev(SpaprMachineState *spapr, uint64_t buid, 140 uint32_t config_addr); 141 142 /* DRC callbacks */ 143 void spapr_phb_remove_pci_device_cb(DeviceState *dev); 144 int spapr_pci_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 145 void *fdt, int *fdt_start_offset, Error **errp); 146 147 /* VFIO EEH hooks */ 148 #ifdef CONFIG_LINUX 149 bool spapr_phb_eeh_available(SpaprPhbState *sphb); 150 int spapr_phb_vfio_eeh_set_option(SpaprPhbState *sphb, 151 unsigned int addr, int option); 152 int spapr_phb_vfio_eeh_get_state(SpaprPhbState *sphb, int *state); 153 int spapr_phb_vfio_eeh_reset(SpaprPhbState *sphb, int option); 154 int spapr_phb_vfio_eeh_configure(SpaprPhbState *sphb); 155 void spapr_phb_vfio_reset(DeviceState *qdev); 156 void spapr_phb_nvgpu_setup(SpaprPhbState *sphb, Error **errp); 157 void spapr_phb_nvgpu_free(SpaprPhbState *sphb); 158 void spapr_phb_nvgpu_populate_dt(SpaprPhbState *sphb, void *fdt, int bus_off, 159 Error **errp); 160 void spapr_phb_nvgpu_ram_populate_dt(SpaprPhbState *sphb, void *fdt); 161 void spapr_phb_nvgpu_populate_pcidev_dt(PCIDevice *dev, void *fdt, int offset, 162 SpaprPhbState *sphb); 163 #else 164 static inline bool spapr_phb_eeh_available(SpaprPhbState *sphb) 165 { 166 return false; 167 } 168 static inline int spapr_phb_vfio_eeh_set_option(SpaprPhbState *sphb, 169 unsigned int addr, int option) 170 { 171 return RTAS_OUT_HW_ERROR; 172 } 173 static inline int spapr_phb_vfio_eeh_get_state(SpaprPhbState *sphb, 174 int *state) 175 { 176 return RTAS_OUT_HW_ERROR; 177 } 178 static inline int spapr_phb_vfio_eeh_reset(SpaprPhbState *sphb, int option) 179 { 180 return RTAS_OUT_HW_ERROR; 181 } 182 static inline int spapr_phb_vfio_eeh_configure(SpaprPhbState *sphb) 183 { 184 return RTAS_OUT_HW_ERROR; 185 } 186 static inline void spapr_phb_vfio_reset(DeviceState *qdev) 187 { 188 } 189 static inline void spapr_phb_nvgpu_setup(SpaprPhbState *sphb, Error **errp) 190 { 191 } 192 static inline void spapr_phb_nvgpu_free(SpaprPhbState *sphb) 193 { 194 } 195 static inline void spapr_phb_nvgpu_populate_dt(SpaprPhbState *sphb, void *fdt, 196 int bus_off, Error **errp) 197 { 198 } 199 static inline void spapr_phb_nvgpu_ram_populate_dt(SpaprPhbState *sphb, 200 void *fdt) 201 { 202 } 203 static inline void spapr_phb_nvgpu_populate_pcidev_dt(PCIDevice *dev, void *fdt, 204 int offset, 205 SpaprPhbState *sphb) 206 { 207 } 208 #endif 209 210 void spapr_phb_dma_reset(SpaprPhbState *sphb); 211 212 static inline unsigned spapr_phb_windows_supported(SpaprPhbState *sphb) 213 { 214 return sphb->ddw_enabled ? SPAPR_PCI_DMA_MAX_WINDOWS : 1; 215 } 216 217 #endif /* PCI_HOST_SPAPR_H */ 218