1 /* 2 * q35.h 3 * 4 * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp> 5 * VA Linux Systems Japan K.K. 6 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, see <http://www.gnu.org/licenses/> 20 */ 21 22 #ifndef HW_Q35_H 23 #define HW_Q35_H 24 25 #include "hw/pci/pci.h" 26 #include "hw/pci/pcie_host.h" 27 #include "hw/pci-host/pam.h" 28 #include "qemu/units.h" 29 #include "qemu/range.h" 30 #include "qom/object.h" 31 32 #define TYPE_Q35_HOST_DEVICE "q35-pcihost" 33 typedef struct Q35PCIHost Q35PCIHost; 34 DECLARE_INSTANCE_CHECKER(Q35PCIHost, Q35_HOST_DEVICE, 35 TYPE_Q35_HOST_DEVICE) 36 37 #define TYPE_MCH_PCI_DEVICE "mch" 38 typedef struct MCHPCIState MCHPCIState; 39 DECLARE_INSTANCE_CHECKER(MCHPCIState, MCH_PCI_DEVICE, 40 TYPE_MCH_PCI_DEVICE) 41 42 struct MCHPCIState { 43 /*< private >*/ 44 PCIDevice parent_obj; 45 /*< public >*/ 46 47 MemoryRegion *ram_memory; 48 MemoryRegion *pci_address_space; 49 MemoryRegion *system_memory; 50 MemoryRegion *address_space_io; 51 PAMMemoryRegion pam_regions[13]; 52 MemoryRegion smram_region, open_high_smram; 53 MemoryRegion smram, low_smram, high_smram; 54 MemoryRegion tseg_blackhole, tseg_window; 55 MemoryRegion smbase_blackhole, smbase_window; 56 bool has_smram_at_smbase; 57 Range pci_hole; 58 uint64_t below_4g_mem_size; 59 uint64_t above_4g_mem_size; 60 uint64_t pci_hole64_size; 61 uint32_t short_root_bus; 62 uint16_t ext_tseg_mbytes; 63 }; 64 65 struct Q35PCIHost { 66 /*< private >*/ 67 PCIExpressHost parent_obj; 68 /*< public >*/ 69 70 bool pci_hole64_fix; 71 MCHPCIState mch; 72 }; 73 74 #define Q35_MASK(bit, ms_bit, ls_bit) \ 75 ((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1))) 76 77 /* 78 * gmch part 79 */ 80 81 #define MCH_HOST_PROP_RAM_MEM "ram-mem" 82 #define MCH_HOST_PROP_PCI_MEM "pci-mem" 83 #define MCH_HOST_PROP_SYSTEM_MEM "system-mem" 84 #define MCH_HOST_PROP_IO_MEM "io-mem" 85 86 /* PCI configuration */ 87 #define MCH_HOST_BRIDGE "MCH" 88 89 #define MCH_HOST_BRIDGE_CONFIG_ADDR 0xcf8 90 #define MCH_HOST_BRIDGE_CONFIG_DATA 0xcfc 91 92 /* D0:F0 configuration space */ 93 #define MCH_HOST_BRIDGE_REVISION_DEFAULT 0x0 94 95 #define MCH_HOST_BRIDGE_EXT_TSEG_MBYTES 0x50 96 #define MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_SIZE 2 97 #define MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY 0xffff 98 #define MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_MAX 0xfff 99 100 #define MCH_HOST_BRIDGE_SMBASE_SIZE (128 * KiB) 101 #define MCH_HOST_BRIDGE_SMBASE_ADDR 0x30000 102 #define MCH_HOST_BRIDGE_F_SMBASE 0x9c 103 #define MCH_HOST_BRIDGE_F_SMBASE_QUERY 0xff 104 #define MCH_HOST_BRIDGE_F_SMBASE_IN_RAM 0x01 105 #define MCH_HOST_BRIDGE_F_SMBASE_LCK 0x02 106 107 #define MCH_HOST_BRIDGE_PCIEXBAR 0x60 /* 64bit register */ 108 #define MCH_HOST_BRIDGE_PCIEXBAR_SIZE 8 /* 64bit register */ 109 #define MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT 0xb0000000 110 #define MCH_HOST_BRIDGE_PCIEXBAR_MAX (0x10000000) /* 256M */ 111 #define MCH_HOST_BRIDGE_PCIEXBAR_ADMSK Q35_MASK(64, 35, 28) 112 #define MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK ((uint64_t)(1 << 26)) 113 #define MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK ((uint64_t)(1 << 25)) 114 #define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK ((uint64_t)(0x3 << 1)) 115 #define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M ((uint64_t)(0x0 << 1)) 116 #define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M ((uint64_t)(0x1 << 1)) 117 #define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M ((uint64_t)(0x2 << 1)) 118 #define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD ((uint64_t)(0x3 << 1)) 119 #define MCH_HOST_BRIDGE_PCIEXBAREN ((uint64_t)1) 120 121 #define MCH_HOST_BRIDGE_PAM_NB 7 122 #define MCH_HOST_BRIDGE_PAM_SIZE 7 123 #define MCH_HOST_BRIDGE_PAM0 0x90 124 #define MCH_HOST_BRIDGE_PAM_BIOS_AREA 0xf0000 125 #define MCH_HOST_BRIDGE_PAM_AREA_SIZE 0x10000 /* 16KB */ 126 #define MCH_HOST_BRIDGE_PAM1 0x91 127 #define MCH_HOST_BRIDGE_PAM_EXPAN_AREA 0xc0000 128 #define MCH_HOST_BRIDGE_PAM_EXPAN_SIZE 0x04000 129 #define MCH_HOST_BRIDGE_PAM2 0x92 130 #define MCH_HOST_BRIDGE_PAM3 0x93 131 #define MCH_HOST_BRIDGE_PAM4 0x94 132 #define MCH_HOST_BRIDGE_PAM_EXBIOS_AREA 0xe0000 133 #define MCH_HOST_BRIDGE_PAM_EXBIOS_SIZE 0x04000 134 #define MCH_HOST_BRIDGE_PAM5 0x95 135 #define MCH_HOST_BRIDGE_PAM6 0x96 136 #define MCH_HOST_BRIDGE_PAM_WE_HI ((uint8_t)(0x2 << 4)) 137 #define MCH_HOST_BRIDGE_PAM_RE_HI ((uint8_t)(0x1 << 4)) 138 #define MCH_HOST_BRIDGE_PAM_HI_MASK ((uint8_t)(0x3 << 4)) 139 #define MCH_HOST_BRIDGE_PAM_WE_LO ((uint8_t)0x2) 140 #define MCH_HOST_BRIDGE_PAM_RE_LO ((uint8_t)0x1) 141 #define MCH_HOST_BRIDGE_PAM_LO_MASK ((uint8_t)0x3) 142 #define MCH_HOST_BRIDGE_PAM_WE ((uint8_t)0x2) 143 #define MCH_HOST_BRIDGE_PAM_RE ((uint8_t)0x1) 144 #define MCH_HOST_BRIDGE_PAM_MASK ((uint8_t)0x3) 145 146 #define MCH_HOST_BRIDGE_SMRAM 0x9d 147 #define MCH_HOST_BRIDGE_SMRAM_SIZE 2 148 #define MCH_HOST_BRIDGE_SMRAM_D_OPEN ((uint8_t)(1 << 6)) 149 #define MCH_HOST_BRIDGE_SMRAM_D_CLS ((uint8_t)(1 << 5)) 150 #define MCH_HOST_BRIDGE_SMRAM_D_LCK ((uint8_t)(1 << 4)) 151 #define MCH_HOST_BRIDGE_SMRAM_G_SMRAME ((uint8_t)(1 << 3)) 152 #define MCH_HOST_BRIDGE_SMRAM_C_BASE_SEG_MASK ((uint8_t)0x7) 153 #define MCH_HOST_BRIDGE_SMRAM_C_BASE_SEG ((uint8_t)0x2) /* hardwired to b010 */ 154 #define MCH_HOST_BRIDGE_SMRAM_C_BASE 0xa0000 155 #define MCH_HOST_BRIDGE_SMRAM_C_END 0xc0000 156 #define MCH_HOST_BRIDGE_SMRAM_C_SIZE 0x20000 157 #define MCH_HOST_BRIDGE_UPPER_SYSTEM_BIOS_END 0x100000 158 #define MCH_HOST_BRIDGE_SMRAM_DEFAULT \ 159 MCH_HOST_BRIDGE_SMRAM_C_BASE_SEG 160 #define MCH_HOST_BRIDGE_SMRAM_WMASK \ 161 (MCH_HOST_BRIDGE_SMRAM_D_OPEN | \ 162 MCH_HOST_BRIDGE_SMRAM_D_CLS | \ 163 MCH_HOST_BRIDGE_SMRAM_D_LCK | \ 164 MCH_HOST_BRIDGE_SMRAM_G_SMRAME) 165 #define MCH_HOST_BRIDGE_SMRAM_WMASK_LCK \ 166 MCH_HOST_BRIDGE_SMRAM_D_CLS 167 168 #define MCH_HOST_BRIDGE_ESMRAMC 0x9e 169 #define MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME ((uint8_t)(1 << 7)) 170 #define MCH_HOST_BRIDGE_ESMRAMC_E_SMERR ((uint8_t)(1 << 6)) 171 #define MCH_HOST_BRIDGE_ESMRAMC_SM_CACHE ((uint8_t)(1 << 5)) 172 #define MCH_HOST_BRIDGE_ESMRAMC_SM_L1 ((uint8_t)(1 << 4)) 173 #define MCH_HOST_BRIDGE_ESMRAMC_SM_L2 ((uint8_t)(1 << 3)) 174 #define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK ((uint8_t)(0x3 << 1)) 175 #define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB ((uint8_t)(0x0 << 1)) 176 #define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB ((uint8_t)(0x1 << 1)) 177 #define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB ((uint8_t)(0x2 << 1)) 178 #define MCH_HOST_BRIDGE_ESMRAMC_T_EN ((uint8_t)1) 179 #define MCH_HOST_BRIDGE_ESMRAMC_DEFAULT \ 180 (MCH_HOST_BRIDGE_ESMRAMC_SM_CACHE | \ 181 MCH_HOST_BRIDGE_ESMRAMC_SM_L1 | \ 182 MCH_HOST_BRIDGE_ESMRAMC_SM_L2) 183 #define MCH_HOST_BRIDGE_ESMRAMC_WMASK \ 184 (MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME | \ 185 MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK | \ 186 MCH_HOST_BRIDGE_ESMRAMC_T_EN) 187 #define MCH_HOST_BRIDGE_ESMRAMC_WMASK_LCK 0 188 189 /* D1:F0 PCIE* port*/ 190 #define MCH_PCIE_DEV 1 191 #define MCH_PCIE_FUNC 0 192 193 uint64_t mch_mcfg_base(void); 194 195 /* 196 * Arbitrary but unique BNF number for IOAPIC device. 197 * 198 * TODO: make sure there would have no conflict with real PCI bus 199 */ 200 #define Q35_PSEUDO_BUS_PLATFORM (0xff) 201 #define Q35_PSEUDO_DEVFN_IOAPIC (0x00) 202 203 #endif /* HW_Q35_H */ 204