1 /* 2 * q35.h 3 * 4 * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp> 5 * VA Linux Systems Japan K.K. 6 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU Lesser General Public 19 * License along with this library; if not, see <http://www.gnu.org/licenses/> 20 */ 21 22 #ifndef HW_Q35_H 23 #define HW_Q35_H 24 25 #include "hw/hw.h" 26 #include "qemu/range.h" 27 #include "hw/isa/isa.h" 28 #include "hw/sysbus.h" 29 #include "hw/i386/pc.h" 30 #include "hw/isa/apm.h" 31 #include "hw/pci/pci.h" 32 #include "hw/pci/pcie_host.h" 33 #include "hw/acpi/acpi.h" 34 #include "hw/acpi/ich9.h" 35 #include "hw/pci-host/pam.h" 36 37 #define TYPE_Q35_HOST_DEVICE "q35-pcihost" 38 #define Q35_HOST_DEVICE(obj) \ 39 OBJECT_CHECK(Q35PCIHost, (obj), TYPE_Q35_HOST_DEVICE) 40 41 #define TYPE_MCH_PCI_DEVICE "mch" 42 #define MCH_PCI_DEVICE(obj) \ 43 OBJECT_CHECK(MCHPCIState, (obj), TYPE_MCH_PCI_DEVICE) 44 45 typedef struct MCHPCIState { 46 /*< private >*/ 47 PCIDevice parent_obj; 48 /*< public >*/ 49 50 MemoryRegion *ram_memory; 51 MemoryRegion *pci_address_space; 52 MemoryRegion *system_memory; 53 MemoryRegion *address_space_io; 54 PAMMemoryRegion pam_regions[13]; 55 MemoryRegion smram_region; 56 MemoryRegion pci_hole; 57 MemoryRegion pci_hole_64bit; 58 uint8_t smm_enabled; 59 ram_addr_t below_4g_mem_size; 60 ram_addr_t above_4g_mem_size; 61 PcGuestInfo *guest_info; 62 } MCHPCIState; 63 64 typedef struct Q35PCIHost { 65 /*< private >*/ 66 PCIExpressHost parent_obj; 67 /*< public >*/ 68 69 MCHPCIState mch; 70 } Q35PCIHost; 71 72 #define Q35_MASK(bit, ms_bit, ls_bit) \ 73 ((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1))) 74 75 /* 76 * gmch part 77 */ 78 79 /* PCI configuration */ 80 #define MCH_HOST_BRIDGE "MCH" 81 82 #define MCH_HOST_BRIDGE_CONFIG_ADDR 0xcf8 83 #define MCH_HOST_BRIDGE_CONFIG_DATA 0xcfc 84 85 /* D0:F0 configuration space */ 86 #define MCH_HOST_BRIDGE_REVISION_DEFUALT 0x0 87 88 #define MCH_HOST_BRIDGE_PCIEXBAR 0x60 /* 64bit register */ 89 #define MCH_HOST_BRIDGE_PCIEXBAR_SIZE 8 /* 64bit register */ 90 #define MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT 0xb0000000 91 #define MCH_HOST_BRIDGE_PCIEXBAR_MAX (0x10000000) /* 256M */ 92 #define MCH_HOST_BRIDGE_PCIEXBAR_ADMSK Q35_MASK(64, 35, 28) 93 #define MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK ((uint64_t)(1 << 26)) 94 #define MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK ((uint64_t)(1 << 25)) 95 #define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK ((uint64_t)(0x3 << 1)) 96 #define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M ((uint64_t)(0x0 << 1)) 97 #define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M ((uint64_t)(0x1 << 1)) 98 #define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M ((uint64_t)(0x2 << 1)) 99 #define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD ((uint64_t)(0x3 << 1)) 100 #define MCH_HOST_BRIDGE_PCIEXBAREN ((uint64_t)1) 101 102 #define MCH_HOST_BRIDGE_PAM_NB 7 103 #define MCH_HOST_BRIDGE_PAM_SIZE 7 104 #define MCH_HOST_BRIDGE_PAM0 0x90 105 #define MCH_HOST_BRIDGE_PAM_BIOS_AREA 0xf0000 106 #define MCH_HOST_BRIDGE_PAM_AREA_SIZE 0x10000 /* 16KB */ 107 #define MCH_HOST_BRIDGE_PAM1 0x91 108 #define MCH_HOST_BRIDGE_PAM_EXPAN_AREA 0xc0000 109 #define MCH_HOST_BRIDGE_PAM_EXPAN_SIZE 0x04000 110 #define MCH_HOST_BRIDGE_PAM2 0x92 111 #define MCH_HOST_BRIDGE_PAM3 0x93 112 #define MCH_HOST_BRIDGE_PAM4 0x94 113 #define MCH_HOST_BRIDGE_PAM_EXBIOS_AREA 0xe0000 114 #define MCH_HOST_BRIDGE_PAM_EXBIOS_SIZE 0x04000 115 #define MCH_HOST_BRIDGE_PAM5 0x95 116 #define MCH_HOST_BRIDGE_PAM6 0x96 117 #define MCH_HOST_BRIDGE_PAM_WE_HI ((uint8_t)(0x2 << 4)) 118 #define MCH_HOST_BRIDGE_PAM_RE_HI ((uint8_t)(0x1 << 4)) 119 #define MCH_HOST_BRIDGE_PAM_HI_MASK ((uint8_t)(0x3 << 4)) 120 #define MCH_HOST_BRIDGE_PAM_WE_LO ((uint8_t)0x2) 121 #define MCH_HOST_BRIDGE_PAM_RE_LO ((uint8_t)0x1) 122 #define MCH_HOST_BRIDGE_PAM_LO_MASK ((uint8_t)0x3) 123 #define MCH_HOST_BRIDGE_PAM_WE ((uint8_t)0x2) 124 #define MCH_HOST_BRIDGE_PAM_RE ((uint8_t)0x1) 125 #define MCH_HOST_BRIDGE_PAM_MASK ((uint8_t)0x3) 126 127 #define MCH_HOST_BRDIGE_SMRAM 0x9d 128 #define MCH_HOST_BRDIGE_SMRAM_SIZE 1 129 #define MCH_HOST_BRIDGE_SMRAM_DEFAULT ((uint8_t)0x2) 130 #define MCH_HOST_BRIDGE_SMRAM_D_OPEN ((uint8_t)(1 << 6)) 131 #define MCH_HOST_BRIDGE_SMRAM_D_CLS ((uint8_t)(1 << 5)) 132 #define MCH_HOST_BRIDGE_SMRAM_D_LCK ((uint8_t)(1 << 4)) 133 #define MCH_HOST_BRIDGE_SMRAM_G_SMRAME ((uint8_t)(1 << 3)) 134 #define MCH_HOST_BRIDGE_SMRAM_C_BASE_SEG_MASK ((uint8_t)0x7) 135 #define MCH_HOST_BRIDGE_SMRAM_C_BASE_SEG ((uint8_t)0x2) /* hardwired to b010 */ 136 #define MCH_HOST_BRIDGE_SMRAM_C_BASE 0xa0000 137 #define MCH_HOST_BRIDGE_SMRAM_C_END 0xc0000 138 #define MCH_HOST_BRIDGE_SMRAM_C_SIZE 0x20000 139 #define MCH_HOST_BRIDGE_UPPER_SYSTEM_BIOS_END 0x100000 140 141 #define MCH_HOST_BRIDGE_ESMRAMC 0x9e 142 #define MCH_HOST_BRDIGE_ESMRAMC_H_SMRAME ((uint8_t)(1 << 6)) 143 #define MCH_HOST_BRDIGE_ESMRAMC_E_SMERR ((uint8_t)(1 << 5)) 144 #define MCH_HOST_BRDIGE_ESMRAMC_SM_CACHE ((uint8_t)(1 << 4)) 145 #define MCH_HOST_BRDIGE_ESMRAMC_SM_L1 ((uint8_t)(1 << 3)) 146 #define MCH_HOST_BRDIGE_ESMRAMC_SM_L2 ((uint8_t)(1 << 2)) 147 #define MCH_HOST_BRDIGE_ESMRAMC_TSEG_SZ_MASK ((uint8_t)(0x3 << 1)) 148 #define MCH_HOST_BRDIGE_ESMRAMC_TSEG_SZ_1MB ((uint8_t)(0x0 << 1)) 149 #define MCH_HOST_BRDIGE_ESMRAMC_TSEG_SZ_2MB ((uint8_t)(0x1 << 1)) 150 #define MCH_HOST_BRDIGE_ESMRAMC_TSEG_SZ_8MB ((uint8_t)(0x2 << 1)) 151 #define MCH_HOST_BRDIGE_ESMRAMC_T_EN ((uint8_t)1) 152 153 /* D1:F0 PCIE* port*/ 154 #define MCH_PCIE_DEV 1 155 #define MCH_PCIE_FUNC 0 156 157 #endif /* HW_Q35_H */ 158