1 /* 2 * QEMU PowerPC PowerNV (POWER9) PHB4 model 3 * 4 * Copyright (c) 2018-2020, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #ifndef PCI_HOST_PNV_PHB4_H 11 #define PCI_HOST_PNV_PHB4_H 12 13 #include "hw/pci/pcie_host.h" 14 #include "hw/pci/pcie_port.h" 15 #include "hw/ppc/xive.h" 16 #include "qom/object.h" 17 18 typedef struct PnvPhb4PecState PnvPhb4PecState; 19 typedef struct PnvPhb4PecStack PnvPhb4PecStack; 20 typedef struct PnvPHB4 PnvPHB4; 21 typedef struct PnvPHB PnvPHB; 22 typedef struct PnvChip PnvChip; 23 24 /* 25 * We have one such address space wrapper per possible device under 26 * the PHB since they need to be assigned statically at qemu device 27 * creation time. The relationship to a PE is done later 28 * dynamically. This means we can potentially create a lot of these 29 * guys. Q35 stores them as some kind of radix tree but we never 30 * really need to do fast lookups so instead we simply keep a QLIST of 31 * them for now, we can add the radix if needed later on. 32 * 33 * We do cache the PE number to speed things up a bit though. 34 */ 35 typedef struct PnvPhb4DMASpace { 36 PCIBus *bus; 37 uint8_t devfn; 38 int pe_num; /* Cached PE number */ 39 #define PHB_INVALID_PE (-1) 40 PnvPHB4 *phb; 41 AddressSpace dma_as; 42 IOMMUMemoryRegion dma_mr; 43 MemoryRegion msi32_mr; 44 MemoryRegion msi64_mr; 45 QLIST_ENTRY(PnvPhb4DMASpace) list; 46 } PnvPhb4DMASpace; 47 48 #define TYPE_PNV_PHB4_ROOT_BUS "pnv-phb4-root" 49 50 /* 51 * PHB4 PCIe Host Bridge for PowerNV machines (POWER9) 52 */ 53 #define TYPE_PNV_PHB4 "pnv-phb4" 54 OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB4, PNV_PHB4) 55 56 #define PNV_PHB4_MAX_LSIs 8 57 #define PNV_PHB4_MAX_INTs 4096 58 #define PNV_PHB4_MAX_MIST (PNV_PHB4_MAX_INTs >> 2) 59 #define PNV_PHB4_MAX_MMIO_WINDOWS 32 60 #define PNV_PHB4_MIN_MMIO_WINDOWS 16 61 #define PNV_PHB4_NUM_REGS (0x3000 >> 3) 62 #define PNV_PHB4_MAX_PEs 512 63 #define PNV_PHB4_MAX_TVEs (PNV_PHB4_MAX_PEs * 2) 64 #define PNV_PHB4_MAX_PEEVs (PNV_PHB4_MAX_PEs / 64) 65 #define PNV_PHB4_MAX_MBEs (PNV_PHB4_MAX_MMIO_WINDOWS * 2) 66 67 #define PNV_PHB4_VERSION 0x000000a400000002ull 68 #define PNV_PHB4_DEVICE_ID 0x04c1 69 70 #define PCI_MMIO_TOTAL_SIZE (0x1ull << 60) 71 72 struct PnvPHB4 { 73 DeviceState parent; 74 75 PnvPHB *phb_base; 76 77 uint32_t chip_id; 78 uint32_t phb_id; 79 80 /* The owner PEC */ 81 PnvPhb4PecState *pec; 82 83 char bus_path[8]; 84 85 /* Main register images */ 86 uint64_t regs[PNV_PHB4_NUM_REGS]; 87 MemoryRegion mr_regs; 88 89 /* Extra SCOM-only register */ 90 uint64_t scom_hv_ind_addr_reg; 91 92 /* 93 * Geometry of the PHB. There are two types, small and big PHBs, a 94 * number of resources (number of PEs, windows etc...) are doubled 95 * for a big PHB 96 */ 97 bool big_phb; 98 99 /* Memory regions for MMIO space */ 100 MemoryRegion mr_mmio[PNV_PHB4_MAX_MMIO_WINDOWS]; 101 102 /* PCI side space */ 103 MemoryRegion pci_mmio; 104 MemoryRegion pci_io; 105 106 /* PCI registers (excluding pass-through) */ 107 #define PHB4_PEC_PCI_STK_REGS_COUNT 0xf 108 uint64_t pci_regs[PHB4_PEC_PCI_STK_REGS_COUNT]; 109 MemoryRegion pci_regs_mr; 110 111 /* Nest registers */ 112 #define PHB4_PEC_NEST_STK_REGS_COUNT 0x17 113 uint64_t nest_regs[PHB4_PEC_NEST_STK_REGS_COUNT]; 114 MemoryRegion nest_regs_mr; 115 116 /* PHB pass-through XSCOM */ 117 MemoryRegion phb_regs_mr; 118 119 /* Memory windows from PowerBus to PHB */ 120 MemoryRegion phbbar; 121 MemoryRegion intbar; 122 MemoryRegion mmbar0; 123 MemoryRegion mmbar1; 124 uint64_t mmio0_base; 125 uint64_t mmio0_size; 126 uint64_t mmio1_base; 127 uint64_t mmio1_size; 128 129 /* On-chip IODA tables */ 130 uint64_t ioda_LIST[PNV_PHB4_MAX_LSIs]; 131 uint64_t ioda_MIST[PNV_PHB4_MAX_MIST]; 132 uint64_t ioda_TVT[PNV_PHB4_MAX_TVEs]; 133 uint64_t ioda_MBT[PNV_PHB4_MAX_MBEs]; 134 uint64_t ioda_MDT[PNV_PHB4_MAX_PEs]; 135 uint64_t ioda_PEEV[PNV_PHB4_MAX_PEEVs]; 136 137 /* 138 * The internal PESTA/B is 2 bits per PE split into two tables, we 139 * store them in a single array here to avoid wasting space. 140 */ 141 uint8_t ioda_PEST_AB[PNV_PHB4_MAX_PEs]; 142 143 /* P9 Interrupt generation */ 144 XiveSource xsrc; 145 qemu_irq *qirqs; 146 147 QLIST_HEAD(, PnvPhb4DMASpace) dma_spaces; 148 }; 149 150 void pnv_phb4_pic_print_info(PnvPHB4 *phb, Monitor *mon); 151 int pnv_phb4_pec_get_phb_id(PnvPhb4PecState *pec, int stack_index); 152 void pnv_phb4_bus_init(DeviceState *dev, PnvPHB4 *phb); 153 extern const MemoryRegionOps pnv_phb4_xscom_ops; 154 155 /* 156 * PHB4 PEC (PCI Express Controller) 157 */ 158 #define TYPE_PNV_PHB4_PEC "pnv-phb4-pec" 159 OBJECT_DECLARE_TYPE(PnvPhb4PecState, PnvPhb4PecClass, PNV_PHB4_PEC) 160 161 struct PnvPhb4PecState { 162 DeviceState parent; 163 164 /* PEC number in chip */ 165 uint32_t index; 166 uint32_t chip_id; 167 168 MemoryRegion *system_memory; 169 170 /* Nest registers, excuding per-stack */ 171 #define PHB4_PEC_NEST_REGS_COUNT 0xf 172 uint64_t nest_regs[PHB4_PEC_NEST_REGS_COUNT]; 173 MemoryRegion nest_regs_mr; 174 175 /* PCI registers, excluding per-stack */ 176 #define PHB4_PEC_PCI_REGS_COUNT 0x3 177 uint64_t pci_regs[PHB4_PEC_PCI_REGS_COUNT]; 178 MemoryRegion pci_regs_mr; 179 180 /* PHBs */ 181 uint32_t num_phbs; 182 183 PnvChip *chip; 184 }; 185 186 187 struct PnvPhb4PecClass { 188 DeviceClass parent_class; 189 190 uint32_t (*xscom_nest_base)(PnvPhb4PecState *pec); 191 uint32_t xscom_nest_size; 192 uint32_t (*xscom_pci_base)(PnvPhb4PecState *pec); 193 uint32_t xscom_pci_size; 194 const char *compat; 195 int compat_size; 196 const char *stk_compat; 197 int stk_compat_size; 198 uint64_t version; 199 const char *phb_type; 200 const uint32_t *num_phbs; 201 }; 202 203 /* 204 * POWER10 definitions 205 */ 206 207 #define TYPE_PNV_PHB5 "pnv-phb5" 208 #define PNV_PHB5(obj) \ 209 OBJECT_CHECK(PnvPhb4, (obj), TYPE_PNV_PHB5) 210 211 #define PNV_PHB5_VERSION 0x000000a500000001ull 212 #define PNV_PHB5_DEVICE_ID 0x0652 213 214 #define TYPE_PNV_PHB5_PEC "pnv-phb5-pec" 215 #define PNV_PHB5_PEC(obj) \ 216 OBJECT_CHECK(PnvPhb4PecState, (obj), TYPE_PNV_PHB5_PEC) 217 218 #endif /* PCI_HOST_PNV_PHB4_H */ 219