1 /* 2 * QEMU PowerPC PowerNV (POWER9) PHB4 model 3 * 4 * Copyright (c) 2018-2020, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #ifndef PCI_HOST_PNV_PHB4_H 11 #define PCI_HOST_PNV_PHB4_H 12 13 #include "hw/pci/pcie_host.h" 14 #include "hw/pci/pcie_port.h" 15 #include "hw/ppc/xive.h" 16 #include "qom/object.h" 17 18 typedef struct PnvPhb4PecState PnvPhb4PecState; 19 typedef struct PnvPhb4PecStack PnvPhb4PecStack; 20 typedef struct PnvPHB4 PnvPHB4; 21 typedef struct PnvChip PnvChip; 22 23 /* 24 * We have one such address space wrapper per possible device under 25 * the PHB since they need to be assigned statically at qemu device 26 * creation time. The relationship to a PE is done later 27 * dynamically. This means we can potentially create a lot of these 28 * guys. Q35 stores them as some kind of radix tree but we never 29 * really need to do fast lookups so instead we simply keep a QLIST of 30 * them for now, we can add the radix if needed later on. 31 * 32 * We do cache the PE number to speed things up a bit though. 33 */ 34 typedef struct PnvPhb4DMASpace { 35 PCIBus *bus; 36 uint8_t devfn; 37 int pe_num; /* Cached PE number */ 38 #define PHB_INVALID_PE (-1) 39 PnvPHB4 *phb; 40 AddressSpace dma_as; 41 IOMMUMemoryRegion dma_mr; 42 MemoryRegion msi32_mr; 43 MemoryRegion msi64_mr; 44 QLIST_ENTRY(PnvPhb4DMASpace) list; 45 } PnvPhb4DMASpace; 46 47 /* 48 * PHB4 PCIe Root port 49 */ 50 #define TYPE_PNV_PHB4_ROOT_BUS "pnv-phb4-root-bus" 51 #define TYPE_PNV_PHB4_ROOT_PORT "pnv-phb4-root-port" 52 53 typedef struct PnvPHB4RootPort { 54 PCIESlot parent_obj; 55 } PnvPHB4RootPort; 56 57 /* 58 * PHB4 PCIe Host Bridge for PowerNV machines (POWER9) 59 */ 60 #define TYPE_PNV_PHB4 "pnv-phb4" 61 DECLARE_INSTANCE_CHECKER(PnvPHB4, PNV_PHB4, 62 TYPE_PNV_PHB4) 63 64 #define PNV_PHB4_MAX_LSIs 8 65 #define PNV_PHB4_MAX_INTs 4096 66 #define PNV_PHB4_MAX_MIST (PNV_PHB4_MAX_INTs >> 2) 67 #define PNV_PHB4_MAX_MMIO_WINDOWS 32 68 #define PNV_PHB4_MIN_MMIO_WINDOWS 16 69 #define PNV_PHB4_NUM_REGS (0x3000 >> 3) 70 #define PNV_PHB4_MAX_PEs 512 71 #define PNV_PHB4_MAX_TVEs (PNV_PHB4_MAX_PEs * 2) 72 #define PNV_PHB4_MAX_PEEVs (PNV_PHB4_MAX_PEs / 64) 73 #define PNV_PHB4_MAX_MBEs (PNV_PHB4_MAX_MMIO_WINDOWS * 2) 74 75 #define PNV_PHB4_VERSION 0x000000a400000002ull 76 #define PNV_PHB4_DEVICE_ID 0x04c1 77 78 #define PCI_MMIO_TOTAL_SIZE (0x1ull << 60) 79 80 struct PnvPHB4 { 81 PCIExpressHost parent_obj; 82 83 PnvPHB4RootPort root; 84 85 uint32_t chip_id; 86 uint32_t phb_id; 87 88 uint64_t version; 89 uint16_t device_id; 90 91 char bus_path[8]; 92 93 /* Main register images */ 94 uint64_t regs[PNV_PHB4_NUM_REGS]; 95 MemoryRegion mr_regs; 96 97 /* Extra SCOM-only register */ 98 uint64_t scom_hv_ind_addr_reg; 99 100 /* 101 * Geometry of the PHB. There are two types, small and big PHBs, a 102 * number of resources (number of PEs, windows etc...) are doubled 103 * for a big PHB 104 */ 105 bool big_phb; 106 107 /* Memory regions for MMIO space */ 108 MemoryRegion mr_mmio[PNV_PHB4_MAX_MMIO_WINDOWS]; 109 110 /* PCI side space */ 111 MemoryRegion pci_mmio; 112 MemoryRegion pci_io; 113 114 /* On-chip IODA tables */ 115 uint64_t ioda_LIST[PNV_PHB4_MAX_LSIs]; 116 uint64_t ioda_MIST[PNV_PHB4_MAX_MIST]; 117 uint64_t ioda_TVT[PNV_PHB4_MAX_TVEs]; 118 uint64_t ioda_MBT[PNV_PHB4_MAX_MBEs]; 119 uint64_t ioda_MDT[PNV_PHB4_MAX_PEs]; 120 uint64_t ioda_PEEV[PNV_PHB4_MAX_PEEVs]; 121 122 /* 123 * The internal PESTA/B is 2 bits per PE split into two tables, we 124 * store them in a single array here to avoid wasting space. 125 */ 126 uint8_t ioda_PEST_AB[PNV_PHB4_MAX_PEs]; 127 128 /* P9 Interrupt generation */ 129 XiveSource xsrc; 130 qemu_irq *qirqs; 131 132 PnvPhb4PecStack *stack; 133 134 QLIST_HEAD(, PnvPhb4DMASpace) dma_spaces; 135 }; 136 137 void pnv_phb4_pic_print_info(PnvPHB4 *phb, Monitor *mon); 138 void pnv_phb4_update_regions(PnvPhb4PecStack *stack); 139 extern const MemoryRegionOps pnv_phb4_xscom_ops; 140 141 /* 142 * PHB4 PEC (PCI Express Controller) 143 */ 144 #define TYPE_PNV_PHB4_PEC "pnv-phb4-pec" 145 typedef struct PnvPhb4PecClass PnvPhb4PecClass; 146 DECLARE_OBJ_CHECKERS(PnvPhb4PecState, PnvPhb4PecClass, 147 PNV_PHB4_PEC, TYPE_PNV_PHB4_PEC) 148 149 #define TYPE_PNV_PHB4_PEC_STACK "pnv-phb4-pec-stack" 150 DECLARE_INSTANCE_CHECKER(PnvPhb4PecStack, PNV_PHB4_PEC_STACK, 151 TYPE_PNV_PHB4_PEC_STACK) 152 153 /* Per-stack data */ 154 struct PnvPhb4PecStack { 155 DeviceState parent; 156 157 /* My own stack number */ 158 uint32_t stack_no; 159 160 /* Nest registers */ 161 #define PHB4_PEC_NEST_STK_REGS_COUNT 0x17 162 uint64_t nest_regs[PHB4_PEC_NEST_STK_REGS_COUNT]; 163 MemoryRegion nest_regs_mr; 164 165 /* PCI registers (excluding pass-through) */ 166 #define PHB4_PEC_PCI_STK_REGS_COUNT 0xf 167 uint64_t pci_regs[PHB4_PEC_PCI_STK_REGS_COUNT]; 168 MemoryRegion pci_regs_mr; 169 170 /* PHB pass-through XSCOM */ 171 MemoryRegion phb_regs_mr; 172 173 /* Memory windows from PowerBus to PHB */ 174 MemoryRegion mmbar0; 175 MemoryRegion mmbar1; 176 MemoryRegion phbbar; 177 MemoryRegion intbar; 178 uint64_t mmio0_base; 179 uint64_t mmio0_size; 180 uint64_t mmio1_base; 181 uint64_t mmio1_size; 182 183 /* The owner PEC */ 184 PnvPhb4PecState *pec; 185 186 /* The actual PHB */ 187 PnvPHB4 phb; 188 }; 189 190 struct PnvPhb4PecState { 191 DeviceState parent; 192 193 /* PEC number in chip */ 194 uint32_t index; 195 uint32_t chip_id; 196 197 MemoryRegion *system_memory; 198 199 /* Nest registers, excuding per-stack */ 200 #define PHB4_PEC_NEST_REGS_COUNT 0xf 201 uint64_t nest_regs[PHB4_PEC_NEST_REGS_COUNT]; 202 MemoryRegion nest_regs_mr; 203 204 /* PCI registers, excluding per-stack */ 205 #define PHB4_PEC_PCI_REGS_COUNT 0x2 206 uint64_t pci_regs[PHB4_PEC_PCI_REGS_COUNT]; 207 MemoryRegion pci_regs_mr; 208 209 /* Stacks */ 210 #define PHB4_PEC_MAX_STACKS 3 211 uint32_t num_stacks; 212 PnvPhb4PecStack stacks[PHB4_PEC_MAX_STACKS]; 213 }; 214 215 216 struct PnvPhb4PecClass { 217 DeviceClass parent_class; 218 219 uint32_t (*xscom_nest_base)(PnvPhb4PecState *pec); 220 uint32_t xscom_nest_size; 221 uint32_t (*xscom_pci_base)(PnvPhb4PecState *pec); 222 uint32_t xscom_pci_size; 223 const char *compat; 224 int compat_size; 225 const char *stk_compat; 226 int stk_compat_size; 227 }; 228 229 #endif /* PCI_HOST_PNV_PHB4_H */ 230