1 /* 2 * QEMU PowerPC PowerNV (POWER9) PHB4 model 3 * 4 * Copyright (c) 2018-2020, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #ifndef PCI_HOST_PNV_PHB4_H 11 #define PCI_HOST_PNV_PHB4_H 12 13 #include "hw/pci/pcie_host.h" 14 #include "hw/pci/pcie_port.h" 15 #include "hw/ppc/xive.h" 16 #include "qom/object.h" 17 18 typedef struct PnvPhb4PecState PnvPhb4PecState; 19 typedef struct PnvPhb4PecStack PnvPhb4PecStack; 20 typedef struct PnvPHB4 PnvPHB4; 21 typedef struct PnvChip PnvChip; 22 23 /* 24 * We have one such address space wrapper per possible device under 25 * the PHB since they need to be assigned statically at qemu device 26 * creation time. The relationship to a PE is done later 27 * dynamically. This means we can potentially create a lot of these 28 * guys. Q35 stores them as some kind of radix tree but we never 29 * really need to do fast lookups so instead we simply keep a QLIST of 30 * them for now, we can add the radix if needed later on. 31 * 32 * We do cache the PE number to speed things up a bit though. 33 */ 34 typedef struct PnvPhb4DMASpace { 35 PCIBus *bus; 36 uint8_t devfn; 37 int pe_num; /* Cached PE number */ 38 #define PHB_INVALID_PE (-1) 39 PnvPHB4 *phb; 40 AddressSpace dma_as; 41 IOMMUMemoryRegion dma_mr; 42 MemoryRegion msi32_mr; 43 MemoryRegion msi64_mr; 44 QLIST_ENTRY(PnvPhb4DMASpace) list; 45 } PnvPhb4DMASpace; 46 47 /* 48 * PHB4 PCIe Root port 49 */ 50 #define TYPE_PNV_PHB4_ROOT_BUS "pnv-phb4-root" 51 #define TYPE_PNV_PHB4_ROOT_PORT "pnv-phb4-root-port" 52 53 typedef struct PnvPHB4RootPort { 54 PCIESlot parent_obj; 55 } PnvPHB4RootPort; 56 57 /* 58 * PHB4 PCIe Host Bridge for PowerNV machines (POWER9) 59 */ 60 #define TYPE_PNV_PHB4 "pnv-phb4" 61 OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB4, PNV_PHB4) 62 63 #define PNV_PHB4_MAX_LSIs 8 64 #define PNV_PHB4_MAX_INTs 4096 65 #define PNV_PHB4_MAX_MIST (PNV_PHB4_MAX_INTs >> 2) 66 #define PNV_PHB4_MAX_MMIO_WINDOWS 32 67 #define PNV_PHB4_MIN_MMIO_WINDOWS 16 68 #define PNV_PHB4_NUM_REGS (0x3000 >> 3) 69 #define PNV_PHB4_MAX_PEs 512 70 #define PNV_PHB4_MAX_TVEs (PNV_PHB4_MAX_PEs * 2) 71 #define PNV_PHB4_MAX_PEEVs (PNV_PHB4_MAX_PEs / 64) 72 #define PNV_PHB4_MAX_MBEs (PNV_PHB4_MAX_MMIO_WINDOWS * 2) 73 74 #define PNV_PHB4_VERSION 0x000000a400000002ull 75 #define PNV_PHB4_DEVICE_ID 0x04c1 76 77 #define PCI_MMIO_TOTAL_SIZE (0x1ull << 60) 78 79 struct PnvPHB4 { 80 PCIExpressHost parent_obj; 81 82 uint32_t chip_id; 83 uint32_t phb_id; 84 85 uint64_t version; 86 87 char bus_path[8]; 88 89 /* Main register images */ 90 uint64_t regs[PNV_PHB4_NUM_REGS]; 91 MemoryRegion mr_regs; 92 93 /* Extra SCOM-only register */ 94 uint64_t scom_hv_ind_addr_reg; 95 96 /* 97 * Geometry of the PHB. There are two types, small and big PHBs, a 98 * number of resources (number of PEs, windows etc...) are doubled 99 * for a big PHB 100 */ 101 bool big_phb; 102 103 /* Memory regions for MMIO space */ 104 MemoryRegion mr_mmio[PNV_PHB4_MAX_MMIO_WINDOWS]; 105 106 /* PCI side space */ 107 MemoryRegion pci_mmio; 108 MemoryRegion pci_io; 109 110 /* PCI registers (excluding pass-through) */ 111 #define PHB4_PEC_PCI_STK_REGS_COUNT 0xf 112 uint64_t pci_regs[PHB4_PEC_PCI_STK_REGS_COUNT]; 113 MemoryRegion pci_regs_mr; 114 115 /* Memory windows from PowerBus to PHB */ 116 MemoryRegion phbbar; 117 MemoryRegion intbar; 118 MemoryRegion mmbar0; 119 MemoryRegion mmbar1; 120 uint64_t mmio0_base; 121 uint64_t mmio0_size; 122 uint64_t mmio1_base; 123 uint64_t mmio1_size; 124 125 /* On-chip IODA tables */ 126 uint64_t ioda_LIST[PNV_PHB4_MAX_LSIs]; 127 uint64_t ioda_MIST[PNV_PHB4_MAX_MIST]; 128 uint64_t ioda_TVT[PNV_PHB4_MAX_TVEs]; 129 uint64_t ioda_MBT[PNV_PHB4_MAX_MBEs]; 130 uint64_t ioda_MDT[PNV_PHB4_MAX_PEs]; 131 uint64_t ioda_PEEV[PNV_PHB4_MAX_PEEVs]; 132 133 /* 134 * The internal PESTA/B is 2 bits per PE split into two tables, we 135 * store them in a single array here to avoid wasting space. 136 */ 137 uint8_t ioda_PEST_AB[PNV_PHB4_MAX_PEs]; 138 139 /* P9 Interrupt generation */ 140 XiveSource xsrc; 141 qemu_irq *qirqs; 142 143 PnvPhb4PecStack *stack; 144 145 QLIST_HEAD(, PnvPhb4DMASpace) dma_spaces; 146 }; 147 148 void pnv_phb4_pic_print_info(PnvPHB4 *phb, Monitor *mon); 149 int pnv_phb4_pec_get_phb_id(PnvPhb4PecState *pec, int stack_index); 150 extern const MemoryRegionOps pnv_phb4_xscom_ops; 151 152 /* 153 * PHB4 PEC (PCI Express Controller) 154 */ 155 #define TYPE_PNV_PHB4_PEC "pnv-phb4-pec" 156 OBJECT_DECLARE_TYPE(PnvPhb4PecState, PnvPhb4PecClass, PNV_PHB4_PEC) 157 158 #define TYPE_PNV_PHB4_PEC_STACK "pnv-phb4-pec-stack" 159 OBJECT_DECLARE_SIMPLE_TYPE(PnvPhb4PecStack, PNV_PHB4_PEC_STACK) 160 161 /* Per-stack data */ 162 struct PnvPhb4PecStack { 163 DeviceState parent; 164 165 /* My own stack number */ 166 uint32_t stack_no; 167 168 /* Nest registers */ 169 #define PHB4_PEC_NEST_STK_REGS_COUNT 0x17 170 uint64_t nest_regs[PHB4_PEC_NEST_STK_REGS_COUNT]; 171 MemoryRegion nest_regs_mr; 172 173 /* PHB pass-through XSCOM */ 174 MemoryRegion phb_regs_mr; 175 176 /* The owner PEC */ 177 PnvPhb4PecState *pec; 178 179 /* 180 * PHB4 pointer. pnv_phb4_update_regions() needs to access 181 * the PHB4 via a PnvPhb4PecStack pointer. 182 */ 183 PnvPHB4 *phb; 184 }; 185 186 struct PnvPhb4PecState { 187 DeviceState parent; 188 189 /* PEC number in chip */ 190 uint32_t index; 191 uint32_t chip_id; 192 193 MemoryRegion *system_memory; 194 195 /* Nest registers, excuding per-stack */ 196 #define PHB4_PEC_NEST_REGS_COUNT 0xf 197 uint64_t nest_regs[PHB4_PEC_NEST_REGS_COUNT]; 198 MemoryRegion nest_regs_mr; 199 200 /* PCI registers, excluding per-stack */ 201 #define PHB4_PEC_PCI_REGS_COUNT 0x2 202 uint64_t pci_regs[PHB4_PEC_PCI_REGS_COUNT]; 203 MemoryRegion pci_regs_mr; 204 205 /* Stacks */ 206 #define PHB4_PEC_MAX_STACKS 3 207 uint32_t num_stacks; 208 PnvPhb4PecStack stacks[PHB4_PEC_MAX_STACKS]; 209 210 PnvChip *chip; 211 }; 212 213 214 struct PnvPhb4PecClass { 215 DeviceClass parent_class; 216 217 uint32_t (*xscom_nest_base)(PnvPhb4PecState *pec); 218 uint32_t xscom_nest_size; 219 uint32_t (*xscom_pci_base)(PnvPhb4PecState *pec); 220 uint32_t xscom_pci_size; 221 const char *compat; 222 int compat_size; 223 const char *stk_compat; 224 int stk_compat_size; 225 uint64_t version; 226 const uint32_t *num_stacks; 227 }; 228 229 #endif /* PCI_HOST_PNV_PHB4_H */ 230