1 /* 2 * QEMU PowerPC PowerNV (POWER8) PHB3 model 3 * 4 * Copyright (c) 2014-2020, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #ifndef PCI_HOST_PNV_PHB3_H 11 #define PCI_HOST_PNV_PHB3_H 12 13 #include "hw/pci/pcie_host.h" 14 #include "hw/pci/pcie_port.h" 15 #include "hw/ppc/xics.h" 16 #include "qom/object.h" 17 18 typedef struct PnvPHB3 PnvPHB3; 19 typedef struct PnvChip PnvChip; 20 21 /* 22 * PHB3 XICS Source for MSIs 23 */ 24 #define TYPE_PHB3_MSI "phb3-msi" 25 typedef struct Phb3MsiState Phb3MsiState; 26 DECLARE_INSTANCE_CHECKER(Phb3MsiState, PHB3_MSI, 27 TYPE_PHB3_MSI) 28 29 #define PHB3_MAX_MSI 2048 30 31 struct Phb3MsiState { 32 ICSState ics; 33 qemu_irq *qirqs; 34 35 PnvPHB3 *phb; 36 uint64_t rba[PHB3_MAX_MSI / 64]; 37 uint32_t rba_sum; 38 }; 39 40 void pnv_phb3_msi_update_config(Phb3MsiState *msis, uint32_t base, 41 uint32_t count); 42 void pnv_phb3_msi_send(Phb3MsiState *msis, uint64_t addr, uint16_t data, 43 int32_t dev_pe); 44 void pnv_phb3_msi_ffi(Phb3MsiState *msis, uint64_t val); 45 void pnv_phb3_msi_pic_print_info(Phb3MsiState *msis, Monitor *mon); 46 47 48 /* 49 * We have one such address space wrapper per possible device under 50 * the PHB since they need to be assigned statically at qemu device 51 * creation time. The relationship to a PE is done later dynamically. 52 * This means we can potentially create a lot of these guys. Q35 53 * stores them as some kind of radix tree but we never really need to 54 * do fast lookups so instead we simply keep a QLIST of them for now, 55 * we can add the radix if needed later on. 56 * 57 * We do cache the PE number to speed things up a bit though. 58 */ 59 typedef struct PnvPhb3DMASpace { 60 PCIBus *bus; 61 uint8_t devfn; 62 int pe_num; /* Cached PE number */ 63 #define PHB_INVALID_PE (-1) 64 PnvPHB3 *phb; 65 AddressSpace dma_as; 66 IOMMUMemoryRegion dma_mr; 67 MemoryRegion msi32_mr; 68 MemoryRegion msi64_mr; 69 QLIST_ENTRY(PnvPhb3DMASpace) list; 70 } PnvPhb3DMASpace; 71 72 /* 73 * PHB3 Power Bus Common Queue 74 */ 75 #define TYPE_PNV_PBCQ "pnv-pbcq" 76 OBJECT_DECLARE_SIMPLE_TYPE(PnvPBCQState, PNV_PBCQ) 77 78 struct PnvPBCQState { 79 DeviceState parent; 80 81 uint32_t nest_xbase; 82 uint32_t spci_xbase; 83 uint32_t pci_xbase; 84 #define PBCQ_NEST_REGS_COUNT 0x46 85 #define PBCQ_PCI_REGS_COUNT 0x15 86 #define PBCQ_SPCI_REGS_COUNT 0x5 87 88 uint64_t nest_regs[PBCQ_NEST_REGS_COUNT]; 89 uint64_t spci_regs[PBCQ_SPCI_REGS_COUNT]; 90 uint64_t pci_regs[PBCQ_PCI_REGS_COUNT]; 91 MemoryRegion mmbar0; 92 MemoryRegion mmbar1; 93 MemoryRegion phbbar; 94 uint64_t mmio0_base; 95 uint64_t mmio0_size; 96 uint64_t mmio1_base; 97 uint64_t mmio1_size; 98 PnvPHB3 *phb; 99 100 MemoryRegion xscom_nest_regs; 101 MemoryRegion xscom_pci_regs; 102 MemoryRegion xscom_spci_regs; 103 }; 104 105 /* 106 * PHB3 PCIe Root port 107 */ 108 #define TYPE_PNV_PHB3_ROOT_BUS "pnv-phb3-root" 109 110 #define TYPE_PNV_PHB3_ROOT_PORT "pnv-phb3-root-port" 111 112 typedef struct PnvPHB3RootPort { 113 PCIESlot parent_obj; 114 } PnvPHB3RootPort; 115 116 /* 117 * PHB3 PCIe Host Bridge for PowerNV machines (POWER8) 118 */ 119 #define TYPE_PNV_PHB3 "pnv-phb3" 120 OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB3, PNV_PHB3) 121 122 #define PNV_PHB3_NUM_M64 16 123 #define PNV_PHB3_NUM_REGS (0x1000 >> 3) 124 #define PNV_PHB3_NUM_LSI 8 125 #define PNV_PHB3_NUM_PE 256 126 127 #define PCI_MMIO_TOTAL_SIZE (0x1ull << 60) 128 129 struct PnvPHB3 { 130 PCIExpressHost parent_obj; 131 132 uint32_t chip_id; 133 uint32_t phb_id; 134 char bus_path[8]; 135 136 uint64_t regs[PNV_PHB3_NUM_REGS]; 137 MemoryRegion mr_regs; 138 139 MemoryRegion mr_m32; 140 MemoryRegion mr_m64[PNV_PHB3_NUM_M64]; 141 MemoryRegion pci_mmio; 142 MemoryRegion pci_io; 143 144 uint64_t ioda_LIST[8]; 145 uint64_t ioda_LXIVT[8]; 146 uint64_t ioda_TVT[512]; 147 uint64_t ioda_M64BT[16]; 148 uint64_t ioda_MDT[256]; 149 uint64_t ioda_PEEV[4]; 150 151 uint32_t total_irq; 152 ICSState lsis; 153 qemu_irq *qirqs; 154 Phb3MsiState msis; 155 156 PnvPBCQState pbcq; 157 158 QLIST_HEAD(, PnvPhb3DMASpace) dma_spaces; 159 160 PnvChip *chip; 161 }; 162 163 uint64_t pnv_phb3_reg_read(void *opaque, hwaddr off, unsigned size); 164 void pnv_phb3_reg_write(void *opaque, hwaddr off, uint64_t val, unsigned size); 165 void pnv_phb3_update_regions(PnvPHB3 *phb); 166 void pnv_phb3_remap_irqs(PnvPHB3 *phb); 167 168 #endif /* PCI_HOST_PNV_PHB3_H */ 169