1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * QEMU LoongArch CPU 4 * 5 * Copyright (c) 2021 Loongson Technology Corporation Limited 6 */ 7 8 #ifndef HW_LS7A_H 9 #define HW_LS7A_H 10 11 #include "hw/pci/pci.h" 12 #include "hw/pci/pcie_host.h" 13 #include "hw/pci-host/pam.h" 14 #include "qemu/units.h" 15 #include "qemu/range.h" 16 #include "qom/object.h" 17 18 #define LS7A_PCI_MEM_BASE 0x40000000UL 19 #define LS7A_PCI_MEM_SIZE 0x40000000UL 20 #define LS7A_PCI_IO_OFFSET 0x4000 21 #define LS_PCIECFG_BASE 0x20000000 22 #define LS_PCIECFG_SIZE 0x08000000 23 #define LS7A_PCI_IO_BASE 0x18004000UL 24 #define LS7A_PCI_IO_SIZE 0xC000 25 26 #define LS7A_PCI_MEM_BASE 0x40000000UL 27 #define LS7A_PCI_MEM_SIZE 0x40000000UL 28 29 #define LS7A_PCH_REG_BASE 0x10000000UL 30 #define LS7A_IOAPIC_REG_BASE (LS7A_PCH_REG_BASE) 31 #define LS7A_PCH_MSI_ADDR_LOW 0x2FF00000UL 32 33 /* 34 * According to the kernel pch irq start from 64 offset 35 * 0 ~ 16 irqs used for non-pci device while 16 ~ 64 irqs 36 * used for pci device. 37 */ 38 #define PCH_PIC_IRQ_OFFSET 64 39 #define LS7A_DEVICE_IRQS 16 40 #define LS7A_PCI_IRQS 48 41 #define LS7A_UART_IRQ (PCH_PIC_IRQ_OFFSET + 2) 42 #define LS7A_UART_BASE 0x1fe001e0 43 #define LS7A_RTC_IRQ (PCH_PIC_IRQ_OFFSET + 3) 44 #define LS7A_MISC_REG_BASE (LS7A_PCH_REG_BASE + 0x00080000) 45 #define LS7A_RTC_REG_BASE (LS7A_MISC_REG_BASE + 0x00050100) 46 #define LS7A_RTC_LEN 0x100 47 #define LS7A_SCI_IRQ (PCH_PIC_IRQ_OFFSET + 4) 48 #endif 49