1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * QEMU LoongArch CPU 4 * 5 * Copyright (c) 2021 Loongson Technology Corporation Limited 6 */ 7 8 #ifndef HW_LS7A_H 9 #define HW_LS7A_H 10 11 #include "hw/pci-host/pam.h" 12 #include "qemu/units.h" 13 #include "qemu/range.h" 14 #include "qom/object.h" 15 16 #define VIRT_PCI_MEM_BASE 0x40000000UL 17 #define VIRT_PCI_MEM_SIZE 0x40000000UL 18 #define VIRT_PCI_IO_OFFSET 0x4000 19 #define VIRT_PCI_CFG_BASE 0x20000000 20 #define VIRT_PCI_CFG_SIZE 0x08000000 21 #define VIRT_PCI_IO_BASE 0x18004000UL 22 #define VIRT_PCI_IO_SIZE 0xC000 23 24 #define VIRT_PCH_REG_BASE 0x10000000UL 25 #define VIRT_IOAPIC_REG_BASE (VIRT_PCH_REG_BASE) 26 #define VIRT_PCH_MSI_ADDR_LOW 0x2FF00000UL 27 28 /* 29 * According to the kernel pch irq start from 64 offset 30 * 0 ~ 16 irqs used for non-pci device while 16 ~ 64 irqs 31 * used for pci device. 32 */ 33 #define VIRT_PCH_PIC_IRQ_NUM 32 34 #define PCH_PIC_IRQ_OFFSET 64 35 #define VIRT_DEVICE_IRQS 16 36 #define VIRT_UART_IRQ (PCH_PIC_IRQ_OFFSET + 2) 37 #define VIRT_UART_BASE 0x1fe001e0 38 #define VIRT_UART_SIZE 0X100 39 #define VIRT_RTC_IRQ (PCH_PIC_IRQ_OFFSET + 3) 40 #define VIRT_MISC_REG_BASE (VIRT_PCH_REG_BASE + 0x00080000) 41 #define VIRT_RTC_REG_BASE (VIRT_MISC_REG_BASE + 0x00050100) 42 #define VIRT_RTC_LEN 0x100 43 #define VIRT_SCI_IRQ (PCH_PIC_IRQ_OFFSET + 4) 44 45 #define VIRT_PLATFORM_BUS_BASEADDRESS 0x16000000 46 #define VIRT_PLATFORM_BUS_SIZE 0x2000000 47 #define VIRT_PLATFORM_BUS_NUM_IRQS 2 48 #define VIRT_PLATFORM_BUS_IRQ 69 49 #endif 50