1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * QEMU LoongArch CPU 4 * 5 * Copyright (c) 2021 Loongson Technology Corporation Limited 6 */ 7 8 #ifndef HW_LS7A_H 9 #define HW_LS7A_H 10 11 #include "hw/pci/pci.h" 12 #include "hw/pci/pcie_host.h" 13 #include "hw/pci-host/pam.h" 14 #include "qemu/units.h" 15 #include "qemu/range.h" 16 #include "qom/object.h" 17 18 #define LS7A_PCI_MEM_BASE 0x40000000UL 19 #define LS7A_PCI_MEM_SIZE 0x40000000UL 20 21 #define LS7A_PCH_REG_BASE 0x10000000UL 22 #define LS7A_IOAPIC_REG_BASE (LS7A_PCH_REG_BASE) 23 #define LS7A_PCH_MSI_ADDR_LOW 0x2FF00000UL 24 25 /* 26 * According to the kernel pch irq start from 64 offset 27 * 0 ~ 16 irqs used for non-pci device while 16 ~ 64 irqs 28 * used for pci device. 29 */ 30 #define PCH_PIC_IRQ_OFFSET 64 31 #define LS7A_DEVICE_IRQS 16 32 #define LS7A_PCI_IRQS 48 33 #endif 34