1 /* 2 * HP-PARISC Dino PCI chipset emulation, as in B160L and similar machines 3 * 4 * (C) 2017-2019 by Helge Deller <deller@gmx.de> 5 * 6 * This work is licensed under the GNU GPL license version 2 or later. 7 * 8 * Documentation available at: 9 * https://parisc.wiki.kernel.org/images-parisc/9/91/Dino_ers.pdf 10 * https://parisc.wiki.kernel.org/images-parisc/7/70/Dino_3_1_Errata.pdf 11 */ 12 13 #ifndef DINO_H 14 #define DINO_H 15 16 #include "hw/pci/pci_host.h" 17 18 #define TYPE_DINO_PCI_HOST_BRIDGE "dino-pcihost" 19 OBJECT_DECLARE_SIMPLE_TYPE(DinoState, DINO_PCI_HOST_BRIDGE) 20 21 #define DINO_IAR0 0x004 22 #define DINO_IODC 0x008 23 #define DINO_IRR0 0x00C /* RO */ 24 #define DINO_IAR1 0x010 25 #define DINO_IRR1 0x014 /* RO */ 26 #define DINO_IMR 0x018 27 #define DINO_IPR 0x01C 28 #define DINO_TOC_ADDR 0x020 29 #define DINO_ICR 0x024 30 #define DINO_ILR 0x028 /* RO */ 31 #define DINO_IO_COMMAND 0x030 /* WO */ 32 #define DINO_IO_STATUS 0x034 /* RO */ 33 #define DINO_IO_CONTROL 0x038 34 #define DINO_IO_GSC_ERR_RESP 0x040 /* RO */ 35 #define DINO_IO_ERR_INFO 0x044 /* RO */ 36 #define DINO_IO_PCI_ERR_RESP 0x048 /* RO */ 37 #define DINO_IO_FBB_EN 0x05c 38 #define DINO_IO_ADDR_EN 0x060 39 #define DINO_PCI_CONFIG_ADDR 0x064 40 #define DINO_PCI_CONFIG_DATA 0x068 41 #define DINO_PCI_IO_DATA 0x06c 42 #define DINO_PCI_MEM_DATA 0x070 /* Dino 3.x only */ 43 #define DINO_GSC2X_CONFIG 0x7b4 /* RO */ 44 #define DINO_GMASK 0x800 45 #define DINO_PAMR 0x804 46 #define DINO_PAPR 0x808 47 #define DINO_DAMODE 0x80c 48 #define DINO_PCICMD 0x810 49 #define DINO_PCISTS 0x814 /* R/WC */ 50 #define DINO_MLTIM 0x81c 51 #define DINO_BRDG_FEAT 0x820 52 #define DINO_PCIROR 0x824 53 #define DINO_PCIWOR 0x828 54 #define DINO_TLTIM 0x830 55 56 #define DINO_IRQS 11 /* bits 0-10 are architected */ 57 #define DINO_IRR_MASK 0x5ff /* only 10 bits are implemented */ 58 #define DINO_LOCAL_IRQS (DINO_IRQS + 1) 59 #define DINO_MASK_IRQ(x) (1 << (x)) 60 61 #define DINO_IRQ_PCIINTA 0 62 #define DINO_IRQ_PCIINTB 1 63 #define DINO_IRQ_PCIINTC 2 64 #define DINO_IRQ_PCIINTD 3 65 #define DINO_IRQ_PCIINTE 4 66 #define DINO_IRQ_PCIINTF 5 67 #define DINO_IRQ_GSCEXTINT 6 68 #define DINO_IRQ_BUSERRINT 7 69 #define DINO_IRQ_PS2INT 8 70 #define DINO_IRQ_UNUSED 9 71 #define DINO_IRQ_RS232INT 10 72 73 #define PCIINTA 0x001 74 #define PCIINTB 0x002 75 #define PCIINTC 0x004 76 #define PCIINTD 0x008 77 #define PCIINTE 0x010 78 #define PCIINTF 0x020 79 #define GSCEXTINT 0x040 80 /* #define xxx 0x080 - bit 7 is "default" */ 81 /* #define xxx 0x100 - bit 8 not used */ 82 /* #define xxx 0x200 - bit 9 not used */ 83 #define RS232INT 0x400 84 85 #define DINO_MEM_CHUNK_SIZE (8 * MiB) 86 87 #define DINO800_REGS (1 + (DINO_TLTIM - DINO_GMASK) / 4) 88 static const uint32_t reg800_keep_bits[DINO800_REGS] = { 89 MAKE_64BIT_MASK(0, 1), /* GMASK */ 90 MAKE_64BIT_MASK(0, 7), /* PAMR */ 91 MAKE_64BIT_MASK(0, 7), /* PAPR */ 92 MAKE_64BIT_MASK(0, 8), /* DAMODE */ 93 MAKE_64BIT_MASK(0, 7), /* PCICMD */ 94 MAKE_64BIT_MASK(0, 9), /* PCISTS */ 95 MAKE_64BIT_MASK(0, 32), /* Undefined */ 96 MAKE_64BIT_MASK(0, 8), /* MLTIM */ 97 MAKE_64BIT_MASK(0, 30), /* BRDG_FEAT */ 98 MAKE_64BIT_MASK(0, 24), /* PCIROR */ 99 MAKE_64BIT_MASK(0, 22), /* PCIWOR */ 100 MAKE_64BIT_MASK(0, 32), /* Undocumented */ 101 MAKE_64BIT_MASK(0, 9), /* TLTIM */ 102 }; 103 104 /* offsets to DINO HPA: */ 105 #define DINO_PCI_ADDR 0x064 106 #define DINO_CONFIG_DATA 0x068 107 #define DINO_IO_DATA 0x06c 108 109 struct DinoState { 110 PCIHostState parent_obj; 111 112 /* 113 * PCI_CONFIG_ADDR is parent_obj.config_reg, via pci_host_conf_be_ops, 114 * so that we can map PCI_CONFIG_DATA to pci_host_data_be_ops. 115 */ 116 uint32_t config_reg_dino; /* keep original copy, including 2 lowest bits */ 117 118 uint32_t iar0; 119 uint32_t iar1; 120 uint32_t imr; 121 uint32_t ipr; 122 uint32_t icr; 123 uint32_t ilr; 124 uint32_t io_fbb_en; 125 uint32_t io_addr_en; 126 uint32_t io_control; 127 uint32_t toc_addr; 128 129 uint32_t reg800[DINO800_REGS]; 130 131 MemoryRegion this_mem; 132 MemoryRegion pci_mem; 133 MemoryRegion pci_mem_alias[32]; 134 135 MemoryRegion *memory_as; 136 137 AddressSpace bm_as; 138 MemoryRegion bm; 139 MemoryRegion bm_ram_alias; 140 MemoryRegion bm_pci_alias; 141 MemoryRegion bm_cpu_alias; 142 143 qemu_irq irqs[DINO_IRQS]; 144 }; 145 146 #endif 147