1 /* 2 * Copyright (c) 2017, Impinj, Inc. 3 * 4 * Designware PCIe IP block emulation 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see 18 * <http://www.gnu.org/licenses/>. 19 */ 20 21 #ifndef DESIGNWARE_H 22 #define DESIGNWARE_H 23 24 #include "hw/sysbus.h" 25 #include "hw/pci/pci.h" 26 #include "hw/pci/pci_bus.h" 27 #include "hw/pci/pcie_host.h" 28 #include "hw/pci/pci_bridge.h" 29 #include "qom/object.h" 30 31 #define TYPE_DESIGNWARE_PCIE_HOST "designware-pcie-host" 32 typedef struct DesignwarePCIEHost DesignwarePCIEHost; 33 DECLARE_INSTANCE_CHECKER(DesignwarePCIEHost, DESIGNWARE_PCIE_HOST, 34 TYPE_DESIGNWARE_PCIE_HOST) 35 36 #define TYPE_DESIGNWARE_PCIE_ROOT "designware-pcie-root" 37 typedef struct DesignwarePCIERoot DesignwarePCIERoot; 38 DECLARE_INSTANCE_CHECKER(DesignwarePCIERoot, DESIGNWARE_PCIE_ROOT, 39 TYPE_DESIGNWARE_PCIE_ROOT) 40 41 struct DesignwarePCIERoot; 42 43 typedef struct DesignwarePCIEViewport { 44 DesignwarePCIERoot *root; 45 46 MemoryRegion cfg; 47 MemoryRegion mem; 48 49 uint64_t base; 50 uint64_t target; 51 uint32_t limit; 52 uint32_t cr[2]; 53 54 bool inbound; 55 } DesignwarePCIEViewport; 56 57 typedef struct DesignwarePCIEMSIBank { 58 uint32_t enable; 59 uint32_t mask; 60 uint32_t status; 61 } DesignwarePCIEMSIBank; 62 63 typedef struct DesignwarePCIEMSI { 64 uint64_t base; 65 MemoryRegion iomem; 66 67 #define DESIGNWARE_PCIE_NUM_MSI_BANKS 1 68 69 DesignwarePCIEMSIBank intr[DESIGNWARE_PCIE_NUM_MSI_BANKS]; 70 } DesignwarePCIEMSI; 71 72 struct DesignwarePCIERoot { 73 PCIBridge parent_obj; 74 75 uint32_t atu_viewport; 76 77 #define DESIGNWARE_PCIE_VIEWPORT_OUTBOUND 0 78 #define DESIGNWARE_PCIE_VIEWPORT_INBOUND 1 79 #define DESIGNWARE_PCIE_NUM_VIEWPORTS 4 80 81 DesignwarePCIEViewport viewports[2][DESIGNWARE_PCIE_NUM_VIEWPORTS]; 82 DesignwarePCIEMSI msi; 83 }; 84 85 struct DesignwarePCIEHost { 86 PCIHostState parent_obj; 87 88 DesignwarePCIERoot root; 89 90 struct { 91 AddressSpace address_space; 92 MemoryRegion address_space_root; 93 94 MemoryRegion memory; 95 MemoryRegion io; 96 97 qemu_irq irqs[4]; 98 } pci; 99 100 MemoryRegion mmio; 101 }; 102 103 #endif /* DESIGNWARE_H */ 104