1 /* 2 * ASPEED PCIe Host Controller 3 * 4 * Copyright (C) 2025 ASPEED Technology Inc. 5 * Copyright (c) 2022 Cédric Le Goater <clg@kaod.org> 6 * 7 * Jamin Lin <jamin_lin@aspeedtech.com> 8 * 9 * SPDX-License-Identifier: GPL-2.0-or-later 10 * 11 * This file is based on Cédric Le Goater's patch: 12 * "pci: Add Aspeed host bridge (WIP)" 13 * https://github.com/legoater/qemu/commit/d1b97b0c7844219d847122410dc189854f9d26df 14 * 15 * Modifications have been made to support the Aspeed AST2600 and AST2700 16 * platforms. 17 */ 18 19 #ifndef ASPEED_PCIE_H 20 #define ASPEED_PCIE_H 21 22 #include "hw/sysbus.h" 23 #include "hw/pci/pci_bridge.h" 24 #include "hw/pci/pcie_host.h" 25 #include "qom/object.h" 26 27 typedef struct AspeedPCIECfgTxDesc { 28 uint32_t desc0; 29 uint32_t desc1; 30 uint32_t desc2; 31 uint32_t desc3; 32 uint32_t wdata; 33 uint32_t rdata_reg; 34 } AspeedPCIECfgTxDesc; 35 36 typedef struct AspeedPCIERcRegs { 37 uint32_t int_en_reg; 38 uint32_t int_sts_reg; 39 } AspeedPCIERcRegs; 40 41 typedef struct AspeedPCIERegMap { 42 AspeedPCIERcRegs rc; 43 } AspeedPCIERegMap; 44 45 #define TYPE_ASPEED_PCIE_ROOT "aspeed.pcie-root" 46 OBJECT_DECLARE_SIMPLE_TYPE(AspeedPCIERootState, ASPEED_PCIE_ROOT); 47 48 struct AspeedPCIERootState { 49 PCIBridge parent_obj; 50 }; 51 52 #define TYPE_ASPEED_PCIE_RC "aspeed.pcie-rc" 53 OBJECT_DECLARE_SIMPLE_TYPE(AspeedPCIERcState, ASPEED_PCIE_RC); 54 55 struct AspeedPCIERcState { 56 PCIExpressHost parent_obj; 57 58 MemoryRegion mmio_window; 59 MemoryRegion io_window; 60 MemoryRegion mmio; 61 MemoryRegion io; 62 63 uint32_t bus_nr; 64 char name[16]; 65 qemu_irq irq; 66 67 AspeedPCIERootState root; 68 }; 69 70 /* Bridge between AHB bus and PCIe RC. */ 71 #define TYPE_ASPEED_PCIE_CFG "aspeed.pcie-cfg" 72 OBJECT_DECLARE_TYPE(AspeedPCIECfgState, AspeedPCIECfgClass, ASPEED_PCIE_CFG); 73 74 struct AspeedPCIECfgState { 75 SysBusDevice parent_obj; 76 77 MemoryRegion mmio; 78 uint32_t *regs; 79 uint32_t id; 80 81 AspeedPCIERcState rc; 82 }; 83 84 struct AspeedPCIECfgClass { 85 SysBusDeviceClass parent_class; 86 87 const AspeedPCIERegMap *reg_map; 88 const MemoryRegionOps *reg_ops; 89 90 uint64_t rc_bus_nr; 91 uint64_t nr_regs; 92 }; 93 94 #define TYPE_ASPEED_PCIE_PHY "aspeed.pcie-phy" 95 OBJECT_DECLARE_TYPE(AspeedPCIEPhyState, AspeedPCIEPhyClass, ASPEED_PCIE_PHY); 96 97 struct AspeedPCIEPhyState { 98 SysBusDevice parent_obj; 99 100 MemoryRegion mmio; 101 uint32_t *regs; 102 uint32_t id; 103 }; 104 105 struct AspeedPCIEPhyClass { 106 SysBusDeviceClass parent_class; 107 108 uint64_t nr_regs; 109 }; 110 111 #endif /* ASPEED_PCIE_H */ 112