1 /* 2 * ASPEED PCIe Host Controller 3 * 4 * Copyright (C) 2025 ASPEED Technology Inc. 5 * Copyright (c) 2022 Cédric Le Goater <clg@kaod.org> 6 * 7 * Jamin Lin <jamin_lin@aspeedtech.com> 8 * 9 * SPDX-License-Identifier: GPL-2.0-or-later 10 * 11 * This file is based on Cédric Le Goater's patch: 12 * "pci: Add Aspeed host bridge (WIP)" 13 * https://github.com/legoater/qemu/commit/d1b97b0c7844219d847122410dc189854f9d26df 14 * 15 * Modifications have been made to support the Aspeed AST2600 and AST2700 16 * platforms. 17 */ 18 19 #ifndef ASPEED_PCIE_H 20 #define ASPEED_PCIE_H 21 22 #include "hw/sysbus.h" 23 #include "hw/pci/pci_bridge.h" 24 #include "hw/pci/pcie_host.h" 25 #include "qom/object.h" 26 27 typedef struct AspeedPCIECfgTxDesc { 28 uint32_t desc0; 29 uint32_t desc1; 30 uint32_t desc2; 31 uint32_t desc3; 32 uint32_t wdata; 33 uint32_t rdata_reg; 34 } AspeedPCIECfgTxDesc; 35 36 typedef struct AspeedPCIERcRegs { 37 uint32_t int_en_reg; 38 uint32_t int_sts_reg; 39 uint32_t msi_sts0_reg; 40 uint32_t msi_sts1_reg; 41 } AspeedPCIERcRegs; 42 43 typedef struct AspeedPCIERegMap { 44 AspeedPCIERcRegs rc; 45 } AspeedPCIERegMap; 46 47 #define TYPE_ASPEED_PCIE_ROOT "aspeed.pcie-root" 48 OBJECT_DECLARE_SIMPLE_TYPE(AspeedPCIERootState, ASPEED_PCIE_ROOT); 49 50 struct AspeedPCIERootState { 51 PCIBridge parent_obj; 52 }; 53 54 #define TYPE_ASPEED_PCIE_RC "aspeed.pcie-rc" 55 OBJECT_DECLARE_SIMPLE_TYPE(AspeedPCIERcState, ASPEED_PCIE_RC); 56 57 struct AspeedPCIERcState { 58 PCIExpressHost parent_obj; 59 60 MemoryRegion iommu_root; 61 AddressSpace iommu_as; 62 MemoryRegion dram_alias; 63 MemoryRegion *dram_mr; 64 MemoryRegion mmio_window; 65 MemoryRegion msi_window; 66 MemoryRegion io_window; 67 MemoryRegion mmio; 68 MemoryRegion io; 69 70 uint64_t dram_base; 71 uint32_t msi_addr; 72 uint32_t bus_nr; 73 char name[16]; 74 qemu_irq irq; 75 76 AspeedPCIERootState root; 77 }; 78 79 /* Bridge between AHB bus and PCIe RC. */ 80 #define TYPE_ASPEED_PCIE_CFG "aspeed.pcie-cfg" 81 OBJECT_DECLARE_TYPE(AspeedPCIECfgState, AspeedPCIECfgClass, ASPEED_PCIE_CFG); 82 83 struct AspeedPCIECfgState { 84 SysBusDevice parent_obj; 85 86 MemoryRegion mmio; 87 uint32_t *regs; 88 uint32_t id; 89 90 AspeedPCIERcState rc; 91 }; 92 93 struct AspeedPCIECfgClass { 94 SysBusDeviceClass parent_class; 95 96 const AspeedPCIERegMap *reg_map; 97 const MemoryRegionOps *reg_ops; 98 99 uint32_t rc_msi_addr; 100 uint64_t rc_bus_nr; 101 uint64_t nr_regs; 102 }; 103 104 #define TYPE_ASPEED_PCIE_PHY "aspeed.pcie-phy" 105 OBJECT_DECLARE_TYPE(AspeedPCIEPhyState, AspeedPCIEPhyClass, ASPEED_PCIE_PHY); 106 107 struct AspeedPCIEPhyState { 108 SysBusDevice parent_obj; 109 110 MemoryRegion mmio; 111 uint32_t *regs; 112 uint32_t id; 113 }; 114 115 struct AspeedPCIEPhyClass { 116 SysBusDeviceClass parent_class; 117 118 uint64_t nr_regs; 119 }; 120 121 #endif /* ASPEED_PCIE_H */ 122