1 /* 2 * i.MX FEC/ENET Ethernet Controller emulation. 3 * 4 * Copyright (c) 2013 Jean-Christophe Dubois. <jcd@tribudubois.net> 5 * 6 * Based on Coldfire Fast Ethernet Controller emulation. 7 * 8 * Copyright (c) 2007 CodeSourcery. 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, but WITHOUT 16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 18 * for more details. 19 * 20 * You should have received a copy of the GNU General Public License along 21 * with this program; if not, see <http://www.gnu.org/licenses/>. 22 */ 23 24 #ifndef IMX_FEC_H 25 #define IMX_FEC_H 26 27 #define TYPE_IMX_FEC "imx.fec" 28 #define IMX_FEC(obj) OBJECT_CHECK(IMXFECState, (obj), TYPE_IMX_FEC) 29 30 #define TYPE_IMX_ENET "imx.enet" 31 32 #include "hw/sysbus.h" 33 #include "net/net.h" 34 35 #define ENET_EIR 1 36 #define ENET_EIMR 2 37 #define ENET_RDAR 4 38 #define ENET_TDAR 5 39 #define ENET_ECR 9 40 #define ENET_MMFR 16 41 #define ENET_MSCR 17 42 #define ENET_MIBC 25 43 #define ENET_RCR 33 44 #define ENET_TCR 49 45 #define ENET_PALR 57 46 #define ENET_PAUR 58 47 #define ENET_OPD 59 48 #define ENET_IAUR 70 49 #define ENET_IALR 71 50 #define ENET_GAUR 72 51 #define ENET_GALR 73 52 #define ENET_TFWR 81 53 #define ENET_FRBR 83 54 #define ENET_FRSR 84 55 #define ENET_TDSR1 89 56 #define ENET_TDSR2 92 57 #define ENET_RDSR 96 58 #define ENET_TDSR 97 59 #define ENET_MRBR 98 60 #define ENET_RSFL 100 61 #define ENET_RSEM 101 62 #define ENET_RAEM 102 63 #define ENET_RAFL 103 64 #define ENET_TSEM 104 65 #define ENET_TAEM 105 66 #define ENET_TAFL 106 67 #define ENET_TIPG 107 68 #define ENET_FTRL 108 69 #define ENET_TACC 112 70 #define ENET_RACC 113 71 #define ENET_TDAR1 121 72 #define ENET_TDAR2 123 73 #define ENET_MIIGSK_CFGR 192 74 #define ENET_MIIGSK_ENR 194 75 #define ENET_ATCR 256 76 #define ENET_ATVR 257 77 #define ENET_ATOFF 258 78 #define ENET_ATPER 259 79 #define ENET_ATCOR 260 80 #define ENET_ATINC 261 81 #define ENET_ATSTMP 262 82 #define ENET_TGSR 385 83 #define ENET_TCSR0 386 84 #define ENET_TCCR0 387 85 #define ENET_TCSR1 388 86 #define ENET_TCCR1 389 87 #define ENET_TCSR2 390 88 #define ENET_TCCR2 391 89 #define ENET_TCSR3 392 90 #define ENET_TCCR3 393 91 #define ENET_MAX 400 92 93 94 /* EIR and EIMR */ 95 #define ENET_INT_HB (1 << 31) 96 #define ENET_INT_BABR (1 << 30) 97 #define ENET_INT_BABT (1 << 29) 98 #define ENET_INT_GRA (1 << 28) 99 #define ENET_INT_TXF (1 << 27) 100 #define ENET_INT_TXB (1 << 26) 101 #define ENET_INT_RXF (1 << 25) 102 #define ENET_INT_RXB (1 << 24) 103 #define ENET_INT_MII (1 << 23) 104 #define ENET_INT_EBERR (1 << 22) 105 #define ENET_INT_LC (1 << 21) 106 #define ENET_INT_RL (1 << 20) 107 #define ENET_INT_UN (1 << 19) 108 #define ENET_INT_PLR (1 << 18) 109 #define ENET_INT_WAKEUP (1 << 17) 110 #define ENET_INT_TS_AVAIL (1 << 16) 111 #define ENET_INT_TS_TIMER (1 << 15) 112 #define ENET_INT_TXF2 (1 << 7) 113 #define ENET_INT_TXB2 (1 << 6) 114 #define ENET_INT_TXF1 (1 << 3) 115 #define ENET_INT_TXB1 (1 << 2) 116 117 #define ENET_INT_MAC (ENET_INT_HB | ENET_INT_BABR | ENET_INT_BABT | \ 118 ENET_INT_GRA | ENET_INT_TXF | ENET_INT_TXB | \ 119 ENET_INT_RXF | ENET_INT_RXB | ENET_INT_MII | \ 120 ENET_INT_EBERR | ENET_INT_LC | ENET_INT_RL | \ 121 ENET_INT_UN | ENET_INT_PLR | ENET_INT_WAKEUP | \ 122 ENET_INT_TS_AVAIL | ENET_INT_TXF1 | \ 123 ENET_INT_TXB1 | ENET_INT_TXF2 | ENET_INT_TXB2) 124 125 /* RDAR */ 126 #define ENET_RDAR_RDAR (1 << 24) 127 128 /* TDAR */ 129 #define ENET_TDAR_TDAR (1 << 24) 130 131 /* ECR */ 132 #define ENET_ECR_RESET (1 << 0) 133 #define ENET_ECR_ETHEREN (1 << 1) 134 #define ENET_ECR_MAGICEN (1 << 2) 135 #define ENET_ECR_SLEEP (1 << 3) 136 #define ENET_ECR_EN1588 (1 << 4) 137 #define ENET_ECR_SPEED (1 << 5) 138 #define ENET_ECR_DBGEN (1 << 6) 139 #define ENET_ECR_STOPEN (1 << 7) 140 #define ENET_ECR_DSBWP (1 << 8) 141 142 /* MIBC */ 143 #define ENET_MIBC_MIB_DIS (1 << 31) 144 #define ENET_MIBC_MIB_IDLE (1 << 30) 145 #define ENET_MIBC_MIB_CLEAR (1 << 29) 146 147 /* RCR */ 148 #define ENET_RCR_LOOP (1 << 0) 149 #define ENET_RCR_DRT (1 << 1) 150 #define ENET_RCR_MII_MODE (1 << 2) 151 #define ENET_RCR_PROM (1 << 3) 152 #define ENET_RCR_BC_REJ (1 << 4) 153 #define ENET_RCR_FCE (1 << 5) 154 #define ENET_RCR_RGMII_EN (1 << 6) 155 #define ENET_RCR_RMII_MODE (1 << 8) 156 #define ENET_RCR_RMII_10T (1 << 9) 157 #define ENET_RCR_PADEN (1 << 12) 158 #define ENET_RCR_PAUFWD (1 << 13) 159 #define ENET_RCR_CRCFWD (1 << 14) 160 #define ENET_RCR_CFEN (1 << 15) 161 #define ENET_RCR_MAX_FL_SHIFT (16) 162 #define ENET_RCR_MAX_FL_LENGTH (14) 163 #define ENET_RCR_NLC (1 << 30) 164 #define ENET_RCR_GRS (1 << 31) 165 166 #define ENET_MAX_FRAME_SIZE (1 << ENET_RCR_MAX_FL_LENGTH) 167 168 /* TCR */ 169 #define ENET_TCR_GTS (1 << 0) 170 #define ENET_TCR_FDEN (1 << 2) 171 #define ENET_TCR_TFC_PAUSE (1 << 3) 172 #define ENET_TCR_RFC_PAUSE (1 << 4) 173 #define ENET_TCR_ADDSEL_SHIFT (5) 174 #define ENET_TCR_ADDSEL_LENGTH (3) 175 #define ENET_TCR_CRCFWD (1 << 9) 176 177 /* RDSR */ 178 #define ENET_TWFR_TFWR_SHIFT (0) 179 #define ENET_TWFR_TFWR_LENGTH (6) 180 #define ENET_TWFR_STRFWD (1 << 8) 181 182 #define ENET_RACC_SHIFT16 BIT(7) 183 184 /* Buffer Descriptor. */ 185 typedef struct { 186 uint16_t length; 187 uint16_t flags; 188 uint32_t data; 189 } IMXFECBufDesc; 190 191 #define ENET_BD_R (1 << 15) 192 #define ENET_BD_E (1 << 15) 193 #define ENET_BD_O1 (1 << 14) 194 #define ENET_BD_W (1 << 13) 195 #define ENET_BD_O2 (1 << 12) 196 #define ENET_BD_L (1 << 11) 197 #define ENET_BD_TC (1 << 10) 198 #define ENET_BD_ABC (1 << 9) 199 #define ENET_BD_M (1 << 8) 200 #define ENET_BD_BC (1 << 7) 201 #define ENET_BD_MC (1 << 6) 202 #define ENET_BD_LG (1 << 5) 203 #define ENET_BD_NO (1 << 4) 204 #define ENET_BD_CR (1 << 2) 205 #define ENET_BD_OV (1 << 1) 206 #define ENET_BD_TR (1 << 0) 207 208 typedef struct { 209 uint16_t length; 210 uint16_t flags; 211 uint32_t data; 212 uint16_t status; 213 uint16_t option; 214 uint16_t checksum; 215 uint16_t head_proto; 216 uint32_t last_buffer; 217 uint32_t timestamp; 218 uint32_t reserved[2]; 219 } IMXENETBufDesc; 220 221 #define ENET_BD_ME (1 << 15) 222 #define ENET_BD_TX_INT (1 << 14) 223 #define ENET_BD_TS (1 << 13) 224 #define ENET_BD_PINS (1 << 12) 225 #define ENET_BD_IINS (1 << 11) 226 #define ENET_BD_PE (1 << 10) 227 #define ENET_BD_CE (1 << 9) 228 #define ENET_BD_UC (1 << 8) 229 #define ENET_BD_RX_INT (1 << 7) 230 231 #define ENET_BD_TXE (1 << 15) 232 #define ENET_BD_UE (1 << 13) 233 #define ENET_BD_EE (1 << 12) 234 #define ENET_BD_FE (1 << 11) 235 #define ENET_BD_LCE (1 << 10) 236 #define ENET_BD_OE (1 << 9) 237 #define ENET_BD_TSE (1 << 8) 238 #define ENET_BD_ICE (1 << 5) 239 #define ENET_BD_PCR (1 << 4) 240 #define ENET_BD_VLAN (1 << 2) 241 #define ENET_BD_IPV6 (1 << 1) 242 #define ENET_BD_FRAG (1 << 0) 243 244 #define ENET_BD_BDU (1 << 31) 245 246 #define ENET_TX_RING_NUM 3 247 248 #define FSL_IMX25_FEC_SIZE 0x4000 249 250 typedef struct IMXFECState { 251 /*< private >*/ 252 SysBusDevice parent_obj; 253 254 /*< public >*/ 255 NICState *nic; 256 NICConf conf; 257 qemu_irq irq[2]; 258 MemoryRegion iomem; 259 260 uint32_t regs[ENET_MAX]; 261 uint32_t rx_descriptor; 262 263 uint32_t tx_descriptor[ENET_TX_RING_NUM]; 264 uint32_t tx_ring_num; 265 266 uint32_t phy_status; 267 uint32_t phy_control; 268 uint32_t phy_advertise; 269 uint32_t phy_int; 270 uint32_t phy_int_mask; 271 272 bool is_fec; 273 274 /* Buffer used to assemble a Tx frame */ 275 uint8_t frame[ENET_MAX_FRAME_SIZE]; 276 } IMXFECState; 277 278 #endif 279