1 /* 2 * Faraday FTGMAC100 Gigabit Ethernet 3 * 4 * Copyright (C) 2016-2017, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #ifndef FTGMAC100_H 11 #define FTGMAC100_H 12 #include "qom/object.h" 13 14 #define TYPE_FTGMAC100 "ftgmac100" 15 typedef struct FTGMAC100State FTGMAC100State; 16 DECLARE_INSTANCE_CHECKER(FTGMAC100State, FTGMAC100, 17 TYPE_FTGMAC100) 18 19 #include "hw/sysbus.h" 20 #include "net/net.h" 21 22 /* 23 * Max frame size for the receiving buffer 24 */ 25 #define FTGMAC100_MAX_FRAME_SIZE 9220 26 27 struct FTGMAC100State { 28 /*< private >*/ 29 SysBusDevice parent_obj; 30 31 /*< public >*/ 32 NICState *nic; 33 NICConf conf; 34 qemu_irq irq; 35 MemoryRegion iomem; 36 37 uint8_t frame[FTGMAC100_MAX_FRAME_SIZE]; 38 39 uint32_t irq_state; 40 uint32_t isr; 41 uint32_t ier; 42 uint32_t rx_enabled; 43 uint32_t rx_ring; 44 uint32_t rx_descriptor; 45 uint32_t tx_ring; 46 uint32_t tx_descriptor; 47 uint32_t math[2]; 48 uint32_t rbsr; 49 uint32_t itc; 50 uint32_t aptcr; 51 uint32_t dblac; 52 uint32_t revr; 53 uint32_t fear1; 54 uint32_t tpafcr; 55 uint32_t maccr; 56 uint32_t phycr; 57 uint32_t phydata; 58 uint32_t fcr; 59 60 61 uint32_t phy_status; 62 uint32_t phy_control; 63 uint32_t phy_advertise; 64 uint32_t phy_int; 65 uint32_t phy_int_mask; 66 67 bool aspeed; 68 uint32_t txdes0_edotr; 69 uint32_t rxdes0_edorr; 70 }; 71 72 #define TYPE_ASPEED_MII "aspeed-mmi" 73 typedef struct AspeedMiiState AspeedMiiState; 74 DECLARE_INSTANCE_CHECKER(AspeedMiiState, ASPEED_MII, 75 TYPE_ASPEED_MII) 76 77 /* 78 * AST2600 MII controller 79 */ 80 struct AspeedMiiState { 81 /*< private >*/ 82 SysBusDevice parent_obj; 83 84 FTGMAC100State *nic; 85 86 MemoryRegion iomem; 87 uint32_t phycr; 88 uint32_t phydata; 89 }; 90 91 #endif 92