1 /* 2 * QEMU Cadence GEM emulation 3 * 4 * Copyright (c) 2011 Xilinx, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #ifndef CADENCE_GEM_H 26 27 #define TYPE_CADENCE_GEM "cadence_gem" 28 #define CADENCE_GEM(obj) OBJECT_CHECK(CadenceGEMState, (obj), TYPE_CADENCE_GEM) 29 30 #include "net/net.h" 31 #include "hw/sysbus.h" 32 33 #define CADENCE_GEM_MAXREG (0x00000640/4) /* Last valid GEM address */ 34 35 typedef struct CadenceGEMState { 36 /*< private >*/ 37 SysBusDevice parent_obj; 38 39 /*< public >*/ 40 MemoryRegion iomem; 41 NICState *nic; 42 NICConf conf; 43 qemu_irq irq; 44 45 /* GEM registers backing store */ 46 uint32_t regs[CADENCE_GEM_MAXREG]; 47 /* Mask of register bits which are write only */ 48 uint32_t regs_wo[CADENCE_GEM_MAXREG]; 49 /* Mask of register bits which are read only */ 50 uint32_t regs_ro[CADENCE_GEM_MAXREG]; 51 /* Mask of register bits which are clear on read */ 52 uint32_t regs_rtc[CADENCE_GEM_MAXREG]; 53 /* Mask of register bits which are write 1 to clear */ 54 uint32_t regs_w1c[CADENCE_GEM_MAXREG]; 55 56 /* PHY registers backing store */ 57 uint16_t phy_regs[32]; 58 59 uint8_t phy_loop; /* Are we in phy loopback? */ 60 61 /* The current DMA descriptor pointers */ 62 uint32_t rx_desc_addr; 63 uint32_t tx_desc_addr; 64 65 uint8_t can_rx_state; /* Debug only */ 66 67 unsigned rx_desc[2]; 68 69 bool sar_active[4]; 70 } CadenceGEMState; 71 72 #define CADENCE_GEM_H 73 #endif 74