1 /* 2 * Emulation of Allwinner EMAC Fast Ethernet controller and 3 * Realtek RTL8201CP PHY 4 * 5 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> 6 * 7 * Allwinner EMAC register definitions from Linux kernel are: 8 * Copyright 2012 Stefan Roese <sr@denx.de> 9 * Copyright 2013 Maxime Ripard <maxime.ripard@free-electrons.com> 10 * Copyright 1997 Sten Wang 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License 14 * version 2 as published by the Free Software Foundation. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 */ 22 #ifndef AW_EMAC_H 23 #define AW_EMAC_H 24 25 #include "net/net.h" 26 #include "qemu/fifo8.h" 27 #include "hw/net/mii.h" 28 29 #define TYPE_AW_EMAC "allwinner-emac" 30 #define AW_EMAC(obj) OBJECT_CHECK(AwEmacState, (obj), TYPE_AW_EMAC) 31 32 /* 33 * Allwinner EMAC register list 34 */ 35 #define EMAC_CTL_REG 0x00 36 37 #define EMAC_TX_MODE_REG 0x04 38 #define EMAC_TX_FLOW_REG 0x08 39 #define EMAC_TX_CTL0_REG 0x0C 40 #define EMAC_TX_CTL1_REG 0x10 41 #define EMAC_TX_INS_REG 0x14 42 #define EMAC_TX_PL0_REG 0x18 43 #define EMAC_TX_PL1_REG 0x1C 44 #define EMAC_TX_STA_REG 0x20 45 #define EMAC_TX_IO_DATA_REG 0x24 46 #define EMAC_TX_IO_DATA1_REG 0x28 47 #define EMAC_TX_TSVL0_REG 0x2C 48 #define EMAC_TX_TSVH0_REG 0x30 49 #define EMAC_TX_TSVL1_REG 0x34 50 #define EMAC_TX_TSVH1_REG 0x38 51 52 #define EMAC_RX_CTL_REG 0x3C 53 #define EMAC_RX_HASH0_REG 0x40 54 #define EMAC_RX_HASH1_REG 0x44 55 #define EMAC_RX_STA_REG 0x48 56 #define EMAC_RX_IO_DATA_REG 0x4C 57 #define EMAC_RX_FBC_REG 0x50 58 59 #define EMAC_INT_CTL_REG 0x54 60 #define EMAC_INT_STA_REG 0x58 61 62 #define EMAC_MAC_CTL0_REG 0x5C 63 #define EMAC_MAC_CTL1_REG 0x60 64 #define EMAC_MAC_IPGT_REG 0x64 65 #define EMAC_MAC_IPGR_REG 0x68 66 #define EMAC_MAC_CLRT_REG 0x6C 67 #define EMAC_MAC_MAXF_REG 0x70 68 #define EMAC_MAC_SUPP_REG 0x74 69 #define EMAC_MAC_TEST_REG 0x78 70 #define EMAC_MAC_MCFG_REG 0x7C 71 #define EMAC_MAC_MCMD_REG 0x80 72 #define EMAC_MAC_MADR_REG 0x84 73 #define EMAC_MAC_MWTD_REG 0x88 74 #define EMAC_MAC_MRDD_REG 0x8C 75 #define EMAC_MAC_MIND_REG 0x90 76 #define EMAC_MAC_SSRR_REG 0x94 77 #define EMAC_MAC_A0_REG 0x98 78 #define EMAC_MAC_A1_REG 0x9C 79 #define EMAC_MAC_A2_REG 0xA0 80 81 #define EMAC_SAFX_L_REG0 0xA4 82 #define EMAC_SAFX_H_REG0 0xA8 83 #define EMAC_SAFX_L_REG1 0xAC 84 #define EMAC_SAFX_H_REG1 0xB0 85 #define EMAC_SAFX_L_REG2 0xB4 86 #define EMAC_SAFX_H_REG2 0xB8 87 #define EMAC_SAFX_L_REG3 0xBC 88 #define EMAC_SAFX_H_REG3 0xC0 89 90 /* CTL register fields */ 91 #define EMAC_CTL_RESET (1 << 0) 92 #define EMAC_CTL_TX_EN (1 << 1) 93 #define EMAC_CTL_RX_EN (1 << 2) 94 95 /* TX MODE register fields */ 96 #define EMAC_TX_MODE_ABORTED_FRAME_EN (1 << 0) 97 #define EMAC_TX_MODE_DMA_EN (1 << 1) 98 99 /* RX CTL register fields */ 100 #define EMAC_RX_CTL_AUTO_DRQ_EN (1 << 1) 101 #define EMAC_RX_CTL_DMA_EN (1 << 2) 102 #define EMAC_RX_CTL_PASS_ALL_EN (1 << 4) 103 #define EMAC_RX_CTL_PASS_CTL_EN (1 << 5) 104 #define EMAC_RX_CTL_PASS_CRC_ERR_EN (1 << 6) 105 #define EMAC_RX_CTL_PASS_LEN_ERR_EN (1 << 7) 106 #define EMAC_RX_CTL_PASS_LEN_OOR_EN (1 << 8) 107 #define EMAC_RX_CTL_ACCEPT_UNICAST_EN (1 << 16) 108 #define EMAC_RX_CTL_DA_FILTER_EN (1 << 17) 109 #define EMAC_RX_CTL_ACCEPT_MULTICAST_EN (1 << 20) 110 #define EMAC_RX_CTL_HASH_FILTER_EN (1 << 21) 111 #define EMAC_RX_CTL_ACCEPT_BROADCAST_EN (1 << 22) 112 #define EMAC_RX_CTL_SA_FILTER_EN (1 << 24) 113 #define EMAC_RX_CTL_SA_FILTER_INVERT_EN (1 << 25) 114 115 /* RX IO DATA register fields */ 116 #define EMAC_RX_HEADER(len, status) (((len) & 0xffff) | ((status) << 16)) 117 #define EMAC_RX_IO_DATA_STATUS_CRC_ERR (1 << 4) 118 #define EMAC_RX_IO_DATA_STATUS_LEN_ERR (3 << 5) 119 #define EMAC_RX_IO_DATA_STATUS_OK (1 << 7) 120 #define EMAC_UNDOCUMENTED_MAGIC 0x0143414d /* header for RX frames */ 121 122 /* INT CTL and INT STA registers fields */ 123 #define EMAC_INT_TX_CHAN(x) (1 << (x)) 124 #define EMAC_INT_RX (1 << 8) 125 126 /* Due to lack of specifications, size of fifos is chosen arbitrarily */ 127 #define TX_FIFO_SIZE (4 * 1024) 128 #define RX_FIFO_SIZE (32 * 1024) 129 130 #define NUM_TX_FIFOS 2 131 #define RX_HDR_SIZE 8 132 #define CRC_SIZE 4 133 134 #define PHY_REG_SHIFT 0 135 #define PHY_ADDR_SHIFT 8 136 137 typedef struct RTL8201CPState { 138 uint16_t bmcr; 139 uint16_t bmsr; 140 uint16_t anar; 141 uint16_t anlpar; 142 } RTL8201CPState; 143 144 typedef struct AwEmacState { 145 /*< private >*/ 146 SysBusDevice parent_obj; 147 /*< public >*/ 148 149 MemoryRegion iomem; 150 qemu_irq irq; 151 NICState *nic; 152 NICConf conf; 153 RTL8201CPState mii; 154 uint8_t phy_addr; 155 156 uint32_t ctl; 157 uint32_t tx_mode; 158 uint32_t rx_ctl; 159 uint32_t int_ctl; 160 uint32_t int_sta; 161 uint32_t phy_target; 162 163 Fifo8 rx_fifo; 164 uint32_t rx_num_packets; 165 uint32_t rx_packet_size; 166 uint32_t rx_packet_pos; 167 168 Fifo8 tx_fifo[NUM_TX_FIFOS]; 169 uint32_t tx_length[NUM_TX_FIFOS]; 170 uint32_t tx_channel; 171 } AwEmacState; 172 173 #endif 174