1 /* 2 * Emulation of Allwinner EMAC Fast Ethernet controller and 3 * Realtek RTL8201CP PHY 4 * 5 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> 6 * 7 * Allwinner EMAC register definitions from Linux kernel are: 8 * Copyright 2012 Stefan Roese <sr@denx.de> 9 * Copyright 2013 Maxime Ripard <maxime.ripard@free-electrons.com> 10 * Copyright 1997 Sten Wang 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License 14 * version 2 as published by the Free Software Foundation. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 */ 22 #ifndef AW_EMAC_H 23 #define AW_EMAC_H 24 25 #include "net/net.h" 26 #include "qemu/fifo8.h" 27 28 #define TYPE_AW_EMAC "allwinner-emac" 29 #define AW_EMAC(obj) OBJECT_CHECK(AwEmacState, (obj), TYPE_AW_EMAC) 30 31 /* 32 * Allwinner EMAC register list 33 */ 34 #define EMAC_CTL_REG 0x00 35 36 #define EMAC_TX_MODE_REG 0x04 37 #define EMAC_TX_FLOW_REG 0x08 38 #define EMAC_TX_CTL0_REG 0x0C 39 #define EMAC_TX_CTL1_REG 0x10 40 #define EMAC_TX_INS_REG 0x14 41 #define EMAC_TX_PL0_REG 0x18 42 #define EMAC_TX_PL1_REG 0x1C 43 #define EMAC_TX_STA_REG 0x20 44 #define EMAC_TX_IO_DATA_REG 0x24 45 #define EMAC_TX_IO_DATA1_REG 0x28 46 #define EMAC_TX_TSVL0_REG 0x2C 47 #define EMAC_TX_TSVH0_REG 0x30 48 #define EMAC_TX_TSVL1_REG 0x34 49 #define EMAC_TX_TSVH1_REG 0x38 50 51 #define EMAC_RX_CTL_REG 0x3C 52 #define EMAC_RX_HASH0_REG 0x40 53 #define EMAC_RX_HASH1_REG 0x44 54 #define EMAC_RX_STA_REG 0x48 55 #define EMAC_RX_IO_DATA_REG 0x4C 56 #define EMAC_RX_FBC_REG 0x50 57 58 #define EMAC_INT_CTL_REG 0x54 59 #define EMAC_INT_STA_REG 0x58 60 61 #define EMAC_MAC_CTL0_REG 0x5C 62 #define EMAC_MAC_CTL1_REG 0x60 63 #define EMAC_MAC_IPGT_REG 0x64 64 #define EMAC_MAC_IPGR_REG 0x68 65 #define EMAC_MAC_CLRT_REG 0x6C 66 #define EMAC_MAC_MAXF_REG 0x70 67 #define EMAC_MAC_SUPP_REG 0x74 68 #define EMAC_MAC_TEST_REG 0x78 69 #define EMAC_MAC_MCFG_REG 0x7C 70 #define EMAC_MAC_MCMD_REG 0x80 71 #define EMAC_MAC_MADR_REG 0x84 72 #define EMAC_MAC_MWTD_REG 0x88 73 #define EMAC_MAC_MRDD_REG 0x8C 74 #define EMAC_MAC_MIND_REG 0x90 75 #define EMAC_MAC_SSRR_REG 0x94 76 #define EMAC_MAC_A0_REG 0x98 77 #define EMAC_MAC_A1_REG 0x9C 78 #define EMAC_MAC_A2_REG 0xA0 79 80 #define EMAC_SAFX_L_REG0 0xA4 81 #define EMAC_SAFX_H_REG0 0xA8 82 #define EMAC_SAFX_L_REG1 0xAC 83 #define EMAC_SAFX_H_REG1 0xB0 84 #define EMAC_SAFX_L_REG2 0xB4 85 #define EMAC_SAFX_H_REG2 0xB8 86 #define EMAC_SAFX_L_REG3 0xBC 87 #define EMAC_SAFX_H_REG3 0xC0 88 89 /* CTL register fields */ 90 #define EMAC_CTL_RESET (1 << 0) 91 #define EMAC_CTL_TX_EN (1 << 1) 92 #define EMAC_CTL_RX_EN (1 << 2) 93 94 /* TX MODE register fields */ 95 #define EMAC_TX_MODE_ABORTED_FRAME_EN (1 << 0) 96 #define EMAC_TX_MODE_DMA_EN (1 << 1) 97 98 /* RX CTL register fields */ 99 #define EMAC_RX_CTL_AUTO_DRQ_EN (1 << 1) 100 #define EMAC_RX_CTL_DMA_EN (1 << 2) 101 #define EMAC_RX_CTL_PASS_ALL_EN (1 << 4) 102 #define EMAC_RX_CTL_PASS_CTL_EN (1 << 5) 103 #define EMAC_RX_CTL_PASS_CRC_ERR_EN (1 << 6) 104 #define EMAC_RX_CTL_PASS_LEN_ERR_EN (1 << 7) 105 #define EMAC_RX_CTL_PASS_LEN_OOR_EN (1 << 8) 106 #define EMAC_RX_CTL_ACCEPT_UNICAST_EN (1 << 16) 107 #define EMAC_RX_CTL_DA_FILTER_EN (1 << 17) 108 #define EMAC_RX_CTL_ACCEPT_MULTICAST_EN (1 << 20) 109 #define EMAC_RX_CTL_HASH_FILTER_EN (1 << 21) 110 #define EMAC_RX_CTL_ACCEPT_BROADCAST_EN (1 << 22) 111 #define EMAC_RX_CTL_SA_FILTER_EN (1 << 24) 112 #define EMAC_RX_CTL_SA_FILTER_INVERT_EN (1 << 25) 113 114 /* RX IO DATA register fields */ 115 #define EMAC_RX_HEADER(len, status) (((len) & 0xffff) | ((status) << 16)) 116 #define EMAC_RX_IO_DATA_STATUS_CRC_ERR (1 << 4) 117 #define EMAC_RX_IO_DATA_STATUS_LEN_ERR (3 << 5) 118 #define EMAC_RX_IO_DATA_STATUS_OK (1 << 7) 119 #define EMAC_UNDOCUMENTED_MAGIC 0x0143414d /* header for RX frames */ 120 121 /* PHY registers */ 122 #define MII_BMCR 0 123 #define MII_BMSR 1 124 #define MII_PHYID1 2 125 #define MII_PHYID2 3 126 #define MII_ANAR 4 127 #define MII_ANLPAR 5 128 #define MII_ANER 6 129 #define MII_NSR 16 130 #define MII_LBREMR 17 131 #define MII_REC 18 132 #define MII_SNRDR 19 133 #define MII_TEST 25 134 135 /* PHY registers fields */ 136 #define MII_BMCR_RESET (1 << 15) 137 #define MII_BMCR_LOOPBACK (1 << 14) 138 #define MII_BMCR_SPEED (1 << 13) 139 #define MII_BMCR_AUTOEN (1 << 12) 140 #define MII_BMCR_FD (1 << 8) 141 142 #define MII_BMSR_100TX_FD (1 << 14) 143 #define MII_BMSR_100TX_HD (1 << 13) 144 #define MII_BMSR_10T_FD (1 << 12) 145 #define MII_BMSR_10T_HD (1 << 11) 146 #define MII_BMSR_MFPS (1 << 6) 147 #define MII_BMSR_AN_COMP (1 << 5) 148 #define MII_BMSR_AUTONEG (1 << 3) 149 #define MII_BMSR_LINK_ST (1 << 2) 150 151 #define MII_ANAR_TXFD (1 << 8) 152 #define MII_ANAR_TX (1 << 7) 153 #define MII_ANAR_10FD (1 << 6) 154 #define MII_ANAR_10 (1 << 5) 155 #define MII_ANAR_CSMACD (1 << 0) 156 157 #define RTL8201CP_PHYID1 0x0000 158 #define RTL8201CP_PHYID2 0x8201 159 160 /* INT CTL and INT STA registers fields */ 161 #define EMAC_INT_TX_CHAN(x) (1 << (x)) 162 #define EMAC_INT_RX (1 << 8) 163 164 /* Due to lack of specifications, size of fifos is chosen arbitrarily */ 165 #define TX_FIFO_SIZE (4 * 1024) 166 #define RX_FIFO_SIZE (32 * 1024) 167 168 #define NUM_TX_FIFOS 2 169 #define RX_HDR_SIZE 8 170 #define CRC_SIZE 4 171 172 #define PHY_REG_SHIFT 0 173 #define PHY_ADDR_SHIFT 8 174 175 typedef struct RTL8201CPState { 176 uint16_t bmcr; 177 uint16_t bmsr; 178 uint16_t anar; 179 uint16_t anlpar; 180 } RTL8201CPState; 181 182 typedef struct AwEmacState { 183 /*< private >*/ 184 SysBusDevice parent_obj; 185 /*< public >*/ 186 187 MemoryRegion iomem; 188 qemu_irq irq; 189 NICState *nic; 190 NICConf conf; 191 RTL8201CPState mii; 192 uint8_t phy_addr; 193 194 uint32_t ctl; 195 uint32_t tx_mode; 196 uint32_t rx_ctl; 197 uint32_t int_ctl; 198 uint32_t int_sta; 199 uint32_t phy_target; 200 201 Fifo8 rx_fifo; 202 uint32_t rx_num_packets; 203 uint32_t rx_packet_size; 204 uint32_t rx_packet_pos; 205 206 Fifo8 tx_fifo[NUM_TX_FIFOS]; 207 uint32_t tx_length[NUM_TX_FIFOS]; 208 uint32_t tx_channel; 209 } AwEmacState; 210 211 #endif 212