1 /*
2  * Allwinner Sun8i Ethernet MAC emulation
3  *
4  * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
5  *
6  * This program is free software: you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation, either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #ifndef HW_NET_ALLWINNER_SUN8I_EMAC_H
21 #define HW_NET_ALLWINNER_SUN8I_EMAC_H
22 
23 #include "qom/object.h"
24 #include "net/net.h"
25 #include "hw/sysbus.h"
26 
27 /**
28  * Object model
29  * @{
30  */
31 
32 #define TYPE_AW_SUN8I_EMAC "allwinner-sun8i-emac"
33 typedef struct AwSun8iEmacState AwSun8iEmacState;
34 DECLARE_INSTANCE_CHECKER(AwSun8iEmacState, AW_SUN8I_EMAC,
35                          TYPE_AW_SUN8I_EMAC)
36 
37 /** @} */
38 
39 /**
40  * Allwinner Sun8i EMAC object instance state
41  */
42 struct AwSun8iEmacState {
43     /*< private >*/
44     SysBusDevice  parent_obj;
45     /*< public >*/
46 
47     /** Maps I/O registers in physical memory */
48     MemoryRegion iomem;
49 
50     /** Interrupt output signal to notify CPU */
51     qemu_irq     irq;
52 
53     /** Memory region where DMA transfers are done */
54     MemoryRegion *dma_mr;
55 
56     /** Address space used internally for DMA transfers */
57     AddressSpace dma_as;
58 
59     /** Generic Network Interface Controller (NIC) for networking API */
60     NICState     *nic;
61 
62     /** Generic Network Interface Controller (NIC) configuration */
63     NICConf      conf;
64 
65     /**
66      * @name Media Independent Interface (MII)
67      * @{
68      */
69 
70     uint8_t      mii_phy_addr;  /**< PHY address */
71     uint32_t     mii_cr;        /**< Control */
72     uint32_t     mii_st;        /**< Status */
73     uint32_t     mii_adv;       /**< Advertised Abilities */
74 
75     /** @} */
76 
77     /**
78      * @name Hardware Registers
79      * @{
80      */
81 
82     uint32_t     basic_ctl0;    /**< Basic Control 0 */
83     uint32_t     basic_ctl1;    /**< Basic Control 1 */
84     uint32_t     int_en;        /**< Interrupt Enable */
85     uint32_t     int_sta;       /**< Interrupt Status */
86     uint32_t     frm_flt;       /**< Receive Frame Filter */
87 
88     uint32_t     rx_ctl0;       /**< Receive Control 0 */
89     uint32_t     rx_ctl1;       /**< Receive Control 1 */
90     uint32_t     rx_desc_head;  /**< Receive Descriptor List Address */
91     uint32_t     rx_desc_curr;  /**< Current Receive Descriptor Address */
92 
93     uint32_t     tx_ctl0;       /**< Transmit Control 0 */
94     uint32_t     tx_ctl1;       /**< Transmit Control 1 */
95     uint32_t     tx_desc_head;  /**< Transmit Descriptor List Address */
96     uint32_t     tx_desc_curr;  /**< Current Transmit Descriptor Address */
97     uint32_t     tx_flowctl;    /**< Transmit Flow Control */
98 
99     uint32_t     mii_cmd;       /**< Management Interface Command */
100     uint32_t     mii_data;      /**< Management Interface Data */
101 
102     /** @} */
103 
104 };
105 
106 #endif /* HW_NET_ALLWINNER_SUN8I_H */
107