xref: /openbmc/qemu/include/hw/misc/xlnx-zynqmp-crf.h (revision 05caa062)
1 /*
2  * QEMU model of the CRF - Clock Reset FPD.
3  *
4  * Copyright (c) 2022 Xilinx Inc.
5  * SPDX-License-Identifier: GPL-2.0-or-later
6  * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
7  */
8 #ifndef HW_MISC_XLNX_ZYNQMP_CRF_H
9 #define HW_MISC_XLNX_ZYNQMP_CRF_H
10 
11 #include "hw/sysbus.h"
12 #include "hw/register.h"
13 
14 #define TYPE_XLNX_ZYNQMP_CRF "xlnx.zynqmp_crf"
15 OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPCRF, XLNX_ZYNQMP_CRF)
16 
17 REG32(ERR_CTRL, 0x0)
18     FIELD(ERR_CTRL, SLVERR_ENABLE, 0, 1)
19 REG32(IR_STATUS, 0x4)
20     FIELD(IR_STATUS, ADDR_DECODE_ERR, 0, 1)
21 REG32(IR_MASK, 0x8)
22     FIELD(IR_MASK, ADDR_DECODE_ERR, 0, 1)
23 REG32(IR_ENABLE, 0xc)
24     FIELD(IR_ENABLE, ADDR_DECODE_ERR, 0, 1)
25 REG32(IR_DISABLE, 0x10)
26     FIELD(IR_DISABLE, ADDR_DECODE_ERR, 0, 1)
27 REG32(CRF_WPROT, 0x1c)
28     FIELD(CRF_WPROT, ACTIVE, 0, 1)
29 REG32(APLL_CTRL, 0x20)
30     FIELD(APLL_CTRL, POST_SRC, 24, 3)
31     FIELD(APLL_CTRL, PRE_SRC, 20, 3)
32     FIELD(APLL_CTRL, CLKOUTDIV, 17, 1)
33     FIELD(APLL_CTRL, DIV2, 16, 1)
34     FIELD(APLL_CTRL, FBDIV, 8, 7)
35     FIELD(APLL_CTRL, BYPASS, 3, 1)
36     FIELD(APLL_CTRL, RESET, 0, 1)
37 REG32(APLL_CFG, 0x24)
38     FIELD(APLL_CFG, LOCK_DLY, 25, 7)
39     FIELD(APLL_CFG, LOCK_CNT, 13, 10)
40     FIELD(APLL_CFG, LFHF, 10, 2)
41     FIELD(APLL_CFG, CP, 5, 4)
42     FIELD(APLL_CFG, RES, 0, 4)
43 REG32(APLL_FRAC_CFG, 0x28)
44     FIELD(APLL_FRAC_CFG, ENABLED, 31, 1)
45     FIELD(APLL_FRAC_CFG, SEED, 22, 3)
46     FIELD(APLL_FRAC_CFG, ALGRTHM, 19, 1)
47     FIELD(APLL_FRAC_CFG, ORDER, 18, 1)
48     FIELD(APLL_FRAC_CFG, DATA, 0, 16)
49 REG32(DPLL_CTRL, 0x2c)
50     FIELD(DPLL_CTRL, POST_SRC, 24, 3)
51     FIELD(DPLL_CTRL, PRE_SRC, 20, 3)
52     FIELD(DPLL_CTRL, CLKOUTDIV, 17, 1)
53     FIELD(DPLL_CTRL, DIV2, 16, 1)
54     FIELD(DPLL_CTRL, FBDIV, 8, 7)
55     FIELD(DPLL_CTRL, BYPASS, 3, 1)
56     FIELD(DPLL_CTRL, RESET, 0, 1)
57 REG32(DPLL_CFG, 0x30)
58     FIELD(DPLL_CFG, LOCK_DLY, 25, 7)
59     FIELD(DPLL_CFG, LOCK_CNT, 13, 10)
60     FIELD(DPLL_CFG, LFHF, 10, 2)
61     FIELD(DPLL_CFG, CP, 5, 4)
62     FIELD(DPLL_CFG, RES, 0, 4)
63 REG32(DPLL_FRAC_CFG, 0x34)
64     FIELD(DPLL_FRAC_CFG, ENABLED, 31, 1)
65     FIELD(DPLL_FRAC_CFG, SEED, 22, 3)
66     FIELD(DPLL_FRAC_CFG, ALGRTHM, 19, 1)
67     FIELD(DPLL_FRAC_CFG, ORDER, 18, 1)
68     FIELD(DPLL_FRAC_CFG, DATA, 0, 16)
69 REG32(VPLL_CTRL, 0x38)
70     FIELD(VPLL_CTRL, POST_SRC, 24, 3)
71     FIELD(VPLL_CTRL, PRE_SRC, 20, 3)
72     FIELD(VPLL_CTRL, CLKOUTDIV, 17, 1)
73     FIELD(VPLL_CTRL, DIV2, 16, 1)
74     FIELD(VPLL_CTRL, FBDIV, 8, 7)
75     FIELD(VPLL_CTRL, BYPASS, 3, 1)
76     FIELD(VPLL_CTRL, RESET, 0, 1)
77 REG32(VPLL_CFG, 0x3c)
78     FIELD(VPLL_CFG, LOCK_DLY, 25, 7)
79     FIELD(VPLL_CFG, LOCK_CNT, 13, 10)
80     FIELD(VPLL_CFG, LFHF, 10, 2)
81     FIELD(VPLL_CFG, CP, 5, 4)
82     FIELD(VPLL_CFG, RES, 0, 4)
83 REG32(VPLL_FRAC_CFG, 0x40)
84     FIELD(VPLL_FRAC_CFG, ENABLED, 31, 1)
85     FIELD(VPLL_FRAC_CFG, SEED, 22, 3)
86     FIELD(VPLL_FRAC_CFG, ALGRTHM, 19, 1)
87     FIELD(VPLL_FRAC_CFG, ORDER, 18, 1)
88     FIELD(VPLL_FRAC_CFG, DATA, 0, 16)
89 REG32(PLL_STATUS, 0x44)
90     FIELD(PLL_STATUS, VPLL_STABLE, 5, 1)
91     FIELD(PLL_STATUS, DPLL_STABLE, 4, 1)
92     FIELD(PLL_STATUS, APLL_STABLE, 3, 1)
93     FIELD(PLL_STATUS, VPLL_LOCK, 2, 1)
94     FIELD(PLL_STATUS, DPLL_LOCK, 1, 1)
95     FIELD(PLL_STATUS, APLL_LOCK, 0, 1)
96 REG32(APLL_TO_LPD_CTRL, 0x48)
97     FIELD(APLL_TO_LPD_CTRL, DIVISOR0, 8, 6)
98 REG32(DPLL_TO_LPD_CTRL, 0x4c)
99     FIELD(DPLL_TO_LPD_CTRL, DIVISOR0, 8, 6)
100 REG32(VPLL_TO_LPD_CTRL, 0x50)
101     FIELD(VPLL_TO_LPD_CTRL, DIVISOR0, 8, 6)
102 REG32(ACPU_CTRL, 0x60)
103     FIELD(ACPU_CTRL, CLKACT_HALF, 25, 1)
104     FIELD(ACPU_CTRL, CLKACT_FULL, 24, 1)
105     FIELD(ACPU_CTRL, DIVISOR0, 8, 6)
106     FIELD(ACPU_CTRL, SRCSEL, 0, 3)
107 REG32(DBG_TRACE_CTRL, 0x64)
108     FIELD(DBG_TRACE_CTRL, CLKACT, 24, 1)
109     FIELD(DBG_TRACE_CTRL, DIVISOR0, 8, 6)
110     FIELD(DBG_TRACE_CTRL, SRCSEL, 0, 3)
111 REG32(DBG_FPD_CTRL, 0x68)
112     FIELD(DBG_FPD_CTRL, CLKACT, 24, 1)
113     FIELD(DBG_FPD_CTRL, DIVISOR0, 8, 6)
114     FIELD(DBG_FPD_CTRL, SRCSEL, 0, 3)
115 REG32(DP_VIDEO_REF_CTRL, 0x70)
116     FIELD(DP_VIDEO_REF_CTRL, CLKACT, 24, 1)
117     FIELD(DP_VIDEO_REF_CTRL, DIVISOR1, 16, 6)
118     FIELD(DP_VIDEO_REF_CTRL, DIVISOR0, 8, 6)
119     FIELD(DP_VIDEO_REF_CTRL, SRCSEL, 0, 3)
120 REG32(DP_AUDIO_REF_CTRL, 0x74)
121     FIELD(DP_AUDIO_REF_CTRL, CLKACT, 24, 1)
122     FIELD(DP_AUDIO_REF_CTRL, DIVISOR1, 16, 6)
123     FIELD(DP_AUDIO_REF_CTRL, DIVISOR0, 8, 6)
124     FIELD(DP_AUDIO_REF_CTRL, SRCSEL, 0, 3)
125 REG32(DP_STC_REF_CTRL, 0x7c)
126     FIELD(DP_STC_REF_CTRL, CLKACT, 24, 1)
127     FIELD(DP_STC_REF_CTRL, DIVISOR1, 16, 6)
128     FIELD(DP_STC_REF_CTRL, DIVISOR0, 8, 6)
129     FIELD(DP_STC_REF_CTRL, SRCSEL, 0, 3)
130 REG32(DDR_CTRL, 0x80)
131     FIELD(DDR_CTRL, CLKACT, 24, 1)
132     FIELD(DDR_CTRL, DIVISOR0, 8, 6)
133     FIELD(DDR_CTRL, SRCSEL, 0, 3)
134 REG32(GPU_REF_CTRL, 0x84)
135     FIELD(GPU_REF_CTRL, PP1_CLKACT, 26, 1)
136     FIELD(GPU_REF_CTRL, PP0_CLKACT, 25, 1)
137     FIELD(GPU_REF_CTRL, CLKACT, 24, 1)
138     FIELD(GPU_REF_CTRL, DIVISOR0, 8, 6)
139     FIELD(GPU_REF_CTRL, SRCSEL, 0, 3)
140 REG32(SATA_REF_CTRL, 0xa0)
141     FIELD(SATA_REF_CTRL, CLKACT, 24, 1)
142     FIELD(SATA_REF_CTRL, DIVISOR0, 8, 6)
143     FIELD(SATA_REF_CTRL, SRCSEL, 0, 3)
144 REG32(PCIE_REF_CTRL, 0xb4)
145     FIELD(PCIE_REF_CTRL, CLKACT, 24, 1)
146     FIELD(PCIE_REF_CTRL, DIVISOR0, 8, 6)
147     FIELD(PCIE_REF_CTRL, SRCSEL, 0, 3)
148 REG32(GDMA_REF_CTRL, 0xb8)
149     FIELD(GDMA_REF_CTRL, CLKACT, 24, 1)
150     FIELD(GDMA_REF_CTRL, DIVISOR0, 8, 6)
151     FIELD(GDMA_REF_CTRL, SRCSEL, 0, 3)
152 REG32(DPDMA_REF_CTRL, 0xbc)
153     FIELD(DPDMA_REF_CTRL, CLKACT, 24, 1)
154     FIELD(DPDMA_REF_CTRL, DIVISOR0, 8, 6)
155     FIELD(DPDMA_REF_CTRL, SRCSEL, 0, 3)
156 REG32(TOPSW_MAIN_CTRL, 0xc0)
157     FIELD(TOPSW_MAIN_CTRL, CLKACT, 24, 1)
158     FIELD(TOPSW_MAIN_CTRL, DIVISOR0, 8, 6)
159     FIELD(TOPSW_MAIN_CTRL, SRCSEL, 0, 3)
160 REG32(TOPSW_LSBUS_CTRL, 0xc4)
161     FIELD(TOPSW_LSBUS_CTRL, CLKACT, 24, 1)
162     FIELD(TOPSW_LSBUS_CTRL, DIVISOR0, 8, 6)
163     FIELD(TOPSW_LSBUS_CTRL, SRCSEL, 0, 3)
164 REG32(DBG_TSTMP_CTRL, 0xf8)
165     FIELD(DBG_TSTMP_CTRL, DIVISOR0, 8, 6)
166     FIELD(DBG_TSTMP_CTRL, SRCSEL, 0, 3)
167 REG32(RST_FPD_TOP, 0x100)
168     FIELD(RST_FPD_TOP, PCIE_CFG_RESET, 19, 1)
169     FIELD(RST_FPD_TOP, PCIE_BRIDGE_RESET, 18, 1)
170     FIELD(RST_FPD_TOP, PCIE_CTRL_RESET, 17, 1)
171     FIELD(RST_FPD_TOP, DP_RESET, 16, 1)
172     FIELD(RST_FPD_TOP, SWDT_RESET, 15, 1)
173     FIELD(RST_FPD_TOP, AFI_FM5_RESET, 12, 1)
174     FIELD(RST_FPD_TOP, AFI_FM4_RESET, 11, 1)
175     FIELD(RST_FPD_TOP, AFI_FM3_RESET, 10, 1)
176     FIELD(RST_FPD_TOP, AFI_FM2_RESET, 9, 1)
177     FIELD(RST_FPD_TOP, AFI_FM1_RESET, 8, 1)
178     FIELD(RST_FPD_TOP, AFI_FM0_RESET, 7, 1)
179     FIELD(RST_FPD_TOP, GDMA_RESET, 6, 1)
180     FIELD(RST_FPD_TOP, GPU_PP1_RESET, 5, 1)
181     FIELD(RST_FPD_TOP, GPU_PP0_RESET, 4, 1)
182     FIELD(RST_FPD_TOP, GPU_RESET, 3, 1)
183     FIELD(RST_FPD_TOP, GT_RESET, 2, 1)
184     FIELD(RST_FPD_TOP, SATA_RESET, 1, 1)
185 REG32(RST_FPD_APU, 0x104)
186     FIELD(RST_FPD_APU, ACPU3_PWRON_RESET, 13, 1)
187     FIELD(RST_FPD_APU, ACPU2_PWRON_RESET, 12, 1)
188     FIELD(RST_FPD_APU, ACPU1_PWRON_RESET, 11, 1)
189     FIELD(RST_FPD_APU, ACPU0_PWRON_RESET, 10, 1)
190     FIELD(RST_FPD_APU, APU_L2_RESET, 8, 1)
191     FIELD(RST_FPD_APU, ACPU3_RESET, 3, 1)
192     FIELD(RST_FPD_APU, ACPU2_RESET, 2, 1)
193     FIELD(RST_FPD_APU, ACPU1_RESET, 1, 1)
194     FIELD(RST_FPD_APU, ACPU0_RESET, 0, 1)
195 REG32(RST_DDR_SS, 0x108)
196     FIELD(RST_DDR_SS, DDR_RESET, 3, 1)
197     FIELD(RST_DDR_SS, APM_RESET, 2, 1)
198 
199 #define CRF_R_MAX (R_RST_DDR_SS + 1)
200 
201 struct XlnxZynqMPCRF {
202     SysBusDevice parent_obj;
203     MemoryRegion iomem;
204     qemu_irq irq_ir;
205 
206     RegisterInfoArray *reg_array;
207     uint32_t regs[CRF_R_MAX];
208     RegisterInfo regs_info[CRF_R_MAX];
209 };
210 
211 #endif
212