1 /* 2 * QEMU model of the Clock-Reset-LPD (CRL). 3 * 4 * Copyright (c) 2022 Xilinx Inc. 5 * SPDX-License-Identifier: GPL-2.0-or-later 6 * 7 * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com> 8 */ 9 #ifndef HW_MISC_XLNX_VERSAL_CRL_H 10 #define HW_MISC_XLNX_VERSAL_CRL_H 11 12 #include "hw/sysbus.h" 13 #include "hw/register.h" 14 #include "target/arm/cpu.h" 15 16 #define TYPE_XLNX_VERSAL_CRL "xlnx,versal-crl" 17 OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCRL, XLNX_VERSAL_CRL) 18 19 REG32(ERR_CTRL, 0x0) 20 FIELD(ERR_CTRL, SLVERR_ENABLE, 0, 1) 21 REG32(IR_STATUS, 0x4) 22 FIELD(IR_STATUS, ADDR_DECODE_ERR, 0, 1) 23 REG32(IR_MASK, 0x8) 24 FIELD(IR_MASK, ADDR_DECODE_ERR, 0, 1) 25 REG32(IR_ENABLE, 0xc) 26 FIELD(IR_ENABLE, ADDR_DECODE_ERR, 0, 1) 27 REG32(IR_DISABLE, 0x10) 28 FIELD(IR_DISABLE, ADDR_DECODE_ERR, 0, 1) 29 REG32(WPROT, 0x1c) 30 FIELD(WPROT, ACTIVE, 0, 1) 31 REG32(PLL_CLK_OTHER_DMN, 0x20) 32 FIELD(PLL_CLK_OTHER_DMN, APLL_BYPASS, 0, 1) 33 REG32(RPLL_CTRL, 0x40) 34 FIELD(RPLL_CTRL, POST_SRC, 24, 3) 35 FIELD(RPLL_CTRL, PRE_SRC, 20, 3) 36 FIELD(RPLL_CTRL, CLKOUTDIV, 16, 2) 37 FIELD(RPLL_CTRL, FBDIV, 8, 8) 38 FIELD(RPLL_CTRL, BYPASS, 3, 1) 39 FIELD(RPLL_CTRL, RESET, 0, 1) 40 REG32(RPLL_CFG, 0x44) 41 FIELD(RPLL_CFG, LOCK_DLY, 25, 7) 42 FIELD(RPLL_CFG, LOCK_CNT, 13, 10) 43 FIELD(RPLL_CFG, LFHF, 10, 2) 44 FIELD(RPLL_CFG, CP, 5, 4) 45 FIELD(RPLL_CFG, RES, 0, 4) 46 REG32(RPLL_FRAC_CFG, 0x48) 47 FIELD(RPLL_FRAC_CFG, ENABLED, 31, 1) 48 FIELD(RPLL_FRAC_CFG, SEED, 22, 3) 49 FIELD(RPLL_FRAC_CFG, ALGRTHM, 19, 1) 50 FIELD(RPLL_FRAC_CFG, ORDER, 18, 1) 51 FIELD(RPLL_FRAC_CFG, DATA, 0, 16) 52 REG32(PLL_STATUS, 0x50) 53 FIELD(PLL_STATUS, RPLL_STABLE, 2, 1) 54 FIELD(PLL_STATUS, RPLL_LOCK, 0, 1) 55 REG32(RPLL_TO_XPD_CTRL, 0x100) 56 FIELD(RPLL_TO_XPD_CTRL, CLKACT, 25, 1) 57 FIELD(RPLL_TO_XPD_CTRL, DIVISOR0, 8, 10) 58 REG32(LPD_TOP_SWITCH_CTRL, 0x104) 59 FIELD(LPD_TOP_SWITCH_CTRL, CLKACT_ADMA, 26, 1) 60 FIELD(LPD_TOP_SWITCH_CTRL, CLKACT, 25, 1) 61 FIELD(LPD_TOP_SWITCH_CTRL, DIVISOR0, 8, 10) 62 FIELD(LPD_TOP_SWITCH_CTRL, SRCSEL, 0, 3) 63 REG32(LPD_LSBUS_CTRL, 0x108) 64 FIELD(LPD_LSBUS_CTRL, CLKACT, 25, 1) 65 FIELD(LPD_LSBUS_CTRL, DIVISOR0, 8, 10) 66 FIELD(LPD_LSBUS_CTRL, SRCSEL, 0, 3) 67 REG32(CPU_R5_CTRL, 0x10c) 68 FIELD(CPU_R5_CTRL, CLKACT_OCM2, 28, 1) 69 FIELD(CPU_R5_CTRL, CLKACT_OCM, 27, 1) 70 FIELD(CPU_R5_CTRL, CLKACT_CORE, 26, 1) 71 FIELD(CPU_R5_CTRL, CLKACT, 25, 1) 72 FIELD(CPU_R5_CTRL, DIVISOR0, 8, 10) 73 FIELD(CPU_R5_CTRL, SRCSEL, 0, 3) 74 REG32(IOU_SWITCH_CTRL, 0x114) 75 FIELD(IOU_SWITCH_CTRL, CLKACT, 25, 1) 76 FIELD(IOU_SWITCH_CTRL, DIVISOR0, 8, 10) 77 FIELD(IOU_SWITCH_CTRL, SRCSEL, 0, 3) 78 REG32(GEM0_REF_CTRL, 0x118) 79 FIELD(GEM0_REF_CTRL, CLKACT_RX, 27, 1) 80 FIELD(GEM0_REF_CTRL, CLKACT_TX, 26, 1) 81 FIELD(GEM0_REF_CTRL, CLKACT, 25, 1) 82 FIELD(GEM0_REF_CTRL, DIVISOR0, 8, 10) 83 FIELD(GEM0_REF_CTRL, SRCSEL, 0, 3) 84 REG32(GEM1_REF_CTRL, 0x11c) 85 FIELD(GEM1_REF_CTRL, CLKACT_RX, 27, 1) 86 FIELD(GEM1_REF_CTRL, CLKACT_TX, 26, 1) 87 FIELD(GEM1_REF_CTRL, CLKACT, 25, 1) 88 FIELD(GEM1_REF_CTRL, DIVISOR0, 8, 10) 89 FIELD(GEM1_REF_CTRL, SRCSEL, 0, 3) 90 REG32(GEM_TSU_REF_CTRL, 0x120) 91 FIELD(GEM_TSU_REF_CTRL, CLKACT, 25, 1) 92 FIELD(GEM_TSU_REF_CTRL, DIVISOR0, 8, 10) 93 FIELD(GEM_TSU_REF_CTRL, SRCSEL, 0, 3) 94 REG32(USB0_BUS_REF_CTRL, 0x124) 95 FIELD(USB0_BUS_REF_CTRL, CLKACT, 25, 1) 96 FIELD(USB0_BUS_REF_CTRL, DIVISOR0, 8, 10) 97 FIELD(USB0_BUS_REF_CTRL, SRCSEL, 0, 3) 98 REG32(UART0_REF_CTRL, 0x128) 99 FIELD(UART0_REF_CTRL, CLKACT, 25, 1) 100 FIELD(UART0_REF_CTRL, DIVISOR0, 8, 10) 101 FIELD(UART0_REF_CTRL, SRCSEL, 0, 3) 102 REG32(UART1_REF_CTRL, 0x12c) 103 FIELD(UART1_REF_CTRL, CLKACT, 25, 1) 104 FIELD(UART1_REF_CTRL, DIVISOR0, 8, 10) 105 FIELD(UART1_REF_CTRL, SRCSEL, 0, 3) 106 REG32(SPI0_REF_CTRL, 0x130) 107 FIELD(SPI0_REF_CTRL, CLKACT, 25, 1) 108 FIELD(SPI0_REF_CTRL, DIVISOR0, 8, 10) 109 FIELD(SPI0_REF_CTRL, SRCSEL, 0, 3) 110 REG32(SPI1_REF_CTRL, 0x134) 111 FIELD(SPI1_REF_CTRL, CLKACT, 25, 1) 112 FIELD(SPI1_REF_CTRL, DIVISOR0, 8, 10) 113 FIELD(SPI1_REF_CTRL, SRCSEL, 0, 3) 114 REG32(CAN0_REF_CTRL, 0x138) 115 FIELD(CAN0_REF_CTRL, CLKACT, 25, 1) 116 FIELD(CAN0_REF_CTRL, DIVISOR0, 8, 10) 117 FIELD(CAN0_REF_CTRL, SRCSEL, 0, 3) 118 REG32(CAN1_REF_CTRL, 0x13c) 119 FIELD(CAN1_REF_CTRL, CLKACT, 25, 1) 120 FIELD(CAN1_REF_CTRL, DIVISOR0, 8, 10) 121 FIELD(CAN1_REF_CTRL, SRCSEL, 0, 3) 122 REG32(I2C0_REF_CTRL, 0x140) 123 FIELD(I2C0_REF_CTRL, CLKACT, 25, 1) 124 FIELD(I2C0_REF_CTRL, DIVISOR0, 8, 10) 125 FIELD(I2C0_REF_CTRL, SRCSEL, 0, 3) 126 REG32(I2C1_REF_CTRL, 0x144) 127 FIELD(I2C1_REF_CTRL, CLKACT, 25, 1) 128 FIELD(I2C1_REF_CTRL, DIVISOR0, 8, 10) 129 FIELD(I2C1_REF_CTRL, SRCSEL, 0, 3) 130 REG32(DBG_LPD_CTRL, 0x148) 131 FIELD(DBG_LPD_CTRL, CLKACT, 25, 1) 132 FIELD(DBG_LPD_CTRL, DIVISOR0, 8, 10) 133 FIELD(DBG_LPD_CTRL, SRCSEL, 0, 3) 134 REG32(TIMESTAMP_REF_CTRL, 0x14c) 135 FIELD(TIMESTAMP_REF_CTRL, CLKACT, 25, 1) 136 FIELD(TIMESTAMP_REF_CTRL, DIVISOR0, 8, 10) 137 FIELD(TIMESTAMP_REF_CTRL, SRCSEL, 0, 3) 138 REG32(CRL_SAFETY_CHK, 0x150) 139 REG32(PSM_REF_CTRL, 0x154) 140 FIELD(PSM_REF_CTRL, DIVISOR0, 8, 10) 141 FIELD(PSM_REF_CTRL, SRCSEL, 0, 3) 142 REG32(DBG_TSTMP_CTRL, 0x158) 143 FIELD(DBG_TSTMP_CTRL, CLKACT, 25, 1) 144 FIELD(DBG_TSTMP_CTRL, DIVISOR0, 8, 10) 145 FIELD(DBG_TSTMP_CTRL, SRCSEL, 0, 3) 146 REG32(CPM_TOPSW_REF_CTRL, 0x15c) 147 FIELD(CPM_TOPSW_REF_CTRL, CLKACT, 25, 1) 148 FIELD(CPM_TOPSW_REF_CTRL, DIVISOR0, 8, 10) 149 FIELD(CPM_TOPSW_REF_CTRL, SRCSEL, 0, 3) 150 REG32(USB3_DUAL_REF_CTRL, 0x160) 151 FIELD(USB3_DUAL_REF_CTRL, CLKACT, 25, 1) 152 FIELD(USB3_DUAL_REF_CTRL, DIVISOR0, 8, 10) 153 FIELD(USB3_DUAL_REF_CTRL, SRCSEL, 0, 3) 154 REG32(RST_CPU_R5, 0x300) 155 FIELD(RST_CPU_R5, RESET_PGE, 4, 1) 156 FIELD(RST_CPU_R5, RESET_AMBA, 2, 1) 157 FIELD(RST_CPU_R5, RESET_CPU1, 1, 1) 158 FIELD(RST_CPU_R5, RESET_CPU0, 0, 1) 159 REG32(RST_ADMA, 0x304) 160 FIELD(RST_ADMA, RESET, 0, 1) 161 REG32(RST_GEM0, 0x308) 162 FIELD(RST_GEM0, RESET, 0, 1) 163 REG32(RST_GEM1, 0x30c) 164 FIELD(RST_GEM1, RESET, 0, 1) 165 REG32(RST_SPARE, 0x310) 166 FIELD(RST_SPARE, RESET, 0, 1) 167 REG32(RST_USB0, 0x314) 168 FIELD(RST_USB0, RESET, 0, 1) 169 REG32(RST_UART0, 0x318) 170 FIELD(RST_UART0, RESET, 0, 1) 171 REG32(RST_UART1, 0x31c) 172 FIELD(RST_UART1, RESET, 0, 1) 173 REG32(RST_SPI0, 0x320) 174 FIELD(RST_SPI0, RESET, 0, 1) 175 REG32(RST_SPI1, 0x324) 176 FIELD(RST_SPI1, RESET, 0, 1) 177 REG32(RST_CAN0, 0x328) 178 FIELD(RST_CAN0, RESET, 0, 1) 179 REG32(RST_CAN1, 0x32c) 180 FIELD(RST_CAN1, RESET, 0, 1) 181 REG32(RST_I2C0, 0x330) 182 FIELD(RST_I2C0, RESET, 0, 1) 183 REG32(RST_I2C1, 0x334) 184 FIELD(RST_I2C1, RESET, 0, 1) 185 REG32(RST_DBG_LPD, 0x338) 186 FIELD(RST_DBG_LPD, RPU_DBG1_RESET, 5, 1) 187 FIELD(RST_DBG_LPD, RPU_DBG0_RESET, 4, 1) 188 FIELD(RST_DBG_LPD, RESET_HSDP, 1, 1) 189 FIELD(RST_DBG_LPD, RESET, 0, 1) 190 REG32(RST_GPIO, 0x33c) 191 FIELD(RST_GPIO, RESET, 0, 1) 192 REG32(RST_TTC, 0x344) 193 FIELD(RST_TTC, TTC3_RESET, 3, 1) 194 FIELD(RST_TTC, TTC2_RESET, 2, 1) 195 FIELD(RST_TTC, TTC1_RESET, 1, 1) 196 FIELD(RST_TTC, TTC0_RESET, 0, 1) 197 REG32(RST_TIMESTAMP, 0x348) 198 FIELD(RST_TIMESTAMP, RESET, 0, 1) 199 REG32(RST_SWDT, 0x34c) 200 FIELD(RST_SWDT, RESET, 0, 1) 201 REG32(RST_OCM, 0x350) 202 FIELD(RST_OCM, RESET, 0, 1) 203 REG32(RST_IPI, 0x354) 204 FIELD(RST_IPI, RESET, 0, 1) 205 REG32(RST_SYSMON, 0x358) 206 FIELD(RST_SYSMON, SEQ_RST, 1, 1) 207 FIELD(RST_SYSMON, CFG_RST, 0, 1) 208 REG32(RST_FPD, 0x360) 209 FIELD(RST_FPD, SRST, 1, 1) 210 FIELD(RST_FPD, POR, 0, 1) 211 REG32(PSM_RST_MODE, 0x370) 212 FIELD(PSM_RST_MODE, WAKEUP, 2, 1) 213 FIELD(PSM_RST_MODE, RST_MODE, 0, 2) 214 215 #define CRL_R_MAX (R_PSM_RST_MODE + 1) 216 217 #define RPU_MAX_CPU 2 218 219 struct XlnxVersalCRL { 220 SysBusDevice parent_obj; 221 qemu_irq irq; 222 223 struct { 224 ARMCPU *cpu_r5[RPU_MAX_CPU]; 225 DeviceState *adma[8]; 226 DeviceState *uart[2]; 227 DeviceState *gem[2]; 228 DeviceState *usb; 229 } cfg; 230 231 RegisterInfoArray *reg_array; 232 uint32_t regs[CRL_R_MAX]; 233 RegisterInfo regs_info[CRL_R_MAX]; 234 }; 235 #endif 236