1 /*
2  * STM32L4x5 SYSCFG (System Configuration Controller)
3  *
4  * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
5  * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * This work is licensed under the terms of the GNU GPL, version 2 or later.
10  * See the COPYING file in the top-level directory.
11  *
12  * This work is based on the stm32f4xx_syscfg by Alistair Francis.
13  * Original code is licensed under the MIT License:
14  *
15  * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
16  */
17 
18 /*
19  * The reference used is the STMicroElectronics RM0351 Reference manual
20  * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
21  * https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html
22  */
23 
24 #ifndef HW_STM32L4X5_SYSCFG_H
25 #define HW_STM32L4X5_SYSCFG_H
26 
27 #include "hw/sysbus.h"
28 #include "qom/object.h"
29 
30 #define TYPE_STM32L4X5_SYSCFG "stm32l4x5-syscfg"
31 OBJECT_DECLARE_SIMPLE_TYPE(Stm32l4x5SyscfgState, STM32L4X5_SYSCFG)
32 
33 #define NUM_GPIOS 8
34 #define GPIO_NUM_PINS 16
35 #define SYSCFG_NUM_EXTICR 4
36 
37 struct Stm32l4x5SyscfgState {
38     SysBusDevice parent_obj;
39 
40     MemoryRegion mmio;
41 
42     uint32_t memrmp;
43     uint32_t cfgr1;
44     uint32_t exticr[SYSCFG_NUM_EXTICR];
45     uint32_t scsr;
46     uint32_t cfgr2;
47     uint32_t swpr;
48     uint32_t skr;
49     uint32_t swpr2;
50 
51     qemu_irq gpio_out[GPIO_NUM_PINS];
52 };
53 
54 #endif
55