1*d6b55a0fSArnaud Minier /* 2*d6b55a0fSArnaud Minier * STM32L4X5 RCC (Reset and clock control) 3*d6b55a0fSArnaud Minier * 4*d6b55a0fSArnaud Minier * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr> 5*d6b55a0fSArnaud Minier * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr> 6*d6b55a0fSArnaud Minier * 7*d6b55a0fSArnaud Minier * SPDX-License-Identifier: GPL-2.0-or-later 8*d6b55a0fSArnaud Minier * 9*d6b55a0fSArnaud Minier * This work is licensed under the terms of the GNU GPL, version 2 or later. 10*d6b55a0fSArnaud Minier * See the COPYING file in the top-level directory. 11*d6b55a0fSArnaud Minier * 12*d6b55a0fSArnaud Minier * The reference used is the STMicroElectronics RM0351 Reference manual 13*d6b55a0fSArnaud Minier * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs. 14*d6b55a0fSArnaud Minier * 15*d6b55a0fSArnaud Minier * Inspired by the BCM2835 CPRMAN clock manager by Luc Michel. 16*d6b55a0fSArnaud Minier */ 17*d6b55a0fSArnaud Minier 18*d6b55a0fSArnaud Minier #ifndef HW_STM32L4X5_RCC_H 19*d6b55a0fSArnaud Minier #define HW_STM32L4X5_RCC_H 20*d6b55a0fSArnaud Minier 21*d6b55a0fSArnaud Minier #include "hw/sysbus.h" 22*d6b55a0fSArnaud Minier #include "qom/object.h" 23*d6b55a0fSArnaud Minier 24*d6b55a0fSArnaud Minier #define TYPE_STM32L4X5_RCC "stm32l4x5-rcc" 25*d6b55a0fSArnaud Minier OBJECT_DECLARE_SIMPLE_TYPE(Stm32l4x5RccState, STM32L4X5_RCC) 26*d6b55a0fSArnaud Minier 27*d6b55a0fSArnaud Minier /* In the Stm32l4x5 clock tree, mux have at most 7 sources */ 28*d6b55a0fSArnaud Minier #define RCC_NUM_CLOCK_MUX_SRC 7 29*d6b55a0fSArnaud Minier struct Stm32l4x5RccState { 30*d6b55a0fSArnaud Minier SysBusDevice parent_obj; 31*d6b55a0fSArnaud Minier 32*d6b55a0fSArnaud Minier MemoryRegion mmio; 33*d6b55a0fSArnaud Minier 34*d6b55a0fSArnaud Minier uint32_t cr; 35*d6b55a0fSArnaud Minier uint32_t icscr; 36*d6b55a0fSArnaud Minier uint32_t cfgr; 37*d6b55a0fSArnaud Minier uint32_t pllcfgr; 38*d6b55a0fSArnaud Minier uint32_t pllsai1cfgr; 39*d6b55a0fSArnaud Minier uint32_t pllsai2cfgr; 40*d6b55a0fSArnaud Minier uint32_t cier; 41*d6b55a0fSArnaud Minier uint32_t cifr; 42*d6b55a0fSArnaud Minier uint32_t ahb1rstr; 43*d6b55a0fSArnaud Minier uint32_t ahb2rstr; 44*d6b55a0fSArnaud Minier uint32_t ahb3rstr; 45*d6b55a0fSArnaud Minier uint32_t apb1rstr1; 46*d6b55a0fSArnaud Minier uint32_t apb1rstr2; 47*d6b55a0fSArnaud Minier uint32_t apb2rstr; 48*d6b55a0fSArnaud Minier uint32_t ahb1enr; 49*d6b55a0fSArnaud Minier uint32_t ahb2enr; 50*d6b55a0fSArnaud Minier uint32_t ahb3enr; 51*d6b55a0fSArnaud Minier uint32_t apb1enr1; 52*d6b55a0fSArnaud Minier uint32_t apb1enr2; 53*d6b55a0fSArnaud Minier uint32_t apb2enr; 54*d6b55a0fSArnaud Minier uint32_t ahb1smenr; 55*d6b55a0fSArnaud Minier uint32_t ahb2smenr; 56*d6b55a0fSArnaud Minier uint32_t ahb3smenr; 57*d6b55a0fSArnaud Minier uint32_t apb1smenr1; 58*d6b55a0fSArnaud Minier uint32_t apb1smenr2; 59*d6b55a0fSArnaud Minier uint32_t apb2smenr; 60*d6b55a0fSArnaud Minier uint32_t ccipr; 61*d6b55a0fSArnaud Minier uint32_t bdcr; 62*d6b55a0fSArnaud Minier uint32_t csr; 63*d6b55a0fSArnaud Minier 64*d6b55a0fSArnaud Minier /* Clock sources */ 65*d6b55a0fSArnaud Minier Clock *gnd; 66*d6b55a0fSArnaud Minier Clock *hsi16_rc; 67*d6b55a0fSArnaud Minier Clock *msi_rc; 68*d6b55a0fSArnaud Minier Clock *hse; 69*d6b55a0fSArnaud Minier Clock *lsi_rc; 70*d6b55a0fSArnaud Minier Clock *lse_crystal; 71*d6b55a0fSArnaud Minier Clock *sai1_extclk; 72*d6b55a0fSArnaud Minier Clock *sai2_extclk; 73*d6b55a0fSArnaud Minier 74*d6b55a0fSArnaud Minier qemu_irq irq; 75*d6b55a0fSArnaud Minier uint64_t hse_frequency; 76*d6b55a0fSArnaud Minier uint64_t sai1_extclk_frequency; 77*d6b55a0fSArnaud Minier uint64_t sai2_extclk_frequency; 78*d6b55a0fSArnaud Minier }; 79*d6b55a0fSArnaud Minier 80*d6b55a0fSArnaud Minier #endif /* HW_STM32L4X5_RCC_H */ 81