1 /* 2 * STM32 RCC (only reset and enable registers are implemented) 3 * 4 * Copyright (c) 2024 Román Cárdenas <rcardenas.rod@gmail.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #ifndef HW_STM32_RCC_H 26 #define HW_STM32_RCC_H 27 28 #include "hw/sysbus.h" 29 #include "qom/object.h" 30 31 #define STM32_RCC_CR 0x00 32 #define STM32_RCC_PLL_CFGR 0x04 33 #define STM32_RCC_CFGR 0x08 34 #define STM32_RCC_CIR 0x0C 35 #define STM32_RCC_AHB1_RSTR 0x10 36 #define STM32_RCC_AHB2_RSTR 0x14 37 #define STM32_RCC_AHB3_RSTR 0x18 38 39 #define STM32_RCC_APB1_RSTR 0x20 40 #define STM32_RCC_APB2_RSTR 0x24 41 42 #define STM32_RCC_AHB1_ENR 0x30 43 #define STM32_RCC_AHB2_ENR 0x34 44 #define STM32_RCC_AHB3_ENR 0x38 45 46 #define STM32_RCC_APB1_ENR 0x40 47 #define STM32_RCC_APB2_ENR 0x44 48 49 #define STM32_RCC_AHB1_LPENR 0x50 50 #define STM32_RCC_AHB2_LPENR 0x54 51 #define STM32_RCC_AHB3_LPENR 0x58 52 53 #define STM32_RCC_APB1_LPENR 0x60 54 #define STM32_RCC_APB2_LPENR 0x64 55 56 #define STM32_RCC_BDCR 0x70 57 #define STM32_RCC_CSR 0x74 58 59 #define STM32_RCC_SSCGR 0x80 60 #define STM32_RCC_PLLI2SCFGR 0x84 61 #define STM32_RCC_PLLSAI_CFGR 0x88 62 #define STM32_RCC_DCKCFGR 0x8C 63 #define STM32_RCC_CKGATENR 0x90 64 #define STM32_RCC_DCKCFGR2 0x94 65 66 #define STM32_RCC_NREGS ((STM32_RCC_DCKCFGR2 >> 2) + 1) 67 #define STM32_RCC_PERIPHERAL_SIZE 0x400 68 #define STM32_RCC_NIRQS (32 * 5) /* 32 bits per reg, 5 en/rst regs */ 69 70 #define STM32_RCC_GPIO_IRQ_OFFSET 0 71 72 #define TYPE_STM32_RCC "stm32.rcc" 73 74 typedef struct STM32RccState STM32RccState; 75 76 DECLARE_INSTANCE_CHECKER(STM32RccState, STM32_RCC, TYPE_STM32_RCC) 77 78 #define NUM_GPIO_EVENT_IN_LINES 16 79 80 struct STM32RccState { 81 SysBusDevice parent_obj; 82 83 MemoryRegion mmio; 84 85 uint32_t regs[STM32_RCC_NREGS]; 86 87 qemu_irq enable_irq[STM32_RCC_NIRQS]; 88 qemu_irq reset_irq[STM32_RCC_NIRQS]; 89 }; 90 91 #endif /* HW_STM32_RCC_H */ 92