xref: /openbmc/qemu/include/hw/misc/sifive_u_prci.h (revision ef5c8d0b)
1 /*
2  * QEMU SiFive U PRCI (Power, Reset, Clock, Interrupt) interface
3  *
4  * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2 or later, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License along with
16  * this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18 
19 #ifndef HW_SIFIVE_U_PRCI_H
20 #define HW_SIFIVE_U_PRCI_H
21 
22 #include "hw/sysbus.h"
23 
24 #define SIFIVE_U_PRCI_HFXOSCCFG     0x00
25 #define SIFIVE_U_PRCI_COREPLLCFG0   0x04
26 #define SIFIVE_U_PRCI_DDRPLLCFG0    0x0C
27 #define SIFIVE_U_PRCI_DDRPLLCFG1    0x10
28 #define SIFIVE_U_PRCI_GEMGXLPLLCFG0 0x1C
29 #define SIFIVE_U_PRCI_GEMGXLPLLCFG1 0x20
30 #define SIFIVE_U_PRCI_CORECLKSEL    0x24
31 #define SIFIVE_U_PRCI_DEVICESRESET  0x28
32 #define SIFIVE_U_PRCI_CLKMUXSTATUS  0x2C
33 
34 /*
35  * Current FU540-C000 manual says ready bit is at bit 29, but
36  * freedom-u540-c000-bootloader codes (ux00prci.h) says it is at bit 31.
37  * We have to trust the actual code that works.
38  *
39  * see https://github.com/sifive/freedom-u540-c000-bootloader
40  */
41 
42 #define SIFIVE_U_PRCI_HFXOSCCFG_EN  (1 << 30)
43 #define SIFIVE_U_PRCI_HFXOSCCFG_RDY (1 << 31)
44 
45 /* xxxPLLCFG0 register bits */
46 #define SIFIVE_U_PRCI_PLLCFG0_DIVR  (1 << 0)
47 #define SIFIVE_U_PRCI_PLLCFG0_DIVF  (31 << 6)
48 #define SIFIVE_U_PRCI_PLLCFG0_DIVQ  (3 << 15)
49 #define SIFIVE_U_PRCI_PLLCFG0_FSE   (1 << 25)
50 #define SIFIVE_U_PRCI_PLLCFG0_LOCK  (1 << 31)
51 
52 /* xxxPLLCFG1 register bits */
53 #define SIFIVE_U_PRCI_PLLCFG1_CKE   (1 << 24)
54 
55 /* coreclksel register bits */
56 #define SIFIVE_U_PRCI_CORECLKSEL_HFCLK  (1 << 0)
57 
58 
59 #define SIFIVE_U_PRCI_REG_SIZE  0x1000
60 
61 #define TYPE_SIFIVE_U_PRCI      "riscv.sifive.u.prci"
62 
63 typedef struct SiFiveUPRCIState SiFiveUPRCIState;
64 DECLARE_INSTANCE_CHECKER(SiFiveUPRCIState, SIFIVE_U_PRCI,
65                          TYPE_SIFIVE_U_PRCI)
66 
67 struct SiFiveUPRCIState {
68     /*< private >*/
69     SysBusDevice parent_obj;
70 
71     /*< public >*/
72     MemoryRegion mmio;
73     uint32_t hfxosccfg;
74     uint32_t corepllcfg0;
75     uint32_t ddrpllcfg0;
76     uint32_t ddrpllcfg1;
77     uint32_t gemgxlpllcfg0;
78     uint32_t gemgxlpllcfg1;
79     uint32_t coreclksel;
80     uint32_t devicesreset;
81     uint32_t clkmuxstatus;
82 };
83 
84 /*
85  * Clock indexes for use by Device Tree data and the PRCI driver.
86  *
87  * These values are from sifive-fu540-prci.h in the Linux kernel.
88  */
89 #define PRCI_CLK_COREPLL        0
90 #define PRCI_CLK_DDRPLL         1
91 #define PRCI_CLK_GEMGXLPLL      2
92 #define PRCI_CLK_TLCLK          3
93 
94 #endif /* HW_SIFIVE_U_PRCI_H */
95